22 #define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff))  macro
250 		val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]);  in uw2453_synth_set_channel()
252 		val = UW2453_REGWRITE(1, uw2453_std_synth[idx]);  in uw2453_synth_set_channel()
259 		UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS);  in uw2453_synth_set_channel()
267 	return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS);  in uw2453_write_vco_cfg()
273 		UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */  in uw2453_init_mode()
274 		UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */  in uw2453_init_mode()
275 		UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */  in uw2453_init_mode()
276 		UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */  in uw2453_init_mode()
293 		UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS);  in uw2453_set_tx_gain_level()
345 		UW2453_REGWRITE(4, 0x2b),    /* configure receiver gain */  in uw2453_init_hw()
346 		UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */  in uw2453_init_hw()
347 		UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */  in uw2453_init_hw()
348 		UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */  in uw2453_init_hw()
352 		UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */  in uw2453_init_hw()
355 		UW2453_REGWRITE(1, 0x47),  in uw2453_init_hw()
356 		UW2453_REGWRITE(2, 0x999),  in uw2453_init_hw()
359 		UW2453_REGWRITE(3, 0x7602),  in uw2453_init_hw()
362 		UW2453_REGWRITE(3, 0x46063),  in uw2453_init_hw()
478 	r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS);  in uw2453_switch_radio_on()
498 	r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS);  in uw2453_switch_radio_off()