Lines Matching full:u8
19 u8 ref_clock;
20 u8 settling_time;
21 u8 clk_valid_on_wakeup;
22 u8 dc2dc_mode;
23 u8 dual_mode_select;
24 u8 tx_bip_fem_auto_detect;
25 u8 tx_bip_fem_manufacturer;
26 u8 general_settings;
27 u8 sr_state;
28 u8 srf1[WL1271_INI_MAX_SMART_REFLEX_PARAM];
29 u8 srf2[WL1271_INI_MAX_SMART_REFLEX_PARAM];
30 u8 srf3[WL1271_INI_MAX_SMART_REFLEX_PARAM];
36 u8 ref_clock;
37 u8 settling_time;
38 u8 clk_valid_on_wakeup;
39 u8 tcxo_ref_clock;
40 u8 tcxo_settling_time;
41 u8 tcxo_valid_on_wakeup;
42 u8 tcxo_ldo_voltage;
43 u8 xtal_itrim_val;
44 u8 platform_conf;
45 u8 dual_mode_select;
46 u8 tx_bip_fem_auto_detect;
47 u8 tx_bip_fem_manufacturer;
48 u8 general_settings[WL128X_INI_MAX_SETTINGS_PARAM];
49 u8 sr_state;
50 u8 srf1[WL1271_INI_MAX_SMART_REFLEX_PARAM];
51 u8 srf2[WL1271_INI_MAX_SMART_REFLEX_PARAM];
52 u8 srf3[WL1271_INI_MAX_SMART_REFLEX_PARAM];
58 u8 rx_trace_insertion_loss;
59 u8 tx_trace_loss;
60 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
66 u8 rx_trace_insertion_loss;
67 u8 tx_trace_loss[WL1271_INI_CHANNEL_COUNT_2];
68 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
75 u8 tx_bip_ref_power;
76 u8 tx_bip_ref_offset;
77 u8 tx_per_rate_pwr_limits_normal[WL1271_INI_RATE_GROUP_COUNT];
78 u8 tx_per_rate_pwr_limits_degraded[WL1271_INI_RATE_GROUP_COUNT];
79 u8 tx_per_rate_pwr_limits_extreme[WL1271_INI_RATE_GROUP_COUNT];
80 u8 tx_per_chan_pwr_limits_11b[WL1271_INI_CHANNEL_COUNT_2];
81 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_2];
82 u8 tx_pd_vs_rate_offsets[WL1271_INI_RATE_GROUP_COUNT];
83 u8 tx_ibias[WL1271_INI_RATE_GROUP_COUNT];
84 u8 rx_fem_insertion_loss;
85 u8 degraded_low_to_normal_thr;
86 u8 normal_to_degraded_high_thr;
95 u8 tx_bip_ref_power;
96 u8 tx_bip_ref_offset;
97 u8 tx_per_rate_pwr_limits_normal[WL128X_INI_RATE_GROUP_COUNT];
98 u8 tx_per_rate_pwr_limits_degraded[WL128X_INI_RATE_GROUP_COUNT];
99 u8 tx_per_rate_pwr_limits_extreme[WL128X_INI_RATE_GROUP_COUNT];
100 u8 tx_per_chan_pwr_limits_11b[WL1271_INI_CHANNEL_COUNT_2];
101 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_2];
102 u8 tx_pd_vs_rate_offsets[WL128X_INI_RATE_GROUP_COUNT];
103 u8 tx_ibias[WL128X_INI_RATE_GROUP_COUNT + 1];
104 u8 tx_pd_vs_chan_offsets[WL1271_INI_CHANNEL_COUNT_2];
105 u8 tx_pd_vs_temperature[WL128X_INI_PD_VS_TEMPERATURE_RANGES];
106 u8 rx_fem_insertion_loss;
107 u8 degraded_low_to_normal_thr;
108 u8 normal_to_degraded_high_thr;
115 u8 rx_trace_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
116 u8 tx_trace_loss[WL1271_INI_SUB_BAND_COUNT_5];
117 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
121 u8 rx_trace_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
122 u8 tx_trace_loss[WL1271_INI_CHANNEL_COUNT_5];
123 u8 rx_rssi_process_compens[WL1271_INI_RSSI_PROCESS_COMPENS_SIZE];
128 u8 tx_bip_ref_power[WL1271_INI_SUB_BAND_COUNT_5];
129 u8 tx_bip_ref_offset[WL1271_INI_SUB_BAND_COUNT_5];
130 u8 tx_per_rate_pwr_limits_normal[WL1271_INI_RATE_GROUP_COUNT];
131 u8 tx_per_rate_pwr_limits_degraded[WL1271_INI_RATE_GROUP_COUNT];
132 u8 tx_per_rate_pwr_limits_extreme[WL1271_INI_RATE_GROUP_COUNT];
133 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_5];
134 u8 tx_pd_vs_rate_offsets[WL1271_INI_RATE_GROUP_COUNT];
135 u8 tx_ibias[WL1271_INI_RATE_GROUP_COUNT];
136 u8 rx_fem_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
137 u8 degraded_low_to_normal_thr;
138 u8 normal_to_degraded_high_thr;
143 u8 tx_bip_ref_power[WL1271_INI_SUB_BAND_COUNT_5];
144 u8 tx_bip_ref_offset[WL1271_INI_SUB_BAND_COUNT_5];
145 u8 tx_per_rate_pwr_limits_normal[WL128X_INI_RATE_GROUP_COUNT];
146 u8 tx_per_rate_pwr_limits_degraded[WL128X_INI_RATE_GROUP_COUNT];
147 u8 tx_per_rate_pwr_limits_extreme[WL128X_INI_RATE_GROUP_COUNT];
148 u8 tx_per_chan_pwr_limits_ofdm[WL1271_INI_CHANNEL_COUNT_5];
149 u8 tx_pd_vs_rate_offsets[WL128X_INI_RATE_GROUP_COUNT];
150 u8 tx_ibias[WL128X_INI_RATE_GROUP_COUNT];
151 u8 tx_pd_vs_chan_offsets[WL1271_INI_CHANNEL_COUNT_5];
152 u8 tx_pd_vs_temperature[WL1271_INI_SUB_BAND_COUNT_5 *
154 u8 rx_fem_insertion_loss[WL1271_INI_SUB_BAND_COUNT_5];
155 u8 degraded_low_to_normal_thr;
156 u8 normal_to_degraded_high_thr;
179 u8 nvs[WL1271_INI_NVS_SECTION_SIZE];
183 u8 padding1;
185 u8 padding2;
188 u8 padding;
191 u8 padding3;
194 u8 padding;
200 u8 nvs[WL1271_INI_NVS_SECTION_SIZE];
204 u8 fem_vendor_and_options;
206 u8 padding2;
209 u8 padding;
212 u8 padding3;
215 u8 padding;