Lines Matching +full:tx +full:- +full:clk +full:- +full:10 +full:- +full:inverted
1 // SPDX-License-Identifier: GPL-2.0-only
20 #include "../wlcore/tx.h"
28 #include "tx.h"
40 static int num_rx_desc_param = -1;
43 static int dc2dc_param = -1;
44 static int n_antennas_2_param = -1;
45 static int n_antennas_5_param = -1;
46 static int low_band_component_param = -1;
47 static int low_band_component_type_param = -1;
48 static int high_band_component_param = -1;
49 static int high_band_component_type_param = -1;
50 static int pwr_limit_reference_11_abg_param = -1;
59 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
72 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
76 /* TI-specific rate */
96 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
113 /* TI-specific rate */
256 .tx = {
260 .short_retry_limit = 10,
261 .long_retry_limit = 10,
334 .tx_compl_threshold = 10,
337 .tmpl_short_retry_limit = 10,
338 .tmpl_long_retry_limit = 10,
369 .ps_poll_threshold = 10,
393 .avg_weight_rssi_data = 10,
395 .avg_weight_snr_data = 10,
421 .rssi_threshold = -90,
476 .tx_fail_high_th = 10,
479 .per_beta1_shift = 10,
638 [CLOCK_CONFIG_19_2_M] = { 10, 128, 0, 0, false },
642 [CLOCK_CONFIG_38_468_M] = { 10, 128, 0, 0, false },
659 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-4.bin"
665 switch (wl->chip.id) { in wl18xx_identify_chip()
668 wl->chip.id); in wl18xx_identify_chip()
669 wl->sr_fw_name = WL18XX_FW_NAME; in wl18xx_identify_chip()
671 wl->plt_fw_name = WL18XX_FW_NAME; in wl18xx_identify_chip()
672 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN | in wl18xx_identify_chip()
682 /* there's no separate multi-role FW */ in wl18xx_identify_chip()
687 wl->chip.id); in wl18xx_identify_chip()
688 ret = -ENODEV; in wl18xx_identify_chip()
692 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id); in wl18xx_identify_chip()
693 ret = -ENODEV; in wl18xx_identify_chip()
697 wl->fw_mem_block_size = 272; in wl18xx_identify_chip()
698 wl->fwlog_end = 0x40000000; in wl18xx_identify_chip()
700 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4; in wl18xx_identify_chip()
701 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5; in wl18xx_identify_chip()
702 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC; in wl18xx_identify_chip()
703 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC; in wl18xx_identify_chip()
704 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ; in wl18xx_identify_chip()
705 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS; in wl18xx_identify_chip()
715 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_set_clk()
719 /* TODO: PG2: apparently we need to read the clk type */ in wl18xx_set_clk()
822 /* disable Rx/Tx */ in wl18xx_boot_soft_reset()
849 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_pre_boot()
873 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_pre_upload()
899 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_pre_upload()
915 /* re-enable FDSP clock */ in wl18xx_pre_upload()
921 ret = irq_get_trigger_type(wl->irq); in wl18xx_pre_upload()
923 wl1271_info("using inverted interrupt logic: %d", ret); in wl18xx_pre_upload()
925 &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_pre_upload()
938 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_pre_upload()
947 struct wl18xx_priv *priv = wl->priv; in wl18xx_set_mac_and_phy()
951 params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL); in wl18xx_set_mac_and_phy()
953 ret = -ENOMEM; in wl18xx_set_mac_and_phy()
957 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]); in wl18xx_set_mac_and_phy()
1017 wl->event_mask = BSS_LOSS_EVENT_ID | in wl18xx_boot()
1036 wl->ap_event_mask = MAX_TX_FAILURE_EVENT_ID; in wl18xx_boot()
1051 struct wl18xx_priv *priv = wl->priv; in wl18xx_trigger_cmd()
1053 memcpy(priv->cmd_buf, buf, len); in wl18xx_trigger_cmd()
1054 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len); in wl18xx_trigger_cmd()
1056 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf, in wl18xx_trigger_cmd()
1069 return (len + blk_size - 1) / blk_size + spare_blks; in wl18xx_calc_tx_blocks()
1076 desc->wl18xx_mem.total_mem_blocks = blks; in wl18xx_set_tx_desc_blocks()
1083 desc->length = cpu_to_le16(skb->len); in wl18xx_set_tx_desc_data_len()
1085 /* if only the last frame is to be padded, we unset this bit on Tx */ in wl18xx_set_tx_desc_data_len()
1086 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) in wl18xx_set_tx_desc_data_len()
1087 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED; in wl18xx_set_tx_desc_data_len()
1089 desc->wl18xx_mem.ctrl = 0; in wl18xx_set_tx_desc_data_len()
1092 "len: %d life: %d mem: %d", desc->hlid, in wl18xx_set_tx_desc_data_len()
1093 le16_to_cpu(desc->length), in wl18xx_set_tx_desc_data_len()
1094 le16_to_cpu(desc->life_time), in wl18xx_set_tx_desc_data_len()
1095 desc->wl18xx_mem.total_mem_blocks); in wl18xx_set_tx_desc_data_len()
1116 return data_len - sizeof(*desc); in wl18xx_get_rx_packet_len()
1131 /* Enable Tx SDIO padding */ in wl18xx_set_host_cfg_bitmap()
1132 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) { in wl18xx_set_host_cfg_bitmap()
1138 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) { in wl18xx_set_host_cfg_bitmap()
1155 struct wl18xx_priv *priv = wl->priv; in wl18xx_hw_init()
1158 priv->last_fw_rls_idx = 0; in wl18xx_hw_init()
1159 priv->extra_spare_key_count = 0; in wl18xx_hw_init()
1186 fw_status->intr = le32_to_cpu(int_fw_status->intr); in wl18xx_convert_fw_status_8_9_1()
1187 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter; in wl18xx_convert_fw_status_8_9_1()
1188 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter; in wl18xx_convert_fw_status_8_9_1()
1189 fw_status->tx_results_counter = int_fw_status->tx_results_counter; in wl18xx_convert_fw_status_8_9_1()
1190 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs; in wl18xx_convert_fw_status_8_9_1()
1192 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime); in wl18xx_convert_fw_status_8_9_1()
1193 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap); in wl18xx_convert_fw_status_8_9_1()
1194 fw_status->link_fast_bitmap = in wl18xx_convert_fw_status_8_9_1()
1195 le32_to_cpu(int_fw_status->link_fast_bitmap); in wl18xx_convert_fw_status_8_9_1()
1196 fw_status->total_released_blks = in wl18xx_convert_fw_status_8_9_1()
1197 le32_to_cpu(int_fw_status->total_released_blks); in wl18xx_convert_fw_status_8_9_1()
1198 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total); in wl18xx_convert_fw_status_8_9_1()
1200 fw_status->counters.tx_released_pkts = in wl18xx_convert_fw_status_8_9_1()
1201 int_fw_status->counters.tx_released_pkts; in wl18xx_convert_fw_status_8_9_1()
1202 fw_status->counters.tx_lnk_free_pkts = in wl18xx_convert_fw_status_8_9_1()
1203 int_fw_status->counters.tx_lnk_free_pkts; in wl18xx_convert_fw_status_8_9_1()
1204 fw_status->counters.tx_lnk_sec_pn16 = in wl18xx_convert_fw_status_8_9_1()
1205 int_fw_status->counters.tx_lnk_sec_pn16; in wl18xx_convert_fw_status_8_9_1()
1206 fw_status->counters.tx_voice_released_blks = in wl18xx_convert_fw_status_8_9_1()
1207 int_fw_status->counters.tx_voice_released_blks; in wl18xx_convert_fw_status_8_9_1()
1208 fw_status->counters.tx_last_rate = in wl18xx_convert_fw_status_8_9_1()
1209 int_fw_status->counters.tx_last_rate; in wl18xx_convert_fw_status_8_9_1()
1210 fw_status->counters.tx_last_rate_mbps = in wl18xx_convert_fw_status_8_9_1()
1211 int_fw_status->counters.tx_last_rate_mbps; in wl18xx_convert_fw_status_8_9_1()
1212 fw_status->counters.hlid = in wl18xx_convert_fw_status_8_9_1()
1213 int_fw_status->counters.hlid; in wl18xx_convert_fw_status_8_9_1()
1215 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr); in wl18xx_convert_fw_status_8_9_1()
1217 fw_status->priv = &int_fw_status->priv; in wl18xx_convert_fw_status_8_9_1()
1226 fw_status->intr = le32_to_cpu(int_fw_status->intr); in wl18xx_convert_fw_status_8_9_0()
1227 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter; in wl18xx_convert_fw_status_8_9_0()
1228 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter; in wl18xx_convert_fw_status_8_9_0()
1229 fw_status->tx_results_counter = int_fw_status->tx_results_counter; in wl18xx_convert_fw_status_8_9_0()
1230 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs; in wl18xx_convert_fw_status_8_9_0()
1232 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime); in wl18xx_convert_fw_status_8_9_0()
1233 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap); in wl18xx_convert_fw_status_8_9_0()
1234 fw_status->link_fast_bitmap = in wl18xx_convert_fw_status_8_9_0()
1235 le32_to_cpu(int_fw_status->link_fast_bitmap); in wl18xx_convert_fw_status_8_9_0()
1236 fw_status->total_released_blks = in wl18xx_convert_fw_status_8_9_0()
1237 le32_to_cpu(int_fw_status->total_released_blks); in wl18xx_convert_fw_status_8_9_0()
1238 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total); in wl18xx_convert_fw_status_8_9_0()
1240 fw_status->counters.tx_released_pkts = in wl18xx_convert_fw_status_8_9_0()
1241 int_fw_status->counters.tx_released_pkts; in wl18xx_convert_fw_status_8_9_0()
1242 fw_status->counters.tx_lnk_free_pkts = in wl18xx_convert_fw_status_8_9_0()
1243 int_fw_status->counters.tx_lnk_free_pkts; in wl18xx_convert_fw_status_8_9_0()
1244 fw_status->counters.tx_voice_released_blks = in wl18xx_convert_fw_status_8_9_0()
1245 int_fw_status->counters.tx_voice_released_blks; in wl18xx_convert_fw_status_8_9_0()
1246 fw_status->counters.tx_last_rate = in wl18xx_convert_fw_status_8_9_0()
1247 int_fw_status->counters.tx_last_rate; in wl18xx_convert_fw_status_8_9_0()
1248 fw_status->counters.tx_last_rate_mbps = in wl18xx_convert_fw_status_8_9_0()
1249 int_fw_status->counters.tx_last_rate_mbps; in wl18xx_convert_fw_status_8_9_0()
1250 fw_status->counters.hlid = in wl18xx_convert_fw_status_8_9_0()
1251 int_fw_status->counters.hlid; in wl18xx_convert_fw_status_8_9_0()
1253 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr); in wl18xx_convert_fw_status_8_9_0()
1255 fw_status->priv = &int_fw_status->priv; in wl18xx_convert_fw_status_8_9_0()
1261 if (wl->chip.fw_ver[FW_VER_MAJOR] == 0) in wl18xx_convert_fw_status()
1275 desc->wl18xx_checksum_data = 0; in wl18xx_set_tx_desc_csum()
1279 if (skb->ip_summed != CHECKSUM_PARTIAL) { in wl18xx_set_tx_desc_csum()
1280 desc->wl18xx_checksum_data = 0; in wl18xx_set_tx_desc_csum()
1284 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb); in wl18xx_set_tx_desc_csum()
1286 desc->wl18xx_checksum_data = 0; in wl18xx_set_tx_desc_csum()
1290 desc->wl18xx_checksum_data = ip_hdr_offset << 1; in wl18xx_set_tx_desc_csum()
1294 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01); in wl18xx_set_tx_desc_csum()
1301 if (desc->status & WL18XX_RX_CHECKSUM_MASK) in wl18xx_set_rx_csum()
1302 skb->ip_summed = CHECKSUM_UNNECESSARY; in wl18xx_set_rx_csum()
1307 struct wl18xx_priv *priv = wl->priv; in wl18xx_is_mimo_supported()
1312 return (priv->conf.phy.number_of_assembled_ant2_4 >= 2) && in wl18xx_is_mimo_supported()
1313 (priv->conf.ht.mode != HT_MODE_WIDE) && in wl18xx_is_mimo_supported()
1314 (priv->conf.ht.mode != HT_MODE_SISO20); in wl18xx_is_mimo_supported()
1319 * we should modify the wlvif->rate_set instead
1324 u32 hw_rate_set = wlvif->rate_set; in wl18xx_sta_get_ap_rate_mask()
1326 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS || in wl18xx_sta_get_ap_rate_mask()
1327 wlvif->channel_type == NL80211_CHAN_HT40PLUS) { in wl18xx_sta_get_ap_rate_mask()
1331 /* we don't support MIMO in wide-channel mode */ in wl18xx_sta_get_ap_rate_mask()
1344 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS || in wl18xx_ap_get_mimo_wide_rate_mask()
1345 wlvif->channel_type == NL80211_CHAN_HT40PLUS) { in wl18xx_ap_get_mimo_wide_rate_mask()
1348 /* sanity check - we don't support this */ in wl18xx_ap_get_mimo_wide_rate_mask()
1349 if (WARN_ON(wlvif->band != NL80211_BAND_5GHZ)) in wl18xx_ap_get_mimo_wide_rate_mask()
1354 wlvif->band == NL80211_BAND_2GHZ) { in wl18xx_ap_get_mimo_wide_rate_mask()
1357 * we don't care about HT channel here - if a peer doesn't in wl18xx_ap_get_mimo_wide_rate_mask()
1378 return "RDL11 - Not Supported"; in wl18xx_rdl_name()
1382 return "RDL13 - Not Supported (1893Q)"; in wl18xx_rdl_name()
1398 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_get_pg_ver()
1434 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]); in wl18xx_get_pg_ver()
1455 if (fw->size != WL18XX_CONF_SIZE) { in wl18xx_load_conf_file()
1457 file, WL18XX_CONF_SIZE, fw->size); in wl18xx_load_conf_file()
1458 ret = -EINVAL; in wl18xx_load_conf_file()
1462 conf_file = (struct wlcore_conf_file *) fw->data; in wl18xx_load_conf_file()
1464 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) { in wl18xx_load_conf_file()
1467 conf_file->header.magic); in wl18xx_load_conf_file()
1468 ret = -EINVAL; in wl18xx_load_conf_file()
1472 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) { in wl18xx_load_conf_file()
1475 WL18XX_CONF_VERSION, conf_file->header.version); in wl18xx_load_conf_file()
1476 ret = -EINVAL; in wl18xx_load_conf_file()
1480 memcpy(conf, &conf_file->core, sizeof(*conf)); in wl18xx_load_conf_file()
1481 memcpy(priv_conf, &conf_file->priv, sizeof(*priv_conf)); in wl18xx_load_conf_file()
1490 struct platform_device *pdev = wl->pdev; in wl18xx_conf_init()
1491 struct wlcore_platdev_data *pdata = dev_get_platdata(&pdev->dev); in wl18xx_conf_init()
1492 struct wl18xx_priv *priv = wl->priv; in wl18xx_conf_init()
1494 if (wl18xx_load_conf_file(dev, &wl->conf, &priv->conf, in wl18xx_conf_init()
1495 pdata->family->cfg_name) < 0) { in wl18xx_conf_init()
1499 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl->conf)); in wl18xx_conf_init()
1501 memcpy(&priv->conf, &wl18xx_default_priv_conf, in wl18xx_conf_init()
1502 sizeof(priv->conf)); in wl18xx_conf_init()
1513 if (wl->plt_mode == PLT_FEM_DETECT) { in wl18xx_plt_init()
1515 return -EINVAL; in wl18xx_plt_init()
1522 return wl->ops->boot(wl); in wl18xx_plt_init()
1530 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]); in wl18xx_get_mac()
1543 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) + in wl18xx_get_mac()
1545 wl->fuse_nic_addr = (mac1 & 0xffffff); in wl18xx_get_mac()
1547 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) { in wl18xx_get_mac()
1552 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2]; in wl18xx_get_mac()
1553 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5]; in wl18xx_get_mac()
1557 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]); in wl18xx_get_mac()
1567 (struct wl18xx_static_data_priv *) static_data->priv; in wl18xx_handle_static_data()
1570 strscpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version, in wl18xx_handle_static_data()
1571 sizeof(wl->chip.phy_fw_ver_str)); in wl18xx_handle_static_data()
1573 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version); in wl18xx_handle_static_data()
1576 if (wl->chip.fw_ver[FW_VER_MAJOR] == 0) in wl18xx_handle_static_data()
1581 if (wl->fw_status_len != fw_status_len) { in wl18xx_handle_static_data()
1582 void *new_status = krealloc(wl->raw_fw_status, fw_status_len, in wl18xx_handle_static_data()
1585 return -ENOMEM; in wl18xx_handle_static_data()
1587 wl->raw_fw_status = new_status; in wl18xx_handle_static_data()
1588 wl->fw_status_len = fw_status_len; in wl18xx_handle_static_data()
1596 struct wl18xx_priv *priv = wl->priv; in wl18xx_get_spare_blocks()
1599 if (priv->extra_spare_key_count) in wl18xx_get_spare_blocks()
1610 struct wl18xx_priv *priv = wl->priv; in wl18xx_set_key()
1615 priv->extra_spare_key_count); in wl18xx_set_key()
1617 special_enc = key_conf->cipher == WL1271_CIPHER_SUITE_GEM || in wl18xx_set_key()
1618 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP; in wl18xx_set_key()
1631 change_spare = (priv->extra_spare_key_count == 0); in wl18xx_set_key()
1632 priv->extra_spare_key_count++; in wl18xx_set_key()
1635 change_spare = (priv->extra_spare_key_count == 1); in wl18xx_set_key()
1636 priv->extra_spare_key_count--; in wl18xx_set_key()
1641 priv->extra_spare_key_count); in wl18xx_set_key()
1647 if (priv->extra_spare_key_count) in wl18xx_set_key()
1661 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) { in wl18xx_pre_pkt_send()
1664 /* get the last TX HW descriptor written to the aggr buf */ in wl18xx_pre_pkt_send()
1665 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf + in wl18xx_pre_pkt_send()
1666 buf_offset - last_len); in wl18xx_pre_pkt_send()
1669 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED; in wl18xx_pre_pkt_send()
1680 bool wide = wlvif->rc_update_bw >= IEEE80211_STA_RX_BW_40; in wl18xx_sta_rc_update()
1685 if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS)) in wl18xx_sta_rc_update()
1689 if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags)) in wl18xx_sta_rc_update()
1696 if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS || in wl18xx_sta_rc_update()
1697 wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS) in wl18xx_sta_rc_update()
1698 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide); in wl18xx_sta_rc_update()
1717 (struct wl18xx_fw_status_priv *)wl->fw_status->priv; in wl18xx_lnk_high_prio()
1725 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap); in wl18xx_lnk_high_prio()
1730 if (test_bit(hlid, &wl->fw_fast_lnk_map) && in wl18xx_lnk_high_prio()
1731 !test_bit(hlid, &wl->ap_fw_ps_map)) in wl18xx_lnk_high_prio()
1732 thold = status_priv->tx_fast_link_prio_threshold; in wl18xx_lnk_high_prio()
1734 thold = status_priv->tx_slow_link_prio_threshold; in wl18xx_lnk_high_prio()
1736 return lnk->allocated_pkts < thold; in wl18xx_lnk_high_prio()
1744 (struct wl18xx_fw_status_priv *)wl->fw_status->priv; in wl18xx_lnk_low_prio()
1751 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap); in wl18xx_lnk_low_prio()
1753 thold = status_priv->tx_suspend_threshold; in wl18xx_lnk_low_prio()
1754 else if (test_bit(hlid, &wl->fw_fast_lnk_map) && in wl18xx_lnk_low_prio()
1755 !test_bit(hlid, &wl->ap_fw_ps_map)) in wl18xx_lnk_low_prio()
1756 thold = status_priv->tx_fast_stop_threshold; in wl18xx_lnk_low_prio()
1758 thold = status_priv->tx_slow_stop_threshold; in wl18xx_lnk_low_prio()
1760 return lnk->allocated_pkts < thold; in wl18xx_lnk_low_prio()
1936 struct wl18xx_priv *priv = wl->priv; in wl18xx_setup()
1943 wl->rtable = wl18xx_rtable; in wl18xx_setup()
1944 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS; in wl18xx_setup()
1945 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS; in wl18xx_setup()
1946 wl->num_links = WL18XX_MAX_LINKS; in wl18xx_setup()
1947 wl->max_ap_stations = WL18XX_MAX_AP_STATIONS; in wl18xx_setup()
1948 wl->iface_combinations = wl18xx_iface_combinations; in wl18xx_setup()
1949 wl->n_iface_combinations = ARRAY_SIZE(wl18xx_iface_combinations); in wl18xx_setup()
1950 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES; in wl18xx_setup()
1951 wl->band_rate_to_idx = wl18xx_band_rate_to_idx; in wl18xx_setup()
1952 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX; in wl18xx_setup()
1953 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0; in wl18xx_setup()
1954 wl->fw_status_len = sizeof(struct wl18xx_fw_status); in wl18xx_setup()
1955 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv); in wl18xx_setup()
1956 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics); in wl18xx_setup()
1957 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv); in wl18xx_setup()
1959 if (num_rx_desc_param != -1) in wl18xx_setup()
1960 wl->num_rx_desc = num_rx_desc_param; in wl18xx_setup()
1962 ret = wl18xx_conf_init(wl, wl->dev); in wl18xx_setup()
1969 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX; in wl18xx_setup()
1971 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX; in wl18xx_setup()
1973 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX; in wl18xx_setup()
1975 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX; in wl18xx_setup()
1977 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX; in wl18xx_setup()
1981 return -EINVAL; in wl18xx_setup()
1985 if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) { in wl18xx_setup()
1987 priv->conf.phy.board_type); in wl18xx_setup()
1988 return -EINVAL; in wl18xx_setup()
1991 if (low_band_component_param != -1) in wl18xx_setup()
1992 priv->conf.phy.low_band_component = low_band_component_param; in wl18xx_setup()
1993 if (low_band_component_type_param != -1) in wl18xx_setup()
1994 priv->conf.phy.low_band_component_type = in wl18xx_setup()
1996 if (high_band_component_param != -1) in wl18xx_setup()
1997 priv->conf.phy.high_band_component = high_band_component_param; in wl18xx_setup()
1998 if (high_band_component_type_param != -1) in wl18xx_setup()
1999 priv->conf.phy.high_band_component_type = in wl18xx_setup()
2001 if (pwr_limit_reference_11_abg_param != -1) in wl18xx_setup()
2002 priv->conf.phy.pwr_limit_reference_11_abg = in wl18xx_setup()
2004 if (n_antennas_2_param != -1) in wl18xx_setup()
2005 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param; in wl18xx_setup()
2006 if (n_antennas_5_param != -1) in wl18xx_setup()
2007 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param; in wl18xx_setup()
2008 if (dc2dc_param != -1) in wl18xx_setup()
2009 priv->conf.phy.external_pa_dc2dc = dc2dc_param; in wl18xx_setup()
2013 priv->conf.ht.mode = HT_MODE_DEFAULT; in wl18xx_setup()
2015 priv->conf.ht.mode = HT_MODE_WIDE; in wl18xx_setup()
2017 priv->conf.ht.mode = HT_MODE_SISO20; in wl18xx_setup()
2020 return -EINVAL; in wl18xx_setup()
2024 if (priv->conf.ht.mode == HT_MODE_DEFAULT) { in wl18xx_setup()
2039 } else if (priv->conf.ht.mode == HT_MODE_WIDE) { in wl18xx_setup()
2044 } else if (priv->conf.ht.mode == HT_MODE_SISO20) { in wl18xx_setup()
2057 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0); in wl18xx_setup()
2077 wl = hw->priv; in wl18xx_probe()
2078 wl->ops = &wl18xx_ops; in wl18xx_probe()
2079 wl->ptable = wl18xx_ptable; in wl18xx_probe()