Lines Matching +full:0 +full:x6040
16 #define REGISTERS_BASE 0x00300000
17 #define DRPW_BASE 0x00310000
19 #define REGISTERS_DOWN_SIZE 0x00008800
20 #define REGISTERS_WORK_SIZE 0x0000b000
22 #define FW_STATUS_ADDR (0x14FC0 + 0xA000)
28 0 SOFT_RESET Soft Reset - When this bit is set,
38 #define WL12XX_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
40 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
41 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
42 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
44 #define WL12XX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
45 #define WL12XX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
52 0 - RX0 - Rx first dubble buffer Data Interrupt
73 Default: 0x0001
75 #define WL12XX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
83 state of other bits (0 = no effect).
85 #define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
93 state of other bits (0 = no effect).
95 #define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
106 #define WL12XX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
117 #define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
127 assotiated interrupt inactive. (0-no effect)
129 #define WL12XX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
131 #define WL12XX_REG_RX_DRIVER_COUNTER (REGISTERS_BASE + 0x0538)
134 #define SOR_CFG (REGISTERS_BASE + 0x0800)
141 0 HALT_ECPU Halt Embedded CPU - This bit is the
154 0 enable eCPU
156 #define WL12XX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
158 #define WL12XX_HI_CFG (REGISTERS_BASE + 0x0808)
164 0 ACX_EE_START - EEPROM Burst Read Start 0
168 the burst read starts at EEPROM address 0.
173 Default: 0x00000000
175 #define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
177 #define WL12XX_OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
178 #define WL12XX_OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
179 #define WL12XX_OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
180 #define WL12XX_OCP_CMD (REGISTERS_BASE + 0x09C0)
182 #define WL12XX_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
184 #define WL12XX_CHIP_ID_B (REGISTERS_BASE + 0x5674)
186 #define WL12XX_ENABLE (REGISTERS_BASE + 0x5450)
189 #define WL12XX_ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
190 #define WL12XX_ELP_CMD (REGISTERS_BASE + 0x5808)
191 #define WL12XX_PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
192 #define WL12XX_CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
193 #define WL12XX_CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
195 #define WL12XX_CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
198 #define WL12XX_SCR_PAD0 (REGISTERS_BASE + 0x5608)
199 #define WL12XX_SCR_PAD1 (REGISTERS_BASE + 0x560C)
200 #define WL12XX_SCR_PAD2 (REGISTERS_BASE + 0x5610)
201 #define WL12XX_SCR_PAD3 (REGISTERS_BASE + 0x5614)
202 #define WL12XX_SCR_PAD4 (REGISTERS_BASE + 0x5618)
203 #define WL12XX_SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
204 #define WL12XX_SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
205 #define WL12XX_SCR_PAD5 (REGISTERS_BASE + 0x5624)
206 #define WL12XX_SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
207 #define WL12XX_SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
208 #define WL12XX_SCR_PAD6 (REGISTERS_BASE + 0x5630)
209 #define WL12XX_SCR_PAD7 (REGISTERS_BASE + 0x5634)
210 #define WL12XX_SCR_PAD8 (REGISTERS_BASE + 0x5638)
211 #define WL12XX_SCR_PAD9 (REGISTERS_BASE + 0x563C)
214 #define WL12XX_SPARE_A1 (REGISTERS_BASE + 0x0994)
215 #define WL12XX_SPARE_A2 (REGISTERS_BASE + 0x0998)
216 #define WL12XX_SPARE_A3 (REGISTERS_BASE + 0x099C)
217 #define WL12XX_SPARE_A4 (REGISTERS_BASE + 0x09A0)
218 #define WL12XX_SPARE_A5 (REGISTERS_BASE + 0x09A4)
219 #define WL12XX_SPARE_A6 (REGISTERS_BASE + 0x09A8)
220 #define WL12XX_SPARE_A7 (REGISTERS_BASE + 0x09AC)
221 #define WL12XX_SPARE_A8 (REGISTERS_BASE + 0x09B0)
222 #define WL12XX_SPARE_B1 (REGISTERS_BASE + 0x5420)
223 #define WL12XX_SPARE_B2 (REGISTERS_BASE + 0x5424)
224 #define WL12XX_SPARE_B3 (REGISTERS_BASE + 0x5428)
225 #define WL12XX_SPARE_B4 (REGISTERS_BASE + 0x542C)
226 #define WL12XX_SPARE_B5 (REGISTERS_BASE + 0x5430)
227 #define WL12XX_SPARE_B6 (REGISTERS_BASE + 0x5434)
228 #define WL12XX_SPARE_B7 (REGISTERS_BASE + 0x5438)
229 #define WL12XX_SPARE_B8 (REGISTERS_BASE + 0x543C)
231 #define WL12XX_PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
232 #define WL12XX_WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
233 #define WL12XX_WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
234 #define WL12XX_DRPW_SCRATCH_START (DRPW_BASE + 0x002C)
236 #define WL12XX_CMD_MBOX_ADDRESS 0x407B4
282 0 EE_WRITE - EEPROM Write Request - Setting this bit
288 #define EE_WRITE 0x00000001ul
289 #define EE_READ 0x00000002ul
323 [15: 0] Specify the output values (at the output driver inputs) for
324 GPIO[15:0], respectively.
333 [25:16] Max (0x3ff)
335 [06:00] Current contention window value - default is 0x1F
338 #define ACX_CONT_WIND_MIN_MASK 0x0000007f
339 #define ACX_CONT_WIND_MAX 0x03ff0000
341 #define REF_FREQ_19_2 0
348 #define LUT_PARAM_INTEGER_DIVIDER 0
357 #define USE_EEPROM 0
369 #define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
374 CCK_LONG = 0,
389 b15 - Indicates Preamble type (1=SHORT, 0=LONG).
391 Must be LONG (0) for 1Mbps rate.
392 Does not apply (set to 0) for RevG-OFDM rates.
393 b14 - Indicates PBCC encoding (1=PBCC, 0=not).
395 Does not apply (set to 0) for rates 1 and 2 Mbps.
396 Does not apply (set to 0) for RevG-OFDM rates.
397 b13 - Unused (set to 0).
403 #define OCP_CMD_WRITE 0x1
404 #define OCP_CMD_READ 0x2
407 #define OCP_STATUS_NO_RESP 0x00000
408 #define OCP_STATUS_OK 0x10000
409 #define OCP_STATUS_REQ_FAILED 0x20000
410 #define OCP_STATUS_RESP_ERROR 0x30000
412 #define OCP_REG_POLARITY 0x0064
413 #define OCP_REG_CLK_TYPE 0x0448
414 #define OCP_REG_CLK_POLARITY 0x0cb2
415 #define OCP_REG_CLK_PULL 0x0cb4
420 #define FREF_CLK_TYPE_BITS 0xfffffe7f
421 #define CLK_REQ_PRCM 0x100
422 #define FREF_CLK_POLARITY_BITS 0xfffff8ff
423 #define CLK_REQ_OUTN_SEL 0x700
425 #define WU_COUNTER_PAUSE_VAL 0x3FF
428 #define SYS_CLK_CFG_REG 0x2200
429 /* Bit[0] - 0-TCXO, 1-FREF */
430 #define MCS_PLL_CLK_SEL_FREF BIT(0)
434 /* Bit[4] - 0-TCXO, 1-FREF */
437 #define TCXO_ILOAD_INT_REG 0x2264
438 #define TCXO_CLK_DETECT_REG 0x2266
442 #define FREF_ILOAD_INT_REG 0x2084
443 #define FREF_CLK_DETECT_REG 0x2086
447 #define WL_SPARE_REG 0x2320
452 #define PLL_LOCK_COUNTERS_REG 0xD8C
453 #define PLL_LOCK_COUNTERS_COEX 0x0F
454 #define PLL_LOCK_COUNTERS_MCS 0xF0
455 #define MCS_PLL_OVERRIDE_REG 0xD90
456 #define MCS_PLL_CONFIG_REG 0xD92
457 #define MCS_SEL_IN_FREQ_MASK 0x0070
459 #define MCS_PLL_CONFIG_REG_VAL 0x73
460 #define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1))
462 #define MCS_PLL_M_REG 0xD94
463 #define MCS_PLL_N_REG 0xD96
464 #define MCS_PLL_M_REG_VAL 0xC8
465 #define MCS_PLL_N_REG_VAL 0x07
467 #define SDIO_IO_DS 0xd14
471 HCI_IO_DS_8MA = 0,
485 #define WL12XX_INTR_TRIG_CMD BIT(0)
499 #define HI_CFG_UART_ENABLE 0x00000004
500 #define HI_CFG_RST232_ENABLE 0x00000008
501 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010
502 #define HI_CFG_HOST_INT_ENABLE 0x00000020
503 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
504 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
505 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
506 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
507 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
515 #define WL127X_REG_FUSE_DATA_2_1 0x050a
516 #define WL128X_REG_FUSE_DATA_2_1 0x2152
517 #define PG_VER_MASK 0x3c
520 #define WL127X_PG_MAJOR_VER_MASK 0x3
521 #define WL127X_PG_MAJOR_VER_OFFSET 0x0
522 #define WL127X_PG_MINOR_VER_MASK 0xc
523 #define WL127X_PG_MINOR_VER_OFFSET 0x2
525 #define WL128X_PG_MAJOR_VER_MASK 0xc
526 #define WL128X_PG_MAJOR_VER_OFFSET 0x2
527 #define WL128X_PG_MINOR_VER_MASK 0x3
528 #define WL128X_PG_MINOR_VER_OFFSET 0x0
539 #define WL12XX_REG_FUSE_BD_ADDR_1 0x00310eb4
540 #define WL12XX_REG_FUSE_BD_ADDR_2 0x00310eb8