Lines Matching +full:0 +full:x00f00000

33 #define CFG_ERR_SPI_FRAME          0x00000001 /* only with SPI */
34 #define CFG_ERR_SDIO_BUF_MISMATCH  0x00000001 /* only with SDIO */
35 #define CFG_ERR_BUF_UNDERRUN       0x00000002
36 #define CFG_ERR_DATA_IN_TOO_LARGE  0x00000004
37 #define CFG_ERR_HOST_NO_OUT_QUEUE  0x00000008
38 #define CFG_ERR_BUF_OVERRUN        0x00000010
39 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
40 #define CFG_ERR_HOST_NO_IN_QUEUE   0x00000040
41 #define CFG_ERR_HOST_CRC_MISS      0x00000080 /* only with SDIO */
42 #define CFG_SPI_IGNORE_CS          0x00000080 /* only with SPI */
43 #define CFG_BYTE_ORDER_MASK        0x00000300 /* only writable with SPI */
44 #define     CFG_BYTE_ORDER_BADC    0x00000000
45 #define     CFG_BYTE_ORDER_DCBA    0x00000100
46 #define     CFG_BYTE_ORDER_ABCD    0x00000200 /* SDIO always use this value */
47 #define CFG_DIRECT_ACCESS_MODE     0x00000400
48 #define CFG_PREFETCH_AHB           0x00000800
49 #define CFG_DISABLE_CPU_CLK        0x00001000
50 #define CFG_PREFETCH_SRAM          0x00002000
51 #define CFG_CPU_RESET              0x00004000
52 #define CFG_SDIO_DISABLE_IRQ       0x00008000 /* only with SDIO */
53 #define CFG_IRQ_ENABLE_DATA        0x00010000
54 #define CFG_IRQ_ENABLE_WRDY        0x00020000
55 #define CFG_CLK_RISE_EDGE          0x00040000
56 #define CFG_SDIO_DISABLE_CRC_CHK   0x00080000 /* only with SDIO */
57 #define CFG_RESERVED               0x00F00000
58 #define CFG_DEVICE_ID_MAJOR        0x07000000
59 #define CFG_DEVICE_ID_RESERVED     0x78000000
60 #define CFG_DEVICE_ID_TYPE         0x80000000
65 #define CTRL_NEXT_LEN_MASK   0x00000FFF
66 #define CTRL_WLAN_WAKEUP     0x00001000
67 #define CTRL_WLAN_READY      0x00002000
72 #define IGPR_RW          0x80000000
73 #define IGPR_INDEX       0x7F000000
74 #define IGPR_VALUE       0x00FFFFFF