Lines Matching +full:0 +full:x0013

32 	BUFFER_FULL         = 0x0,
33 	BUFFER_AVAILABLE    = 0x2,
34 	FIRMWARE_ASSERT_IND = 0x3,
35 	MSDU_PACKET_PENDING = 0x4,
36 	UNKNOWN_INT         = 0XE
40 #define PKT_BUFF_SEMI_FULL                      0
51 #define RSI_DEVICE_BUFFER_STATUS_REGISTER       0xf3
52 #define RSI_FN1_INT_REGISTER                    0xf9
53 #define RSI_INT_ENABLE_REGISTER			0x04
54 #define RSI_INT_ENABLE_MASK			0xfc
55 #define RSI_SD_REQUEST_MASTER                   0x10000
58 #define SDIO_RX_NUM_BLOCKS_REG                  0x000F1
59 #define SDIO_FW_STATUS_REG                      0x000F2
60 #define SDIO_NXT_RD_DELAY2                      0x000F5
61 #define SDIO_MASTER_ACCESS_MSBYTE               0x000FA
62 #define SDIO_MASTER_ACCESS_LSBYTE               0x000FB
63 #define SDIO_READ_START_LVL                     0x000FC
64 #define SDIO_READ_FIFO_CTL                      0x000FD
65 #define SDIO_WRITE_FIFO_CTL                     0x000FE
66 #define SDIO_WAKEUP_REG				0x000FF
67 #define SDIO_FUN1_INTR_CLR_REG                  0x0008
68 #define SDIO_REG_HIGH_SPEED                     0x0013
82 #define TA_SOFT_RESET_REG            0x0004
83 #define TA_TH0_PC_REG                0x0400
84 #define TA_HOLD_THREAD_REG           0x0844
85 #define TA_RELEASE_THREAD_REG        0x0848
87 #define TA_SOFT_RST_CLR              0
88 #define TA_SOFT_RST_SET              BIT(0)
89 #define TA_PC_ZERO                   0
90 #define TA_HOLD_THREAD_VALUE         0xF
91 #define TA_RELEASE_THREAD_VALUE      0xF
92 #define TA_BASE_ADDR                 0x2200
93 #define MISC_CFG_BASE_ADDR           0x4105