realtek/rtw89/txrx.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
10 #define DATA_RATE_MODE_CTRL_MASK	GENMASK(8, 7)
20 #define DATA_RATE_NSS_MASK_V1		GENMASK(7, 5)
28 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_rate_mode()
41 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_ht_mcs()
49 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_mcs()
62 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_nss()
69 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
76 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
82 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
83 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
99 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
103 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
106 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0)
110 /* TX WD BODY DWORD 7 (V1) */
111 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
131 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0)
138 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
144 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
153 #define BE_TXD_BODY0_WD_PAGE BIT(7)
166 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
170 #define BE_TXD_BODY1_REUSE_NUM GENMASK(11, 7)
176 #define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
185 #define BE_TXD_BODY2_MACID GENMASK(31, 24)
198 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
203 #define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24)
206 #define BE_TXD_BODY5_SEC_IV_H2 GENMASK(7, 0)
209 #define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24)
221 #define BE_TXD_BODY6_RU_POS GENMASK(31, 24)
223 /* TX WD BODY DWORD 7 */
232 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
245 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
248 #define BE_TXD_INFO1_MAX_AGG_NUM GENMASK(7, 0)
255 #define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28)
258 #define BE_TXD_INFO2_SEC_CAM_IDX GENMASK(7, 0)
266 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
270 #define BE_TXD_INFO3_SPE_PKT_TYPE GENMASK(7, 4)
283 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
294 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
299 #define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)
307 #define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)
309 /* TX WD INFO DWORD 7 */
311 #define BE_TXD_INFO7_UL_PRI_EXP_RSSI_DBM GENMASK(7, 1)
321 #define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)
331 #define AX_RXD_LONG_RXD BIT(31)
336 #define AX_RXD_SR_EN BIT(7)
345 #define AX_RXD_BW_MASK GENMASK(31, 30)
346 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
349 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
359 #define AX_RXD_LAST_MSDU BIT(7)
380 #define AX_RXD_QOS BIT(7)
386 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
389 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0)
398 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
434 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
445 #define RTW89_PHY_STS_HDR_W0_VALID BIT(7)
447 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
448 #define RTW89_PHY_STS_HDR_W1_RSSI_A GENMASK(7, 0)
451 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
475 #define BE_RXD_LONG_RXD BIT(31)
484 #define BE_RXD_MAC_ID_MASK GENMASK(7, 0)
491 #define BE_RXD_TID_MASK GENMASK(31, 28)
498 #define BE_RXD_ICV_ERR BIT(7)
516 #define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)
519 #define BE_RXD_PPDU_TYPE_MASK GENMASK(7, 0)
524 #define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20)
527 #define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
530 #define BE_RXD_ADDR_CAM_MASK GENMASK(7, 0)
537 #define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)
543 #define BE_RXD_PATTERN_WAKE BIT(7)
556 #define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0)
570 #define RTW89_PHY_STS_IE00_W0_RPL GENMASK(15, 7)
599 #define RTW89_PHY_STS_IE01_W0_RX_PATH_EN GENMASK(31, 28)
601 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
621 #define RTW89_PHY_STS_IE01_V2_W5_BW_IDX GENMASK(31, 29)
635 	RTW89_TXCH_ACH7	= 7,
644 	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
653 	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
707 	case 7:  in rtw89_core_get_qsel()
743 	case 7:  in rtw89_core_get_tid_indicate()