realtek/rtw89/txrx.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
12 #define DATA_RATE_NOT_HT_IDX_MASK	GENMASK(3, 0)
17 #define DATA_RATE_HT_NSS_MASK		GENMASK(4, 3)
19 #define DATA_RATE_VHT_HE_IDX_MASK	GENMASK(3, 0)
28 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_rate_mode()
41 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_ht_mcs()
49 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_mcs()
62 	if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)  in rtw89_get_data_nss()
69 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
78 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2)
82 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
83 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16)
85 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0)
93 /* TX WD BODY DWORD 3 */
99 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
103 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
111 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31)
140 /* TX WD INFO DWORD 3 */
144 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31)
166 #define BE_TXD_BODY0_HCI_SEQNUM_MODE BIT(31)
176 #define BE_TXD_BODY1_ADDR_INFO_NUM GENMASK(31, 26)
185 #define BE_TXD_BODY2_MACID GENMASK(31, 24)
187 /* TX WD BODY DWORD 3 */
198 #define BE_TXD_BODY3_BAND1_SU_RTY_V1 BIT(31)
203 #define BE_TXD_BODY4_SEC_IV_L1 GENMASK(31, 24)
209 #define BE_TXD_BODY5_SEC_IV_H5 GENMASK(31, 24)
221 #define BE_TXD_BODY6_RU_POS GENMASK(31, 24)
232 #define BE_TXD_BODY7_USERATE_SEL BIT(31)
235 #define BE_TXD_INFO0_MBSSID GENMASK(3, 0)
245 #define BE_TXD_INFO0_ACK_CH_INFO BIT(31)
255 #define BE_TXD_INFO1_SW_DEFINE GENMASK(31, 28)
266 #define BE_TXD_INFO2_SIFS_TX_V1 BIT(31)
268 /* TX WD INFO DWORD 3 */
269 #define BE_TXD_INFO3_SPE_PKT GENMASK(3, 0)
283 #define BE_TXD_INFO3_FORCE_BSS_CLR BIT(31)
294 #define BE_TXD_INFO4_HW_RTS_EN BIT(31)
299 #define BE_TXD_INFO5_NDPA_DURATION GENMASK(31, 16)
307 #define BE_TXD_INFO6_UL_RF_GAIN_IDX GENMASK(31, 22)
321 #define BE_TXD_INFO7_EXTEND_MODE_SEL GENMASK(31, 28)
331 #define AX_RXD_LONG_RXD BIT(31)
334 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0)
345 #define AX_RXD_BW_MASK GENMASK(31, 30)
346 #define AX_RXD_BW_v1_MASK GENMASK(31, 29)
349 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
355 #define AX_RXD_AMPDU BIT(3)
376 #define AX_RXD_BC BIT(3)
386 #define AX_RXD_FRAG_MASK GENMASK(31, 28)
398 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0)
416 #define RTW89_RXINFO_USER_MGMT BIT(3)
426 #define RTW89_RXINFO_W0_USR_NUM GENMASK(3, 0)
434 #define RTW89_RXINFO_W0_LONG_RXD GENMASK(31, 30)
447 #define RTW89_PHY_STS_HDR_W0_RSSI_AVG GENMASK(31, 24)
451 #define RTW89_PHY_STS_HDR_W1_RSSI_D GENMASK(31, 24)
475 #define BE_RXD_LONG_RXD BIT(31)
491 #define BE_RXD_TID_MASK GENMASK(31, 28)
494 #define BE_RXD_SEC_TYPE_MASK GENMASK(3, 0)
516 #define BE_RXD_GET_CH_INFO_V1_MASK GENMASK(31, 30)
524 #define BE_RXD_RX_DATARATE_MASK GENMASK(31, 20)
527 #define BE_RXD_FREERUN_CNT_MASK GENMASK(31, 0)
537 #define BE_RXD_SEC_CAM_IDX_MASK GENMASK(31, 24)
556 #define BE_RXD_MAC_ADDR_MASK GENMASK(31, 0)
599 #define RTW89_PHY_STS_IE01_W0_RX_PATH_EN GENMASK(31, 28)
601 #define RTW89_PHY_STS_IE01_W1_PREMB_CFO GENMASK(31, 20)
621 #define RTW89_PHY_STS_IE01_V2_W5_BW_IDX GENMASK(31, 29)
631 	RTW89_TXCH_ACH3	= 3,
644 	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1
653 	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1
698 	case 3:  in rtw89_core_get_qsel()
740 	case 3:  in rtw89_core_get_tid_indicate()