Lines Matching +full:0 +full:xf0ffffff
24 {2, 1641, grp_0}, /* ACH 0 */
36 {0, 0, 0}, /* FWCMDQ */
37 {0, 0, 0}, /* BMC */
38 {0, 0, 0}, /* H2D */
42 1651, /* Group 0 */
45 0, /* WP threshold */
164 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
171 0xf},
174 0x0},
218 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
219 [RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
220 [RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
221 [RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
222 [RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x200},
223 [RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
224 [RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x0},
225 [RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
232 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
233 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
234 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
235 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
236 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
237 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x30, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
238 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
239 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
240 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x2, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
242 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
244 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
245 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
246 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
247 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
248 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x1a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
249 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x2a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
250 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
251 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
252 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
254 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
313 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0x02); in rtw8922a_pwr_on_func()
316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x01, 0x01); in rtw8922a_pwr_on_func()
322 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40); in rtw8922a_pwr_on_func()
328 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20); in rtw8922a_pwr_on_func()
331 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04); in rtw8922a_pwr_on_func()
334 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08); in rtw8922a_pwr_on_func()
337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10); in rtw8922a_pwr_on_func()
340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
343 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
346 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01); in rtw8922a_pwr_on_func()
349 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02); in rtw8922a_pwr_on_func()
352 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80); in rtw8922a_pwr_on_func()
355 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF1, 0, 0x40); in rtw8922a_pwr_on_func()
358 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF2, 0, 0x40); in rtw8922a_pwr_on_func()
361 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, 0x40, 0x60); in rtw8922a_pwr_on_func()
404 return 0; in rtw8922a_pwr_on_func()
412 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10); in rtw8922a_pwr_off_func()
415 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08); in rtw8922a_pwr_off_func()
418 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04); in rtw8922a_pwr_off_func()
421 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
424 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
427 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80); in rtw8922a_pwr_off_func()
430 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02); in rtw8922a_pwr_off_func()
433 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01); in rtw8922a_pwr_off_func()
436 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0xFF); in rtw8922a_pwr_off_func()
439 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x00, 0xFF); in rtw8922a_pwr_off_func()
452 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20); in rtw8922a_pwr_off_func()
458 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40); in rtw8922a_pwr_off_func()
488 rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2); in rtw8922a_pwr_off_func()
491 rtw89_write32(rtwdev, R_BE_UDM1, 0); in rtw8922a_pwr_off_func()
493 return 0; in rtw8922a_pwr_off_func()
507 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_efuse_parsing_tssi()
511 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
513 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
523 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
525 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
566 for (j = 0; j < RTW89_GAIN_OFFSET_NR; j++) { in rtw8922a_efuse_parsing_gain_offset()
568 if (t != 0xff) in rtw8922a_efuse_parsing_gain_offset()
570 if (t != 0x0) in rtw8922a_efuse_parsing_gain_offset()
574 if (t & 0x80) in rtw8922a_efuse_parsing_gain_offset()
575 gain->offset[i][j] = (t ^ 0x7f) + 1; in rtw8922a_efuse_parsing_gain_offset()
587 for (i = 0; i < ETH_ALEN; i += 2, addr += 2) { in rtw8922a_read_efuse_mac_addr()
589 efuse->addr[i] = val & 0xff; in rtw8922a_read_efuse_mac_addr()
599 rtw8922a_read_efuse_mac_addr(rtwdev, 0x3104); in rtw8922a_read_efuse_pci_sdio()
601 ether_addr_copy(efuse->addr, log_map + 0x001A); in rtw8922a_read_efuse_pci_sdio()
603 return 0; in rtw8922a_read_efuse_pci_sdio()
608 rtw8922a_read_efuse_mac_addr(rtwdev, 0x4078); in rtw8922a_read_efuse_usb()
610 return 0; in rtw8922a_read_efuse_usb()
620 efuse->country_code[0] = map->country_code[0]; in rtw8922a_read_efuse_rf()
627 return 0; in rtw8922a_read_efuse_rf()
641 return 0; in rtw8922a_read_efuse()
646 #define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
651 static const u32 thm_trim_addr[RF_PATH_NUM_8922A] = {0x1706, 0x1733}; in rtw8922a_phycap_parsing_thermal_trim()
659 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_thermal_trim()
661 if (pg_th == 0xff) { in rtw8922a_phycap_parsing_thermal_trim()
662 info->thermal_trim[i] = 0; in rtw8922a_phycap_parsing_thermal_trim()
675 "[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n", in rtw8922a_phycap_parsing_thermal_trim()
685 static const u32 pabias_trim_addr[RF_PATH_NUM_8922A] = {0x1707, 0x1734}; in rtw8922a_phycap_parsing_pa_bias_trim()
686 static const u32 check_pa_pad_trim_addr = 0x1700; in rtw8922a_phycap_parsing_pa_bias_trim()
693 if (val != 0xff) in rtw8922a_phycap_parsing_pa_bias_trim()
696 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pa_bias_trim()
700 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pa_bias_trim()
718 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pa_bias_trim()
719 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); in rtw8922a_pa_bias_trim()
723 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pa_bias_trim()
734 static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922A] = {0x1708, 0x1735}; in rtw8922a_phycap_parsing_pad_bias_trim()
739 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pad_bias_trim()
743 "[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pad_bias_trim()
760 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pad_bias_trim()
761 pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0)); in rtw8922a_pad_bias_trim()
765 "[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pad_bias_trim()
779 return 0; in rtw8922a_read_phycap()
795 u8 txsb20 = 0, txsb40 = 0, txsb80 = 0; in rtw8922a_set_channel_mac()
833 txsb = 0; in rtw8922a_set_channel_mac()
866 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
868 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
872 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f); in rtw8922a_set_channel_mac()
874 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e); in rtw8922a_set_channel_mac()
880 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
881 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
885 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
886 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
907 return 0; in rtw8922a_ctrl_sco_cck()
918 { .addr = 0x41E8, .mask = 0xFF00},
919 { .addr = 0x41E8, .mask = 0xFF0000},
920 { .addr = 0x41E8, .mask = 0xFF000000},
921 { .addr = 0x41EC, .mask = 0xFF},
922 { .addr = 0x41EC, .mask = 0xFF00},
923 { .addr = 0x41EC, .mask = 0xFF0000},
924 { .addr = 0x41EC, .mask = 0xFF000000},
925 { .addr = 0x41F0, .mask = 0xFF}
929 { .addr = 0x41F4, .mask = 0xFF},
930 { .addr = 0x41F4, .mask = 0xFF00},
931 { .addr = 0x41F4, .mask = 0xFF0000},
932 { .addr = 0x41F4, .mask = 0xFF000000}
936 { .addr = 0x41F0, .mask = 0xFF0000},
937 { .addr = 0x41F0, .mask = 0xFF000000}
941 { .addr = 0x41F0, .mask = 0xFF00}
945 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
946 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
947 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
948 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
949 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
950 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
951 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
952 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
953 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
954 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
955 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
956 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
957 { .gain_g = {0x40a8, 0x44a8}, .gain_a = {0x4078, 0x4478},
958 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
962 { .gain_g = {0x4054, 0x4454}, .gain_a = {0x4054, 0x4454},
963 .gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
964 { .gain_g = {0x4058, 0x4458}, .gain_a = {0x4054, 0x4454},
965 .gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
982 u32 reg_path_ofst = 0; in rtw8922a_set_rpl_gain()
989 reg_path_ofst = 0x400; in rtw8922a_set_rpl_gain()
991 for (i = 0; i < RTW89_BW20_SC_160M; i++) { in rtw8922a_set_rpl_gain()
998 for (i = 0; i < RTW89_BW20_SC_80M; i++) { in rtw8922a_set_rpl_gain()
1005 for (i = 0; i < RTW89_BW20_SC_40M; i++) { in rtw8922a_set_rpl_gain()
1012 for (i = 0; i < RTW89_BW20_SC_20M; i++) { in rtw8922a_set_rpl_gain()
1036 for (i = 0; i < LNA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1048 for (i = 0; i < TIA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1076 u8 fraction = value & 0x3; in rtw8922a_set_rx_gain_normal_cck()
1080 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1082 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1086 value + 1 + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1088 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20, 0); in rtw8922a_set_rx_gain_normal_cck()
1089 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40, 0); in rtw8922a_set_rx_gain_normal_cck()
1093 value + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1101 static const u32 rssi_tb_bias_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1102 static const u32 rssi_tb_ext_comp[2] = {0x4208, 0x4608}; in rtw8922a_set_rx_gain_normal_ofdm()
1103 static const u32 rssi_ofst_addr[2] = {0x40c8, 0x44c8}; in rtw8922a_set_rx_gain_normal_ofdm()
1104 static const u32 rpl_bias_comp[2] = {0x41e8, 0x45e8}; in rtw8922a_set_rx_gain_normal_ofdm()
1105 static const u32 rpl_ext_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1113 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], 0xff000000, value + 0xF8); in rtw8922a_set_rx_gain_normal_ofdm()
1122 rtw89_phy_write32_mask(rtwdev, rpl_bias_comp[path], 0xff, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1123 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1124 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff00, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1126 rtw89_phy_write32_mask(rtwdev, rssi_tb_bias_comp[path], 0xff0000, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1127 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff0000, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1128 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff000000, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1150 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3b13ff, phy_idx); in rtw8922a_set_cck_parameters()
1151 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x1c42de, phy_idx); in rtw8922a_set_cck_parameters()
1152 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0xfdb0ad, phy_idx); in rtw8922a_set_cck_parameters()
1153 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0xf60f6e, phy_idx); in rtw8922a_set_cck_parameters()
1154 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfd8f92, phy_idx); in rtw8922a_set_cck_parameters()
1155 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0x02d011, phy_idx); in rtw8922a_set_cck_parameters()
1156 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0x01c02c, phy_idx); in rtw8922a_set_cck_parameters()
1157 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xfff00a, phy_idx); in rtw8922a_set_cck_parameters()
1159 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3a63ca, phy_idx); in rtw8922a_set_cck_parameters()
1160 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x2a833f, phy_idx); in rtw8922a_set_cck_parameters()
1161 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0x1491f8, phy_idx); in rtw8922a_set_cck_parameters()
1162 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0x03c0b0, phy_idx); in rtw8922a_set_cck_parameters()
1163 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfccff1, phy_idx); in rtw8922a_set_cck_parameters()
1164 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0xfccfc3, phy_idx); in rtw8922a_set_cck_parameters()
1165 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0xfebfdc, phy_idx); in rtw8922a_set_cck_parameters()
1166 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xffdff7, phy_idx); in rtw8922a_set_cck_parameters()
1174 static const u32 band_sel[2] = {0x4160, 0x4560}; in rtw8922a_ctrl_ch()
1214 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1215 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1216 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1217 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1218 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1219 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1222 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1223 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1224 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1225 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1226 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1227 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1230 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1231 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1232 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1233 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1234 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1235 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1238 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1239 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1241 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1242 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1243 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1246 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1247 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1249 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1250 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1251 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1254 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x3, phy_idx); in rtw8922a_ctrl_bw()
1255 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1257 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1258 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1259 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1270 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 0, phy_idx); in rtw8922a_ctrl_bw()
1276 return 0; in rtw8922a_spur_freq()
1291 if (spur_freq == 0) { in rtw8922a_set_csi_tone_idx()
1293 0, phy_idx); in rtw8922a_set_csi_tone_idx()
1308 .notch1_idx = {0x41a0, 0xFF},
1309 .notch1_frac_idx = {0x41a0, 0xC00},
1310 .notch1_en = {0x41a0, 0x1000},
1311 .notch2_idx = {0x41ac, 0xFF},
1312 .notch2_frac_idx = {0x41ac, 0xC00},
1313 .notch2_en = {0x41ac, 0x1000},
1316 .notch1_idx = {0x45a0, 0xFF},
1317 .notch1_frac_idx = {0x45a0, 0xC00},
1318 .notch1_en = {0x45a0, 0x1000},
1319 .notch2_idx = {0x45ac, 0xFF},
1320 .notch2_frac_idx = {0x45ac, 0xC00},
1321 .notch2_en = {0x45ac, 0x1000},
1338 if (spur_freq == 0) { in rtw8922a_set_nbi_tone_idx()
1340 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1342 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1378 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1382 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1390 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1394 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1410 u32 cr_ofst = 0x0; in rtw8922a_ctrl_afe_dac()
1413 cr_ofst = 0x100; in rtw8922a_ctrl_afe_dac()
1421 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xE); in rtw8922a_ctrl_afe_dac()
1422 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x7); in rtw8922a_ctrl_afe_dac()
1425 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xD); in rtw8922a_ctrl_afe_dac()
1426 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x6); in rtw8922a_ctrl_afe_dac()
1434 {0x6990, 0x00000000},
1435 {0x6994, 0x00000000},
1436 {0x6998, 0x00000000},
1437 {0x6820, 0xFFFFFFFE},
1438 {0x6800, 0xC0000FFE},
1439 {0x6808, 0x76543210},
1440 {0x6814, 0xBFBFB000},
1441 {0x6818, 0x0478C009},
1442 {0x6800, 0xC0000FFF},
1443 {0x6820, 0xFFFFFFFF},
1447 {0x6990, 0x00000000},
1448 {0x6994, 0x00000000},
1449 {0x6998, 0x00000000},
1450 {0x6820, 0xFFFFFFFE},
1451 {0x6800, 0xC0000FFE},
1452 {0x6808, 0x76543210},
1453 {0x6814, 0xBFBFB000},
1454 {0x6818, 0x0478C009},
1455 {0x6800, 0xC0000FFF},
1456 {0x6820, 0xFFFFFFFF},
1473 for (i = 0; i < size; i++, reg++) in rtw8922a_bbmcu_cr_init()
1484 u32 rdy = 0; in rtw8922a_bb_preinit()
1489 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9); in rtw8922a_bb_preinit()
1490 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1491 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1492 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1); in rtw8922a_bb_preinit()
1494 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0); in rtw8922a_bb_preinit()
1508 rtw89_phy_set_phy_regs(rtwdev, R_TXFCTR, B_TXFCTR_THD, 0x200); in rtw8922a_bb_postinit()
1509 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_EHT_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1510 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_HE_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1511 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_HT_VHT_TH, 0xAAA); in rtw8922a_bb_postinit()
1512 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_EHT_MCS14, 0x1); in rtw8922a_bb_postinit()
1513 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_EHT_MCS15, 0x1); in rtw8922a_bb_postinit()
1514 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_EHTTB_EN, 0x0); in rtw8922a_bb_postinit()
1515 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEERSU_EN, 0x0); in rtw8922a_bb_postinit()
1516 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEMU_EN, 0x0); in rtw8922a_bb_postinit()
1517 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_TB_EN, 0x0); in rtw8922a_bb_postinit()
1518 rtw89_phy_set_phy_regs(rtwdev, R_SU_PUNC, B_SU_PUNC_EN, 0x1); in rtw8922a_bb_postinit()
1519 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_HWGEN_EN, 0x1); in rtw8922a_bb_postinit()
1520 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_PWROFST_COMP, 0x1); in rtw8922a_bb_postinit()
1521 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_BY_SLOPE, 0x1); in rtw8922a_bb_postinit()
1522 rtw89_phy_set_phy_regs(rtwdev, R_MAG_A, B_MGA_AEND, 0xe0); in rtw8922a_bb_postinit()
1523 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_MAG_AB, 0xe0c000); in rtw8922a_bb_postinit()
1524 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_A, 0x3FE0); in rtw8922a_bb_postinit()
1525 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_B, 0x3FE0); in rtw8922a_bb_postinit()
1526 rtw89_phy_set_phy_regs(rtwdev, R_SC_CORNER, B_SC_CORNER, 0x200); in rtw8922a_bb_postinit()
1527 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x0, phy_idx); in rtw8922a_bb_postinit()
1528 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x1, phy_idx); in rtw8922a_bb_postinit()
1538 B_RXCCA_BE1_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1539 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1541 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1542 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1544 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); in rtw8922a_bb_reset_en()
1553 {0x11A00, 0x21C86900}, in rtw8922a_ctrl_tx_path_tmac()
1554 {0x11A04, 0x00E4E433}, in rtw8922a_ctrl_tx_path_tmac()
1555 {0x11A08, 0x39390CC9}, in rtw8922a_ctrl_tx_path_tmac()
1556 {0x11A0C, 0x4E433240}, in rtw8922a_ctrl_tx_path_tmac()
1557 {0x11A10, 0x90CC900E}, in rtw8922a_ctrl_tx_path_tmac()
1558 {0x11A14, 0x00240393}, in rtw8922a_ctrl_tx_path_tmac()
1559 {0x11A18, 0x201C8600}, in rtw8922a_ctrl_tx_path_tmac()
1561 int ret = 0; in rtw8922a_ctrl_tx_path_tmac()
1565 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL, 0x0, phy_idx); in rtw8922a_ctrl_tx_path_tmac()
1568 return 0; in rtw8922a_ctrl_tx_path_tmac()
1571 path_com_cr[0].data = 0x21C82900; in rtw8922a_ctrl_tx_path_tmac()
1572 path_com_cr[1].data = 0x00E4E431; in rtw8922a_ctrl_tx_path_tmac()
1573 path_com_cr[2].data = 0x39390C49; in rtw8922a_ctrl_tx_path_tmac()
1574 path_com_cr[3].data = 0x4E431240; in rtw8922a_ctrl_tx_path_tmac()
1575 path_com_cr[4].data = 0x90C4900E; in rtw8922a_ctrl_tx_path_tmac()
1576 path_com_cr[6].data = 0x201C8200; in rtw8922a_ctrl_tx_path_tmac()
1578 path_com_cr[0].data = 0x21C04900; in rtw8922a_ctrl_tx_path_tmac()
1579 path_com_cr[1].data = 0x00E4E032; in rtw8922a_ctrl_tx_path_tmac()
1580 path_com_cr[2].data = 0x39380C89; in rtw8922a_ctrl_tx_path_tmac()
1581 path_com_cr[3].data = 0x4E032240; in rtw8922a_ctrl_tx_path_tmac()
1582 path_com_cr[4].data = 0x80C8900E; in rtw8922a_ctrl_tx_path_tmac()
1583 path_com_cr[6].data = 0x201C0400; in rtw8922a_ctrl_tx_path_tmac()
1585 path_com_cr[0].data = 0x21C86900; in rtw8922a_ctrl_tx_path_tmac()
1586 path_com_cr[1].data = 0x00E4E433; in rtw8922a_ctrl_tx_path_tmac()
1587 path_com_cr[2].data = 0x39390CC9; in rtw8922a_ctrl_tx_path_tmac()
1588 path_com_cr[3].data = 0x4E433240; in rtw8922a_ctrl_tx_path_tmac()
1589 path_com_cr[4].data = 0x90CC900E; in rtw8922a_ctrl_tx_path_tmac()
1590 path_com_cr[6].data = 0x201C8600; in rtw8922a_ctrl_tx_path_tmac()
1595 for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) { in rtw8922a_ctrl_tx_path_tmac()
1611 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1612 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1615 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1616 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1617 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1618 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 0, in rtw8922a_cfg_rx_nss_limit()
1638 return 0; in rtw8922a_cfg_rx_nss_limit()
1647 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1648 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1650 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1651 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1654 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1655 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1656 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1657 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1667 /* Set to 0 first to avoid abnormal EDCCA report */ in rtw8922a_ctrl_rx_path_tmac()
1668 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x0, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1671 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x1, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1676 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x2, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1681 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x3, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1689 return 0; in rtw8922a_ctrl_rx_path_tmac()
1694 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1695 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303,
1696 0x05030302, 0x06060605, 0x06050300, 0x0A090807, 0x02000B0B,
1697 0x09080604, 0x0D0D0C0B, 0x08060400, 0x110F0C0B, 0x05001111,
1698 0x0D0C0907, 0x12121210},
1699 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1700 0x0BB80708, 0x17701194, 0x04030201, 0x05050505, 0x01000505,
1701 0x07060504, 0x09090908, 0x09070400, 0x0E0D0C0B, 0x03000E0E,
1702 0x0D0B0907, 0x1010100F, 0x0B080500, 0x1512100D, 0x05001515,
1703 0x100D0B08, 0x15151512},
1716 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; in rtw8922a_set_digital_pwr_comp()
1721 for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) { in rtw8922a_set_digital_pwr_comp()
1722 val = enable ? digital_pwr_comp[i] : 0; in rtw8922a_set_digital_pwr_comp()
1751 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x1); in rtw8922a_ctrl_mlo()
1752 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x0); in rtw8922a_ctrl_mlo()
1755 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_ctrl_mlo()
1756 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x1); in rtw8922a_ctrl_mlo()
1768 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_ctrl_mlo()
1771 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1772 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_ctrl_mlo()
1773 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_ctrl_mlo()
1774 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_ctrl_mlo()
1776 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1777 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_ctrl_mlo()
1778 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_ctrl_mlo()
1779 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_ctrl_mlo()
1781 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x7BAB); in rtw8922a_ctrl_mlo()
1782 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3BAB); in rtw8922a_ctrl_mlo()
1783 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3AAB); in rtw8922a_ctrl_mlo()
1785 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x180); in rtw8922a_ctrl_mlo()
1786 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x0); in rtw8922a_ctrl_mlo()
1789 return 0; in rtw8922a_ctrl_mlo()
1799 rtw89_write32_mask(rtwdev, R_BE_PWR_BOOST, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1802 rtw89_write32_mask(rtwdev, reg, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1812 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1815 0, phy_idx); in rtw8922a_ctrl_cck_en()
1818 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1851 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1852 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_pre_set_channel_bb()
1853 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1854 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_pre_set_channel_bb()
1855 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_pre_set_channel_bb()
1856 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_pre_set_channel_bb()
1858 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1859 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1860 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_pre_set_channel_bb()
1861 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_pre_set_channel_bb()
1862 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_pre_set_channel_bb()
1891 u32 path_ofst = (path == RF_PATH_B) ? 0x100 : 0x0; in rtw8922a_dfs_en_idx()
1894 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 1, in rtw8922a_dfs_en_idx()
1897 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 0, in rtw8922a_dfs_en_idx()
1917 val &= ~0x1; in rtw8922a_adc_en_path()
1919 val &= ~0x2; in rtw8922a_adc_en_path()
1922 val |= 0x1; in rtw8922a_adc_en_path()
1924 val |= 0x2; in rtw8922a_adc_en_path()
1991 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); in rtw8922a_rfk_init()
2010 for (path = 0; path < RF_PATH_NUM_8922A; path++) { in _wait_rx_mode()
2015 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
2065 s16 ref_ofdm = 0; in rtw8922a_set_txpwr_ref()
2066 s16 ref_cck = 0; in rtw8922a_set_txpwr_ref()
2079 u8 ctrl = en ? 0x1 : 0x0; in rtw8922a_bb_tx_triangular()
2097 if (tx_shape_idx == 0) in rtw8922a_set_tx_shape()
2137 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2139 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2141 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2142 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2143 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2144 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2145 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2146 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2147 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2149 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2151 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2152 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2153 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2154 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2155 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2156 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2158 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2160 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2162 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2163 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2164 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2165 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2166 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2167 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2168 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2170 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2172 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2173 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2174 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2175 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x2a30, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2176 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2177 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2216 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2217 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); in rtw8922a_get_thermal()
2218 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2225 return clamp_t(int, th, 0, U8_MAX); in rtw8922a_get_thermal()
2235 module->bt_solo = 0; in rtw8922a_btc_set_rfe()
2237 module->wa_type = 0; in rtw8922a_btc_set_rfe()
2242 module->ant.diversity = 0; in rtw8922a_btc_set_rfe()
2251 if (module->rfe_type == 0) { in rtw8922a_btc_set_rfe()
2258 if (module->kt_ver == 0) in rtw8922a_btc_set_rfe()
2301 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */ in rtw8922a_btc_init_cfg()
2302 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2304 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */ in rtw8922a_btc_init_cfg()
2305 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df); in rtw8922a_btc_init_cfg()
2307 /* if GNT_WL = 0 && BT = Tx_group --> in rtw8922a_btc_init_cfg()
2308 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) in rtw8922a_btc_init_cfg()
2311 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f); in rtw8922a_btc_init_cfg()
2313 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2315 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0); in rtw8922a_btc_init_cfg()
2327 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2329 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2331 rtw89_write32(rtwdev, R_BTC_ZB_BREAK_TBL, 0xf0ffffff); in rtw8922a_btc_init_cfg()
2338 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0)); in rtw8922a_btc_set_wl_txpwr_ctrl()
2342 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2344 B_BE_FORCE_PWR_BY_RATE_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2346 B_BE_FORCE_PWR_BY_RATE_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2352 B_BE_FORCE_PWR_BY_RATE_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2357 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2359 B_BE_PWR_BT_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2361 B_BE_PWR_BT_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2367 B_BE_PWR_BT_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2375 return clamp_t(s8, val, -100, 0) + 100; in rtw8922a_btc_get_bt_rssi()
2379 {255, 0, 0, 7}, /* 0 -> original */
2380 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2381 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2382 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2383 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2384 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2385 {6, 1, 0, 7},
2386 {13, 1, 0, 7},
2387 {13, 1, 0, 7}
2391 {255, 0, 0, 7}, /* 0 -> original */
2392 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2393 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2394 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2395 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2396 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2397 {255, 1, 0, 7},
2398 {255, 1, 0, 7},
2399 {255, 1, 0, 7}
2406 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
2407 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe320),
2408 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe324),
2409 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe328),
2410 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe32c),
2411 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
2412 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
2413 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
2414 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
2415 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
2416 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
2417 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
2418 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a2c),
2419 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a50),
2420 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2421 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x660),
2422 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x1660),
2423 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x418c),
2424 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x518c),
2437 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2438 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2439 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2440 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2441 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2443 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2444 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2445 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2446 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2447 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2449 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2450 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2451 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2452 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2453 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2455 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2456 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2457 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2458 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2459 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2475 if (chan_idx == 0) in rtw8922a_fill_freq_with_ppdu()
2492 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { in rtw8922a_query_ppdu()
2504 static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0}; in rtw8922a_convert_rpl_to_rssi()
2506 u8 compensate = 0; in rtw8922a_convert_rpl_to_rssi()
2513 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_convert_rpl_to_rssi()
2515 rssi[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2516 phy_ppdu->rpl_path[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2517 phy_ppdu->rpl_fd[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2536 rtw89_write32(rtwdev, R_BE_DMAC_SYS_CR32B, 0x7FF97FF9); in rtw8922a_mac_enable_bb_rf()
2538 return 0; in rtw8922a_mac_enable_bb_rf()
2546 return 0; in rtw8922a_mac_disable_bb_rf()
2635 .dle_scc_rsvd_size = 0,
2638 .rsvd_ple_ofst = 0x8f800,
2643 .rf_base_addr = {0xe000, 0xf000},
2685 .physical_efuse_size = 0x1300,
2686 .logical_efuse_size = 0x70000,
2687 .limit_efuse_size = 0x40000,
2688 .dav_phy_efuse_size = 0,
2689 .dav_log_efuse_size = 0,
2691 .phycap_addr = 0x1700,
2692 .phycap_size = 0x38,
2693 .para_ver = 0xf,
2694 .wlcx_desired = 0x07110000,
2695 .btcx_desired = 0x7,
2696 .scbd = 0x1,
2697 .mailbox = 0x1,
2712 .low_power_hci_modes = 0,
2729 .dcfo_comp_sft = 0,
2738 .dma_ch_mask = 0,