15 #define RTW8852A_FW_FORMAT_MAX 0
21 	{128, 1896, grp_0}, /* ACH 0 */
33 	{40, 0, 0} /* FWCMDQ */
37 	1896, /* Group 0 */
40 	0 /* WP threshold */
69 	{0x44AC, 0x00000000},
70 	{0x44B0, 0x00000000},
71 	{0x44B4, 0x00000000},
72 	{0x44B8, 0x00000000},
73 	{0x44BC, 0x00000000},
74 	{0x44C0, 0x00000000},
75 	{0x44C4, 0x00000000},
76 	{0x44C8, 0x00000000},
77 	{0x44CC, 0x00000000},
78 	{0x44D0, 0x00000000},
79 	{0x44D4, 0x00000000},
80 	{0x44D8, 0x00000000},
81 	{0x44DC, 0x00000000},
82 	{0x44E0, 0x00000000},
83 	{0x44E4, 0x00000000},
84 	{0x44E8, 0x00000000},
85 	{0x44EC, 0x00000000},
86 	{0x44F0, 0x00000000},
87 	{0x44F4, 0x00000000},
88 	{0x44F8, 0x00000000},
89 	{0x44FC, 0x00000000},
90 	{0x4500, 0x00000000},
91 	{0x4504, 0x00000000},
92 	{0x4508, 0x00000000},
93 	{0x450C, 0x00000000},
94 	{0x4510, 0x00000000},
95 	{0x4514, 0x00000000},
96 	{0x4518, 0x00000000},
97 	{0x451C, 0x00000000},
98 	{0x4520, 0x00000000},
99 	{0x4524, 0x00000000},
100 	{0x4528, 0x00000000},
101 	{0x452C, 0x00000000},
102 	{0x4530, 0x4E1F3E81},
103 	{0x4534, 0x00000000},
104 	{0x4538, 0x0000005A},
105 	{0x453C, 0x00000000},
106 	{0x4540, 0x00000000},
107 	{0x4544, 0x00000000},
108 	{0x4548, 0x00000000},
109 	{0x454C, 0x00000000},
110 	{0x4550, 0x00000000},
111 	{0x4554, 0x00000000},
112 	{0x4558, 0x00000000},
113 	{0x455C, 0x00000000},
114 	{0x4560, 0x4060001A},
115 	{0x4564, 0x40000000},
116 	{0x4568, 0x00000000},
117 	{0x456C, 0x00000000},
118 	{0x4570, 0x04000007},
119 	{0x4574, 0x0000DC87},
120 	{0x4578, 0x00000BAB},
121 	{0x457C, 0x03E00000},
122 	{0x4580, 0x00000048},
123 	{0x4584, 0x00000000},
124 	{0x4588, 0x000003E8},
125 	{0x458C, 0x30000000},
126 	{0x4590, 0x00000000},
127 	{0x4594, 0x10000000},
128 	{0x4598, 0x00000001},
129 	{0x459C, 0x00030000},
130 	{0x45A0, 0x01000000},
131 	{0x45A4, 0x03000200},
132 	{0x45A8, 0xC00001C0},
133 	{0x45AC, 0x78018000},
134 	{0x45B0, 0x80000000},
135 	{0x45B4, 0x01C80600},
136 	{0x45B8, 0x00000002},
137 	{0x4594, 0x10000000}
141 	{0x4624, GENMASK(20, 14), 0x40},
142 	{0x46f8, GENMASK(20, 14), 0x40},
143 	{0x4674, GENMASK(20, 19), 0x2},
144 	{0x4748, GENMASK(20, 19), 0x2},
145 	{0x4650, GENMASK(14, 10), 0x18},
146 	{0x4724, GENMASK(14, 10), 0x18},
147 	{0x4688, GENMASK(1, 0), 0x3},
148 	{0x475c, GENMASK(1, 0), 0x3},
154 	{0x4624, GENMASK(20, 14), 0x1a},
155 	{0x46f8, GENMASK(20, 14), 0x1a},
156 	{0x4674, GENMASK(20, 19), 0x1},
157 	{0x4748, GENMASK(20, 19), 0x1},
158 	{0x4650, GENMASK(14, 10), 0x12},
159 	{0x4724, GENMASK(14, 10), 0x12},
160 	{0x4688, GENMASK(1, 0), 0x0},
161 	{0x475c, GENMASK(1, 0), 0x0},
167 	{0x00C6,
172 	{0x1086,
176 	 PWR_CMD_WRITE, BIT(0), 0},
177 	{0x1086,
182 	{0x0005,
186 	 PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
187 	{0x0005,
191 	 PWR_CMD_WRITE, BIT(7), 0},
192 	{0x0005,
196 	 PWR_CMD_WRITE, BIT(2), 0},
197 	{0x0006,
202 	{0x0006,
206 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
207 	{0x0005,
211 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
212 	{0x0005,
216 	 PWR_CMD_POLL, BIT(0), 0},
217 	{0x106D,
221 	 PWR_CMD_WRITE, BIT(6), 0},
222 	{0x0088,
226 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
227 	{0x0088,
231 	 PWR_CMD_WRITE, BIT(0), 0},
232 	{0x0088,
236 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
237 	{0x0088,
241 	 PWR_CMD_WRITE, BIT(0), 0},
242 	{0x0088,
246 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
247 	{0x0083,
251 	 PWR_CMD_WRITE, BIT(6), 0},
252 	{0x0080,
257 	{0x0024,
261 	 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
262 	{0x02A0,
267 	{0x02A2,
271 	 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
272 	{0x0071,
276 	 PWR_CMD_WRITE, BIT(4), 0},
277 	{0x0010,
282 	{0x02A0,
286 	 PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
287 	{0xFFFF,
290 	 0,
291 	 PWR_CMD_END, 0, 0},
295 	{0x02F0,
299 	 PWR_CMD_WRITE, 0xFF, 0},
300 	{0x02F1,
304 	 PWR_CMD_WRITE, 0xFF, 0},
305 	{0x0006,
309 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
310 	{0x0002,
314 	 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
315 	{0x0082,
319 	 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
320 	{0x106D,
325 	{0x0005,
330 	{0x0005,
334 	 PWR_CMD_POLL, BIT(1), 0},
335 	{0x0091,
339 	 PWR_CMD_WRITE, BIT(0), 0},
340 	{0x0092,
345 	{0x0005,
350 	{0x0007,
354 	 PWR_CMD_WRITE, BIT(4), 0},
355 	{0x0007,
359 	 PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
360 	{0x0005,
365 	{0x0005,
371 	{0x1086,
375 	 PWR_CMD_WRITE, BIT(0), BIT(0)},
376 	{0x1086,
380 	 PWR_CMD_POLL, BIT(1), 0},
381 	{0xFFFF,
384 	 0,
385 	 PWR_CMD_END, 0, 0},
433 	.mpdu_tx_imr_set	= 0,
434 	.mpdu_rx_imr_set	= 0,
451 	.other_disp_imr_set	= 0,
454 	.bbrpt_err_imr_set	= 0,
461 	.cdma_imr_1_reg		= 0,
462 	.cdma_imr_1_clr		= 0,
463 	.cdma_imr_1_set		= 0,
465 	.phy_intf_imr_clr	= 0,
466 	.phy_intf_imr_set	= 0,
482 	.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
489 		   0xf},
492 		 0x0},
551 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {  in rtw8852a_efuse_parsing_tssi()
555 		for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)  in rtw8852a_efuse_parsing_tssi()
557 				    "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",  in rtw8852a_efuse_parsing_tssi()
565 		for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)  in rtw8852a_efuse_parsing_tssi()
567 				    "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",  in rtw8852a_efuse_parsing_tssi()
580 	efuse->country_code[0] = map->country_code[0];  in rtw8852a_read_efuse()
594 	return 0;  in rtw8852a_read_efuse()
600 	static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};  in rtw8852a_phycap_parsing_tssi()
606 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {  in rtw8852a_phycap_parsing_tssi()
607 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {  in rtw8852a_phycap_parsing_tssi()
612 			if (phycap_map[ofst] != 0xff)  in rtw8852a_phycap_parsing_tssi()
618 		memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));  in rtw8852a_phycap_parsing_tssi()
620 			    "[TSSI][TRIM] no PG, set all trim info to 0\n");  in rtw8852a_phycap_parsing_tssi()
623 	for (i = 0; i < RF_PATH_NUM_8852A; i++)  in rtw8852a_phycap_parsing_tssi()
624 		for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)  in rtw8852a_phycap_parsing_tssi()
626 				    "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",  in rtw8852a_phycap_parsing_tssi()
635 	static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};  in rtw8852a_phycap_parsing_thermal_trim()
639 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {  in rtw8852a_phycap_parsing_thermal_trim()
643 			    "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",  in rtw8852a_phycap_parsing_thermal_trim()
646 		if (info->thermal_trim[i] != 0xff)  in rtw8852a_phycap_parsing_thermal_trim()
656 	((__v & 0x1) << 3) | ((__v & 0x1f) >> 1);	\  in rtw8852a_thermal_trim()
668 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {  in rtw8852a_thermal_trim()
673 			    "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",  in rtw8852a_thermal_trim()
683 	static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};  in rtw8852a_phycap_parsing_pa_bias_trim()
687 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {  in rtw8852a_phycap_parsing_pa_bias_trim()
691 			    "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",  in rtw8852a_phycap_parsing_pa_bias_trim()
694 		if (info->pa_bias_trim[i] != 0xff)  in rtw8852a_phycap_parsing_pa_bias_trim()
712 	for (i = 0; i < RF_PATH_NUM_8852A; i++) {  in rtw8852a_pa_bias_trim()
713 		pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);  in rtw8852a_pa_bias_trim()
717 			    "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",  in rtw8852a_pa_bias_trim()
731 	return 0;  in rtw8852a_read_phycap()
747 	u8 txsc20 = 0, txsc40 = 0;  in rtw8852a_set_channel_mac()
768 		rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));  in rtw8852a_set_channel_mac()
773 		rtw89_write32(rtwdev, sub_carr, 0);  in rtw8852a_set_channel_mac()
788 	0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
789 	0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
793 	0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
794 	0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
818 	return 0;  in rtw8852a_ctrl_sco_cck()
831 	val &= ~0x303ff;  in rtw8852a_ch_setting()
863 		return 0;  in rtw8852a_sco_mapping()
881 					      B_PATH0_TIA_ERR_G1_SEL, 0,  in rtw8852a_ctrl_ch()
894 						      0, phy_idx);  in rtw8852a_ctrl_ch()
917 					      0, phy_idx);  in rtw8852a_ctrl_ch()
929 		rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,  in rtw8852a_ctrl_ch()
935 				       0x3b13ff);  in rtw8852a_ctrl_ch()
937 				       0x1c42de);  in rtw8852a_ctrl_ch()
939 				       0xfdb0ad);  in rtw8852a_ctrl_ch()
941 				       0xf60f6e);  in rtw8852a_ctrl_ch()
943 				       0xfd8f92);  in rtw8852a_ctrl_ch()
944 		rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);  in rtw8852a_ctrl_ch()
945 		rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);  in rtw8852a_ctrl_ch()
947 				       0xfff00a);  in rtw8852a_ctrl_ch()
950 				       0x3d23ff);  in rtw8852a_ctrl_ch()
952 				       0x29b354);  in rtw8852a_ctrl_ch()
953 		rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);  in rtw8852a_ctrl_ch()
955 				       0xfdb053);  in rtw8852a_ctrl_ch()
957 				       0xf86f9a);  in rtw8852a_ctrl_ch()
959 				       0xfaef92);  in rtw8852a_ctrl_ch()
961 				       0xfe5fcc);  in rtw8852a_ctrl_ch()
963 				       0xffdff5);  in rtw8852a_ctrl_ch()
969 	u32 val = 0;  in rtw8852a_bw_setting()
970 	u32 adc_sel[2] = {0x12d0, 0x32d0};  in rtw8852a_bw_setting()
971 	u32 wbadc_sel[2] = {0x12ec, 0x32ec};  in rtw8852a_bw_setting()
981 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);  in rtw8852a_bw_setting()
982 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);  in rtw8852a_bw_setting()
986 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);  in rtw8852a_bw_setting()
987 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);  in rtw8852a_bw_setting()
991 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);  in rtw8852a_bw_setting()
992 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);  in rtw8852a_bw_setting()
996 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);  in rtw8852a_bw_setting()
997 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);  in rtw8852a_bw_setting()
1001 		rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);  in rtw8852a_bw_setting()
1002 		rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);  in rtw8852a_bw_setting()
1019 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,  in rtw8852a_ctrl_bw()
1021 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,  in rtw8852a_ctrl_bw()
1024 				      0x0, phy_idx);  in rtw8852a_ctrl_bw()
1027 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,  in rtw8852a_ctrl_bw()
1029 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,  in rtw8852a_ctrl_bw()
1032 				      0x0, phy_idx);  in rtw8852a_ctrl_bw()
1035 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,  in rtw8852a_ctrl_bw()
1037 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,  in rtw8852a_ctrl_bw()
1040 				      0x0, phy_idx);  in rtw8852a_ctrl_bw()
1043 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,  in rtw8852a_ctrl_bw()
1045 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,  in rtw8852a_ctrl_bw()
1053 			rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);  in rtw8852a_ctrl_bw()
1056 		rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,  in rtw8852a_ctrl_bw()
1058 		rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,  in rtw8852a_ctrl_bw()
1082 				       0x210);  in rtw8852a_spur_elimination()
1084 				       0x210);  in rtw8852a_spur_elimination()
1085 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);  in rtw8852a_spur_elimination()
1087 				       B_P0_NBIIDX_NOTCH_EN, 0x1);  in rtw8852a_spur_elimination()
1089 				       B_P1_NBIIDX_NOTCH_EN, 0x1);  in rtw8852a_spur_elimination()
1091 				       0x1);  in rtw8852a_spur_elimination()
1094 				       0x210);  in rtw8852a_spur_elimination()
1096 				       0x210);  in rtw8852a_spur_elimination()
1097 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);  in rtw8852a_spur_elimination()
1099 				       B_P0_NBIIDX_NOTCH_EN, 0x1);  in rtw8852a_spur_elimination()
1101 				       B_P1_NBIIDX_NOTCH_EN, 0x1);  in rtw8852a_spur_elimination()
1103 				       0x1);  in rtw8852a_spur_elimination()
1106 				       0x2d0);  in rtw8852a_spur_elimination()
1108 				       0x2d0);  in rtw8852a_spur_elimination()
1109 		rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);  in rtw8852a_spur_elimination()
1111 				       B_P0_NBIIDX_NOTCH_EN, 0x1);  in rtw8852a_spur_elimination()
1113 				       B_P1_NBIIDX_NOTCH_EN, 0x1);  in rtw8852a_spur_elimination()
1115 				       0x1);  in rtw8852a_spur_elimination()
1118 				       B_P0_NBIIDX_NOTCH_EN, 0x0);  in rtw8852a_spur_elimination()
1120 				       B_P1_NBIIDX_NOTCH_EN, 0x0);  in rtw8852a_spur_elimination()
1122 				       0x0);  in rtw8852a_spur_elimination()
1131 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,  in rtw8852a_bb_reset_all()
1146 				      0,  in rtw8852a_bb_reset_en()
1171 		rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);  in rtw8852a_bb_macid_ctrl_init()
1181 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);  in rtw8852a_bb_sethw()
1182 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);  in rtw8852a_bb_sethw()
1183 		rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);  in rtw8852a_bb_sethw()
1189 	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);  in rtw8852a_bb_sethw()
1190 	rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);  in rtw8852a_bb_sethw()
1191 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);  in rtw8852a_bb_sethw()
1192 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);  in rtw8852a_bb_sethw()
1225 		rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);  in rtw8852a_set_channel_bb()
1250 		rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);  in rtw8852a_dfs_en()
1256 	static const u32 tssi_trk[2] = {0x5818, 0x7818};  in rtw8852a_tssi_cont_en()
1257 	static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};  in rtw8852a_tssi_cont_en()
1260 		rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);  in rtw8852a_tssi_cont_en()
1261 		rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);  in rtw8852a_tssi_cont_en()
1263 		rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);  in rtw8852a_tssi_cont_en()
1264 		rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);  in rtw8852a_tssi_cont_en()
1286 				       0x0);  in rtw8852a_adc_en()
1289 				       0xf);  in rtw8852a_adc_en()
1386 	s8 ofst_int = 0;  in rtw8852a_bb_cal_txpwr_ref()
1387 	u8 base_cw_0db = 0x27;  in rtw8852a_bb_cal_txpwr_ref()
1388 	u16 tssi_16dbm_cw = 0x12c;  in rtw8852a_bb_cal_txpwr_ref()
1389 	s16 pwr_s10_3 = 0;  in rtw8852a_bb_cal_txpwr_ref()
1390 	s16 rf_pwr_cw = 0;  in rtw8852a_bb_cal_txpwr_ref()
1391 	u16 bb_pwr_cw = 0;  in rtw8852a_bb_cal_txpwr_ref()
1392 	u32 pwr_cw = 0;  in rtw8852a_bb_cal_txpwr_ref()
1393 	u32 tssi_ofst_cw = 0;  in rtw8852a_bb_cal_txpwr_ref()
1396 	bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);  in rtw8852a_bb_cal_txpwr_ref()
1403 		    "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",  in rtw8852a_bb_cal_txpwr_ref()
1406 	return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));  in rtw8852a_bb_cal_txpwr_ref()
1413 	s8 val_1t = 0;  in rtw8852a_set_txpwr_ul_tb_offset()
1414 	s8 val_2t = 0;  in rtw8852a_set_txpwr_ul_tb_offset()
1437 	static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};  in rtw8852a_set_txpwr_ref()
1438 	const u32 mask = 0x7FFFFFF;  in rtw8852a_set_txpwr_ref()
1439 	const u8 ofst_ofdm = 0x4;  in rtw8852a_set_txpwr_ref()
1440 	const u8 ofst_cck = 0x8;  in rtw8852a_set_txpwr_ref()
1441 	s16 ref_ofdm = 0;  in rtw8852a_set_txpwr_ref()
1442 	s16 ref_cck = 0;  in rtw8852a_set_txpwr_ref()
1449 				     GENMASK(27, 10), 0x0);  in rtw8852a_set_txpwr_ref()
1454 	for (i = 0; i < RF_PATH_NUM_8852A; i++)  in rtw8852a_set_txpwr_ref()
1461 	for (i = 0; i < RF_PATH_NUM_8852A; i++)  in rtw8852a_set_txpwr_ref()
1487 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);  in rtw8852a_init_txpwr_unit()
1491 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);  in rtw8852a_init_txpwr_unit()
1495 	ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);  in rtw8852a_init_txpwr_unit()
1499 	return 0;  in rtw8852a_init_txpwr_unit()
1504 	u8 i = 0;  in rtw8852a_bb_set_plcp_tx()
1507 	for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {  in rtw8852a_bb_set_plcp_tx()
1520 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,  in rtw8852a_stop_pmac_tx()
1523 		rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,  in rtw8852a_stop_pmac_tx()
1549 	rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);  in rtw8852a_start_pmac_tx()
1558 		rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);  in rtw8852a_bb_set_pmac_tx()
1566 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,  in rtw8852a_bb_set_pmac_tx()
1568 	rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);  in rtw8852a_bb_set_pmac_tx()
1579 	struct rtw8852a_bb_pmac_info tx_info = {0};  in rtw8852a_bb_set_pmac_pkt_tx()
1582 	tx_info.is_cck = 0;  in rtw8852a_bb_set_pmac_pkt_tx()
1600 	u32 rst_mask0 = 0;  in rtw8852a_bb_cfg_tx_path()
1601 	u32 rst_mask1 = 0;  in rtw8852a_bb_cfg_tx_path()
1611 					       B_TXNSS_MAP_MSK, 0);  in rtw8852a_bb_cfg_tx_path()
1616 					       B_TXNSS_MAP_MSK, 0);  in rtw8852a_bb_cfg_tx_path()
1631 				       0);  in rtw8852a_bb_cfg_tx_path()
1649 	if (mode != 0)  in rtw8852a_bb_tx_mode_switch()
1652 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);  in rtw8852a_bb_tx_mode_switch()
1653 	rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);  in rtw8852a_bb_tx_mode_switch()
1654 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);  in rtw8852a_bb_tx_mode_switch()
1655 	rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);  in rtw8852a_bb_tx_mode_switch()
1656 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);  in rtw8852a_bb_tx_mode_switch()
1657 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);  in rtw8852a_bb_tx_mode_switch()
1658 	rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);  in rtw8852a_bb_tx_mode_switch()
1671 		u32 addr = 0x1c10 + (rf_path << 13);  in rtw8852a_get_thermal()
1673 		return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);  in rtw8852a_get_thermal()
1676 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);  in rtw8852a_get_thermal()
1677 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);  in rtw8852a_get_thermal()
1678 	rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);  in rtw8852a_get_thermal()
1693 		md->md_v7.bt_solo = 0;  in rtw8852a_btc_set_rfe()
1696 		if (md->md_v7.rfe_type > 0)  in rtw8852a_btc_set_rfe()
1701 		md->md_v7.ant.diversity = 0;  in rtw8852a_btc_set_rfe()
1716 		md->md.bt_solo = 0;  in rtw8852a_btc_set_rfe()
1719 		if (md->md.rfe_type > 0)  in rtw8852a_btc_set_rfe()
1724 		md->md.ant.diversity = 0;  in rtw8852a_btc_set_rfe()
1742 	rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);  in rtw8852a_set_trx_mask()
1743 	rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);  in rtw8852a_set_trx_mask()
1744 	rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);  in rtw8852a_set_trx_mask()
1745 	rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);  in rtw8852a_set_trx_mask()
1752 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);  in rtw8852a_ctrl_btg_bt_rx()
1753 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);  in rtw8852a_ctrl_btg_bt_rx()
1754 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);  in rtw8852a_ctrl_btg_bt_rx()
1756 		rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);  in rtw8852a_ctrl_btg_bt_rx()
1757 		rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);  in rtw8852a_ctrl_btg_bt_rx()
1758 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);  in rtw8852a_ctrl_btg_bt_rx()
1759 		rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);  in rtw8852a_ctrl_btg_bt_rx()
1780 	rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);  in rtw8852a_btc_init_cfg()
1781 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);  in rtw8852a_btc_init_cfg()
1783 	/* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */  in rtw8852a_btc_init_cfg()
1786 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);  in rtw8852a_btc_init_cfg()
1788 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);  in rtw8852a_btc_init_cfg()
1789 		/* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */  in rtw8852a_btc_init_cfg()
1791 				      RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);  in rtw8852a_btc_init_cfg()
1792 	} else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */  in rtw8852a_btc_init_cfg()
1794 				      RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);  in rtw8852a_btc_init_cfg()
1796 				      RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);  in rtw8852a_btc_init_cfg()
1802 	 /* enable BT counter 0xda40[16,2] = 2b'11 */  in rtw8852a_btc_init_cfg()
1811 	u32 bitmap = 0;  in rtw8852a_btc_set_wl_pri()
1812 	u32 reg = 0;  in rtw8852a_btc_set_wl_pri()
1835 	return FIELD_GET(GENMASK(15, 0), ctrl);  in __btc_ctrl_val_all_time()
1875 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0))  in rtw8852a_btc_set_wl_txpwr_ctrl()
1882 			    "btc ctrl %s: 0x%x\n", #_case, _val);	\  in rtw8852a_btc_set_wl_txpwr_ctrl()
1886 			    "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur);	\  in rtw8852a_btc_set_wl_txpwr_ctrl()
1892 			    "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt);	\  in rtw8852a_btc_set_wl_txpwr_ctrl()
1893 	} while (0)  in rtw8852a_btc_set_wl_txpwr_ctrl()
1906 	return clamp_t(s8, val + 6, -100, 0) + 100;  in rtw8852a_btc_get_bt_rssi()
1910 	{255, 0, 0, 7}, /* 0 -> original */
1911 	{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
1912 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1913 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1914 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1915 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1916 	{6, 1, 0, 7},
1917 	{13, 1, 0, 7},
1918 	{13, 1, 0, 7}
1922 	{255, 0, 0, 7}, /* 0 -> original */
1923 	{255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
1924 	{255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1925 	{255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1926 	{255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1927 	{255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1928 	{255, 1, 0, 7},
1929 	{255, 1, 0, 7},
1930 	{255, 1, 0, 7}
1939 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
1940 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
1941 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
1942 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
1943 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
1944 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
1945 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
1946 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
1947 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
1948 	RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
1949 	RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
1950 	RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
1982 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);  in rtw8852a_btc_wl_s1_standby()
1983 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);  in rtw8852a_btc_wl_s1_standby()
1984 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);  in rtw8852a_btc_wl_s1_standby()
1986 	/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */  in rtw8852a_btc_wl_s1_standby()
1989 			       RFREG_MASK, 0xa2d7c);  in rtw8852a_btc_wl_s1_standby()
1992 			       RFREG_MASK, 0xa2020);  in rtw8852a_btc_wl_s1_standby()
1994 	rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);  in rtw8852a_btc_wl_s1_standby()
1999 	/* level=0 Default:    TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB  in rtw8852a_set_wl_lna2()
2000 	 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB  in rtw8852a_set_wl_lna2()
2005 	case 0: /* default */  in rtw8852a_set_wl_lna2()
2006 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);  in rtw8852a_set_wl_lna2()
2007 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);  in rtw8852a_set_wl_lna2()
2008 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);  in rtw8852a_set_wl_lna2()
2009 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);  in rtw8852a_set_wl_lna2()
2010 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);  in rtw8852a_set_wl_lna2()
2011 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);  in rtw8852a_set_wl_lna2()
2014 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);  in rtw8852a_set_wl_lna2()
2015 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);  in rtw8852a_set_wl_lna2()
2016 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);  in rtw8852a_set_wl_lna2()
2017 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);  in rtw8852a_set_wl_lna2()
2018 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);  in rtw8852a_set_wl_lna2()
2019 		rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);  in rtw8852a_set_wl_lna2()
2029 	case 0: /* original */  in rtw8852a_btc_set_wl_rx_gain()
2032 		btc->dm.wl_lna2 = 0;  in rtw8852a_btc_set_wl_rx_gain()
2036 		btc->dm.wl_lna2 = 0;  in rtw8852a_btc_set_wl_rx_gain()
2054 	if (chan == 0)  in rtw8852a_fill_freq_with_ppdu()
2070 	for (path = 0; path < rtwdev->chip->rf_path_num; path++) {  in rtw8852a_query_ppdu()
2158 	.bbmcu_nr		= 0,
2159 	.needed_fw_elms		= 0,
2162 	.dle_scc_rsvd_size	= 0,
2165 	.rsvd_ple_ofst		= 0x6f800,
2170 	.rf_base_addr		= {0xc000, 0xd000},
2187 	.support_link_num	= 0,
2214 	.dav_phy_efuse_size	= 0,
2215 	.dav_log_efuse_size	= 0,
2217 	.phycap_addr		= 0x580,
2219 	.para_ver		= 0x0,
2220 	.wlcx_desired		= 0x06000000,
2221 	.btcx_desired		= 0x7,
2222 	.scbd			= 0x1,
2223 	.mailbox		= 0x1,
2238 	.low_power_hci_modes	= 0,
2264 	.dma_ch_mask		= 0,