Lines Matching +full:0 +full:x1032
10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA03 0x03
17 #define RAC_ANA09 0x09
19 #define RAC_ANA0A 0x0A
21 #define RAC_ANA0C 0x0C
23 #define RAC_ANA0D 0x0D
25 #define RAC_ANA10 0x10
26 #define ADDR_SEL_PINOUT_DIS_VAL 0x3C4
28 #define RAC_REG_REV2 0x1B
30 #define PCIE_DPHY_DLY_25US 0x1
31 #define RAC_ANA19 0x19
33 #define RAC_REG_FLD_0 0x1D
35 #define PCIE_AUTOK_4 0x3
36 #define RAC_ANA1E 0x1E
37 #define RAC_ANA1E_G1_VAL 0x66EA
38 #define RAC_ANA1E_G2_VAL 0x6EEA
39 #define RAC_ANA1F 0x1F
41 #define RAC_ANA24 0x24
43 #define RAC_ANA26 0x26
45 #define RAC_ANA2E 0x2E
46 #define RAC_ANA2E_VAL 0xFFFE
47 #define RAC_CTRL_PPR_V1 0x30
51 #define RAC_SET_PPR_V1 0x31
53 #define R_AX_DBI_FLAG 0x1090
58 #define B_AX_DBI_2LSB GENMASK(1, 0)
59 #define R_AX_DBI_WDATA 0x1094
60 #define R_AX_DBI_RDATA 0x1098
62 #define R_AX_MDIO_WDATA 0x10A4
63 #define R_AX_MDIO_RDATA 0x10A6
65 #define R_AX_PCIE_PS_CTRL_V1 0x3008
70 #define B_AX_SEL_REQ_EXIT_L1 BIT(0)
72 #define R_AX_PCIE_MIX_CFG_V1 0x300C
80 #define B_AX_L1SUB_DISABLE BIT(0)
82 #define R_AX_L1_CLK_CTRL 0x3010
85 #define R_AX_PCIE_BG_CLR 0x303C
88 #define R_AX_PCIE_LAT_CTRL 0x3044
90 #define B_AX_CLK_REQ_SEL BIT(0)
92 #define R_AX_PCIE_IO_RCY_M1 0x3100
96 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
98 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
99 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
101 #define R_AX_PCIE_IO_RCY_M2 0x310C
105 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
107 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
108 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
110 #define R_AX_PCIE_IO_RCY_E0 0x3118
114 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
116 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
117 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
119 #define R_AX_PCIE_IO_RCY_S1 0x3124
126 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
128 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
129 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
131 #define R_RAC_DIRECT_OFFSET_G1 0x3800
133 #define R_RAC_DIRECT_OFFSET_G2 0x3880
140 #define R_AX_HIMR0 0x01A0
143 #define R_AX_HISR0 0x01A4
145 #define R_AX_HIMR1 0x01A8
148 #define B_AX_GPIO16_INT_EN BIT(0)
150 #define R_AX_HISR1 0x01AC
153 #define B_AX_GPIO16_INT BIT(0)
155 #define R_AX_MDIO_CFG 0x10A0
159 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0)
161 #define R_AX_PCIE_HIMR00 0x10B0
162 #define R_AX_HAXI_HIMR00 0x10B0
189 #define B_AX_RXDMA_INT_EN BIT(0)
191 #define R_AX_PCIE_HISR00 0x10B4
192 #define R_AX_HAXI_HISR00 0x10B4
218 #define B_AX_RXDMA_INT BIT(0)
220 #define R_AX_HAXI_IDCT_MSK 0x10B8
224 #define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
226 #define R_AX_HAXI_IDCT 0x10BC
230 #define B_AX_TXMDA_STUCK_IDCT BIT(0)
232 #define R_AX_HAXI_HIMR10 0x11E0
234 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
236 #define R_AX_PCIE_HIMR10 0x13B0
241 #define R_AX_PCIE_HISR10 0x13B4
246 #define R_AX_PCIE_HIMR00_V1 0x30B0
254 #define R_AX_PCIE_HISR00_V1 0x30B4
262 #define R_BE_PCIE_FRZ_CLK 0x3004
285 #define B_BE_PCIE_EN_AUX_CLK BIT(0)
287 #define R_BE_PCIE_PS_CTRL 0x3008
296 #define B_BE_SEL_REQ_EXIT_L1 BIT(0)
298 #define R_BE_PCIE_MIX_CFG 0x300C
306 #define B_BE_L1SUB_ENABLE BIT(0)
308 #define R_BE_L1_CLK_CTRL 0x3010
311 #define B_BE_CLK_PM_EN BIT(0)
313 #define R_BE_PCIE_LAT_CTRL 0x3044
322 #define B_BE_CLK_REQ_SEL BIT(0)
324 #define R_BE_PCIE_HIMR0 0x30B0
345 #define B_BE_HS0_IND_INT_EN0 BIT(0)
347 #define R_BE_PCIE_HISR 0x30B4
360 #define B_BE_HS0ISR_IND_INT BIT(0)
362 #define R_BE_PCIE_DMA_IMR_0_V1 0x30B8
385 #define B_BE_PCIE_TX_CH0_IMR0 BIT(0)
387 #define R_BE_PCIE_DMA_ISR 0x30BC
410 #define B_BE_PCIE_TX_CH0_ISR BIT(0)
412 #define R_BE_HAXI_HIMR00 0xB0B0
443 #define B_BE_RX0DMA_INT_EN BIT(0)
445 #define R_BE_HAXI_HISR00 0xB0B4
474 #define B_BE_RX0DMA_INT BIT(0)
477 #define R_AX_DRV_FW_HSK_0 0x01B0
478 #define R_AX_DRV_FW_HSK_1 0x01B4
479 #define R_AX_DRV_FW_HSK_2 0x01B8
480 #define R_AX_DRV_FW_HSK_3 0x01BC
481 #define R_AX_DRV_FW_HSK_4 0x01C0
482 #define R_AX_DRV_FW_HSK_5 0x01C4
483 #define R_AX_DRV_FW_HSK_6 0x01C8
484 #define R_AX_DRV_FW_HSK_7 0x01CC
486 #define R_AX_RXQ_RXBD_IDX 0x1050
487 #define R_AX_RPQ_RXBD_IDX 0x1054
488 #define R_AX_ACH0_TXBD_IDX 0x1058
489 #define R_AX_ACH1_TXBD_IDX 0x105C
490 #define R_AX_ACH2_TXBD_IDX 0x1060
491 #define R_AX_ACH3_TXBD_IDX 0x1064
492 #define R_AX_ACH4_TXBD_IDX 0x1068
493 #define R_AX_ACH5_TXBD_IDX 0x106C
494 #define R_AX_ACH6_TXBD_IDX 0x1070
495 #define R_AX_ACH7_TXBD_IDX 0x1074
496 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */
497 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */
498 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */
499 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
500 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */
501 #define R_AX_CH10_TXBD_IDX_V1 0x11D0
502 #define R_AX_CH11_TXBD_IDX_V1 0x11D4
503 #define R_AX_RXQ_RXBD_IDX_V1 0x1218
504 #define R_AX_RPQ_RXBD_IDX_V1 0x121C
506 #define TXBD_HOST_IDX_MASK GENMASK(11, 0)
508 #define R_AX_ACH0_TXBD_DESA_L 0x1110
509 #define R_AX_ACH0_TXBD_DESA_H 0x1114
510 #define R_AX_ACH1_TXBD_DESA_L 0x1118
511 #define R_AX_ACH1_TXBD_DESA_H 0x111C
512 #define R_AX_ACH2_TXBD_DESA_L 0x1120
513 #define R_AX_ACH2_TXBD_DESA_H 0x1124
514 #define R_AX_ACH3_TXBD_DESA_L 0x1128
515 #define R_AX_ACH3_TXBD_DESA_H 0x112C
516 #define R_AX_ACH4_TXBD_DESA_L 0x1130
517 #define R_AX_ACH4_TXBD_DESA_H 0x1134
518 #define R_AX_ACH5_TXBD_DESA_L 0x1138
519 #define R_AX_ACH5_TXBD_DESA_H 0x113C
520 #define R_AX_ACH6_TXBD_DESA_L 0x1140
521 #define R_AX_ACH6_TXBD_DESA_H 0x1144
522 #define R_AX_ACH7_TXBD_DESA_L 0x1148
523 #define R_AX_ACH7_TXBD_DESA_H 0x114C
524 #define R_AX_CH8_TXBD_DESA_L 0x1150
525 #define R_AX_CH8_TXBD_DESA_H 0x1154
526 #define R_AX_CH9_TXBD_DESA_L 0x1158
527 #define R_AX_CH9_TXBD_DESA_H 0x115C
528 #define R_AX_CH10_TXBD_DESA_L 0x1358
529 #define R_AX_CH10_TXBD_DESA_H 0x135C
530 #define R_AX_CH11_TXBD_DESA_L 0x1360
531 #define R_AX_CH11_TXBD_DESA_H 0x1364
532 #define R_AX_CH12_TXBD_DESA_L 0x1160
533 #define R_AX_CH12_TXBD_DESA_H 0x1164
534 #define R_AX_RXQ_RXBD_DESA_L 0x1100
535 #define R_AX_RXQ_RXBD_DESA_H 0x1104
536 #define R_AX_RPQ_RXBD_DESA_L 0x1108
537 #define R_AX_RPQ_RXBD_DESA_H 0x110C
538 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
539 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
540 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
541 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
542 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
543 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
544 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
545 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
546 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
547 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
548 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
549 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
550 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
551 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
552 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
553 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
554 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
555 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
556 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
557 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
558 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
559 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
560 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
561 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
562 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
563 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
564 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
565 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
566 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
567 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
568 #define B_AX_DESC_NUM_MSK GENMASK(11, 0)
570 #define R_AX_RXQ_RXBD_NUM 0x1020
571 #define R_AX_RPQ_RXBD_NUM 0x1022
572 #define R_AX_ACH0_TXBD_NUM 0x1024
573 #define R_AX_ACH1_TXBD_NUM 0x1026
574 #define R_AX_ACH2_TXBD_NUM 0x1028
575 #define R_AX_ACH3_TXBD_NUM 0x102A
576 #define R_AX_ACH4_TXBD_NUM 0x102C
577 #define R_AX_ACH5_TXBD_NUM 0x102E
578 #define R_AX_ACH6_TXBD_NUM 0x1030
579 #define R_AX_ACH7_TXBD_NUM 0x1032
580 #define R_AX_CH8_TXBD_NUM 0x1034
581 #define R_AX_CH9_TXBD_NUM 0x1036
582 #define R_AX_CH10_TXBD_NUM 0x1338
583 #define R_AX_CH11_TXBD_NUM 0x133A
584 #define R_AX_CH12_TXBD_NUM 0x1038
585 #define R_AX_RXQ_RXBD_NUM_V1 0x1210
586 #define R_AX_RPQ_RXBD_NUM_V1 0x1212
587 #define R_AX_CH10_TXBD_NUM_V1 0x1438
588 #define R_AX_CH11_TXBD_NUM_V1 0x143A
590 #define R_AX_ACH0_BDRAM_CTRL 0x1200
591 #define R_AX_ACH1_BDRAM_CTRL 0x1204
592 #define R_AX_ACH2_BDRAM_CTRL 0x1208
593 #define R_AX_ACH3_BDRAM_CTRL 0x120C
594 #define R_AX_ACH4_BDRAM_CTRL 0x1210
595 #define R_AX_ACH5_BDRAM_CTRL 0x1214
596 #define R_AX_ACH6_BDRAM_CTRL 0x1218
597 #define R_AX_ACH7_BDRAM_CTRL 0x121C
598 #define R_AX_CH8_BDRAM_CTRL 0x1220
599 #define R_AX_CH9_BDRAM_CTRL 0x1224
600 #define R_AX_CH10_BDRAM_CTRL 0x1320
601 #define R_AX_CH11_BDRAM_CTRL 0x1324
602 #define R_AX_CH12_BDRAM_CTRL 0x1228
603 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
604 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
605 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
606 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
607 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
608 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
609 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
610 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
611 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
612 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
613 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
614 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
615 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
616 #define BDRAM_SIDX_MASK GENMASK(7, 0)
620 #define R_AX_PCIE_INIT_CFG1 0x1000
637 #define R_AX_TXDMA_ADDR_H 0x10F0
638 #define R_AX_RXDMA_ADDR_H 0x10F4
640 #define R_AX_PCIE_DMA_STOP1 0x1010
655 #define B_AX_STOP_RXQ BIT(0)
668 #define R_AX_PCIE_DMA_STOP2 0x1310
670 #define B_AX_STOP_CH10 BIT(0)
671 #define B_AX_TX_STOP2_ALL GENMASK(1, 0)
673 #define R_AX_TXBD_RWPTR_CLR1 0x1014
684 #define B_AX_CLR_ACH0_IDX BIT(0)
685 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0)
687 #define R_AX_RXBD_RWPTR_CLR 0x1018
689 #define B_AX_CLR_RXQ_IDX BIT(0)
690 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0)
692 #define R_AX_TXBD_RWPTR_CLR2 0x1314
694 #define B_AX_CLR_CH10_IDX BIT(0)
695 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)
697 #define R_AX_PCIE_DMA_BUSY1 0x101C
714 #define B_AX_RXQ_BUSY BIT(0)
723 #define R_AX_PCIE_DMA_BUSY2 0x131C
725 #define B_AX_CH10_BUSY BIT(0)
727 #define R_AX_WP_ADDR_H_SEL0_3 0x1334
728 #define R_AX_WP_ADDR_H_SEL4_7 0x1338
729 #define R_AX_WP_ADDR_H_SEL8_11 0x133C
730 #define R_AX_WP_ADDR_H_SEL12_15 0x1340
732 #define R_BE_HAXI_DMA_STOP1 0xB010
748 #define B_BE_STOP_CH0 BIT(0)
757 #define R_BE_CH0_TXBD_NUM_V1 0xB030
758 #define R_BE_CH1_TXBD_NUM_V1 0xB032
759 #define R_BE_CH2_TXBD_NUM_V1 0xB034
760 #define R_BE_CH3_TXBD_NUM_V1 0xB036
761 #define R_BE_CH4_TXBD_NUM_V1 0xB038
762 #define R_BE_CH5_TXBD_NUM_V1 0xB03A
763 #define R_BE_CH6_TXBD_NUM_V1 0xB03C
764 #define R_BE_CH7_TXBD_NUM_V1 0xB03E
765 #define R_BE_CH8_TXBD_NUM_V1 0xB040
766 #define R_BE_CH9_TXBD_NUM_V1 0xB042
767 #define R_BE_CH10_TXBD_NUM_V1 0xB044
768 #define R_BE_CH11_TXBD_NUM_V1 0xB046
769 #define R_BE_CH12_TXBD_NUM_V1 0xB048
770 #define R_BE_CH13_TXBD_NUM_V1 0xB04C
771 #define R_BE_CH14_TXBD_NUM_V1 0xB04E
773 #define R_BE_RXQ0_RXBD_NUM_V1 0xB050
774 #define R_BE_RPQ0_RXBD_NUM_V1 0xB052
776 #define R_BE_CH0_TXBD_IDX_V1 0xB100
777 #define R_BE_CH1_TXBD_IDX_V1 0xB104
778 #define R_BE_CH2_TXBD_IDX_V1 0xB108
779 #define R_BE_CH3_TXBD_IDX_V1 0xB10C
780 #define R_BE_CH4_TXBD_IDX_V1 0xB110
781 #define R_BE_CH5_TXBD_IDX_V1 0xB114
782 #define R_BE_CH6_TXBD_IDX_V1 0xB118
783 #define R_BE_CH7_TXBD_IDX_V1 0xB11C
784 #define R_BE_CH8_TXBD_IDX_V1 0xB120
785 #define R_BE_CH9_TXBD_IDX_V1 0xB124
786 #define R_BE_CH10_TXBD_IDX_V1 0xB128
787 #define R_BE_CH11_TXBD_IDX_V1 0xB12C
788 #define R_BE_CH12_TXBD_IDX_V1 0xB130
789 #define R_BE_CH13_TXBD_IDX_V1 0xB134
790 #define R_BE_CH14_TXBD_IDX_V1 0xB138
792 #define R_BE_RXQ0_RXBD_IDX_V1 0xB160
793 #define R_BE_RPQ0_RXBD_IDX_V1 0xB164
795 #define R_BE_CH0_TXBD_DESA_L_V1 0xB200
796 #define R_BE_CH0_TXBD_DESA_H_V1 0xB204
797 #define R_BE_CH1_TXBD_DESA_L_V1 0xB208
798 #define R_BE_CH1_TXBD_DESA_H_V1 0xB20C
799 #define R_BE_CH2_TXBD_DESA_L_V1 0xB210
800 #define R_BE_CH2_TXBD_DESA_H_V1 0xB214
801 #define R_BE_CH3_TXBD_DESA_L_V1 0xB218
802 #define R_BE_CH3_TXBD_DESA_H_V1 0xB21C
803 #define R_BE_CH4_TXBD_DESA_L_V1 0xB220
804 #define R_BE_CH4_TXBD_DESA_H_V1 0xB224
805 #define R_BE_CH5_TXBD_DESA_L_V1 0xB228
806 #define R_BE_CH5_TXBD_DESA_H_V1 0xB22C
807 #define R_BE_CH6_TXBD_DESA_L_V1 0xB230
808 #define R_BE_CH6_TXBD_DESA_H_V1 0xB234
809 #define R_BE_CH7_TXBD_DESA_L_V1 0xB238
810 #define R_BE_CH7_TXBD_DESA_H_V1 0xB23C
811 #define R_BE_CH8_TXBD_DESA_L_V1 0xB240
812 #define R_BE_CH8_TXBD_DESA_H_V1 0xB244
813 #define R_BE_CH9_TXBD_DESA_L_V1 0xB248
814 #define R_BE_CH9_TXBD_DESA_H_V1 0xB24C
815 #define R_BE_CH10_TXBD_DESA_L_V1 0xB250
816 #define R_BE_CH10_TXBD_DESA_H_V1 0xB254
817 #define R_BE_CH11_TXBD_DESA_L_V1 0xB258
818 #define R_BE_CH11_TXBD_DESA_H_V1 0xB25C
819 #define R_BE_CH12_TXBD_DESA_L_V1 0xB260
820 #define R_BE_CH12_TXBD_DESA_H_V1 0xB264
821 #define R_BE_CH13_TXBD_DESA_L_V1 0xB268
822 #define R_BE_CH13_TXBD_DESA_H_V1 0xB26C
823 #define R_BE_CH14_TXBD_DESA_L_V1 0xB270
824 #define R_BE_CH14_TXBD_DESA_H_V1 0xB274
826 #define R_BE_RXQ0_RXBD_DESA_L_V1 0xB300
827 #define R_BE_RXQ0_RXBD_DESA_H_V1 0xB304
828 #define R_BE_RPQ0_RXBD_DESA_L_V1 0xB308
829 #define R_BE_RPQ0_RXBD_DESA_H_V1 0xB30C
831 #define R_BE_WP_ADDR_H_SEL0_3_V1 0xB420
832 #define R_BE_WP_ADDR_H_SEL4_7_V1 0xB424
833 #define R_BE_WP_ADDR_H_SEL8_11_V1 0xB428
834 #define R_BE_WP_ADDR_H_SEL12_15_V1 0xB42C
837 #define R_AX_PCIE_INIT_CFG2 0x1004
840 #define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0)
842 #define R_AX_PCIE_PS_CTRL 0x1008
845 #define R_AX_INT_MIT_RX 0x10D4
849 #define AX_RXTIMER_UNIT_64US 0
854 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0)
856 #define R_AX_DBG_ERR_FLAG_V1 0x1104
858 #define R_AX_INT_MIT_RX_V1 0x1184
863 #define B_AX_MIT_RXTIMER_MATCH_MASK GENMASK(7, 0)
865 #define R_AX_DBG_ERR_FLAG 0x11C4
874 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0)
876 #define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4
878 #define B_AX_CLR_CH10_IDX BIT(0)
880 #define R_AX_LBC_WATCHDOG 0x11D8
883 #define B_AX_LBC_EN BIT(0)
885 #define R_AX_RXBD_RWPTR_CLR_V1 0x1200
887 #define B_AX_CLR_RXQ_IDX BIT(0)
889 #define R_AX_HAXI_EXP_CTRL 0x1204
890 #define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0)
892 #define R_AX_PCIE_EXP_CTRL 0x13F0
897 #define R_AX_PCIE_RX_PREF_ADV 0x13F4
898 #define B_AX_RXDMA_PREF_ADV_EN BIT(0)
900 #define R_AX_PCIE_HRPWM_V1 0x30C0
901 #define R_AX_PCIE_CRPWM 0x30C4
903 #define R_AX_LBC_WATCHDOG_V1 0x30D8
905 #define R_BE_PCIE_HRPWM 0x30C0
906 #define R_BE_PCIE_CRPWM 0x30C4
908 #define R_BE_L1_2_CTRL_HCILDO 0x3110
909 #define B_BE_PCIE_DIS_L1_2_CTRL_HCILDO BIT(0)
911 #define R_BE_PL1_DBG_INFO 0x3120
913 #define B_BE_START_PL1_CNT_MASK GENMASK(7, 0)
915 #define R_BE_PCIE_MIT0_TMR 0x3330
917 #define BE_MIT0_TMR_UNIT_1MS 0
921 #define B_BE_PCIE_MIT0_TX_TMR_MASK GENMASK(1, 0)
923 #define R_BE_PCIE_MIT0_CNT 0x3334
927 #define B_BE_PCIE_TX_MIT0_TMR_CNT_MASK GENMASK(7, 0)
929 #define R_BE_PCIE_MIT_CH_EN 0x3338
952 #define B_BE_PCIE_MIT_TXCH0_EN BIT(0)
954 #define R_BE_SER_PL1_CTRL 0x34A8
958 #define B_BE_PL1_TIMER_CLEAR BIT(0)
960 #define R_BE_REG_PL1_MASK 0x34B0
966 #define B_BE_SER_PMU_IMR BIT(0)
968 #define R_BE_REG_PL1_ISR 0x34B4
970 #define R_BE_RX_APPEND_MODE 0x8920
972 #define B_BE_APPEND_LEN_MASK GENMASK(15, 0)
974 #define R_BE_TXBD_RWPTR_CLR1 0xB014
989 #define B_BE_CLR_CH0_IDX BIT(0)
991 #define R_BE_RXBD_RWPTR_CLR1_V1 0xB018
997 #define B_BE_CLR_RXQ0_IDX BIT(0)
999 #define R_BE_HAXI_DMA_BUSY1 0xB01C
1024 #define B_BE_CH0_BUSY BIT(0)
1031 #define R_BE_HAXI_EXP_CTRL_V1 0xB020
1035 #define B_BE_MAX_TAG_NUM_MASK GENMASK(3, 0)
1048 #define RTW89_PCIE_CAPABILITY_SPEED 0x7C
1049 #define RTW89_PCIE_SUPPORT_GEN_MASK GENMASK(3, 0)
1050 #define RTW89_PCIE_L1_STS_V1 0x80
1052 #define RTW89_PCIE_GEN1_SPEED 0x01
1053 #define RTW89_PCIE_GEN2_SPEED 0x02
1054 #define RTW89_PCIE_PHY_RATE 0x82
1055 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
1056 #define RTW89_PCIE_LINK_CHANGE_SPEED 0xA0
1057 #define RTW89_PCIE_L1SS_STS_V1 0x0168
1061 #define RTW89_PCIE_BIT_PCI_L12 BIT(0)
1062 #define RTW89_PCIE_ASPM_CTRL 0x070F
1064 #define RTW89_L0DLY_MASK GENMASK(2, 0)
1065 #define RTW89_PCIE_TIMER_CTRL 0x0718
1067 #define RTW89_PCIE_L1_CTRL 0x0719
1071 #define RTW89_PCIE_CLK_CTRL 0x0725
1072 #define RTW89_PCIE_FTS 0x080C
1074 #define RTW89_PCIE_RST_MSTATE 0x0B48
1075 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0)
1083 PCIE_PHY_GEN1_UNDEFINE = 0x7F,
1087 PCIE_L0SDLY_1US = 0,
1104 PCIE_CLKDLY_HW_0 = 0,
1105 PCIE_CLKDLY_HW_30US = 0x1,
1106 PCIE_CLKDLY_HW_50US = 0x2,
1107 PCIE_CLKDLY_HW_100US = 0x3,
1108 PCIE_CLKDLY_HW_150US = 0x4,
1109 PCIE_CLKDLY_HW_200US = 0x5,
1113 PCIE_CLKDLY_HW_V1_0 = 0,
1114 PCIE_CLKDLY_HW_V1_16US = 0x1,
1115 PCIE_CLKDLY_HW_V1_32US = 0x2,
1116 PCIE_CLKDLY_HW_V1_64US = 0x3,
1117 PCIE_CLKDLY_HW_V1_80US = 0x4,
1118 PCIE_CLKDLY_HW_V1_96US = 0x5,
1124 MAC_AX_BD_DEF = 0xFE
1130 MAC_AX_RXBD_DEF = 0xFE
1136 MAC_AX_TAG_DEF = 0xFE
1140 MAC_AX_TX_BURST_16B = 0,
1143 MAC_AX_TX_BURST_V1_64B = 0,
1151 MAC_AX_TX_BURST_DEF = 0xFE
1155 MAC_AX_RX_BURST_16B = 0,
1158 MAC_AX_RX_BURST_V1_64B = 0,
1161 MAC_AX_RX_BURST_V1_256B = 0,
1162 MAC_AX_RX_BURST_DEF = 0xFE
1176 MAC_AX_WD_DMA_INTVL_DEF = 0xFE
1188 MAC_AX_TAG_NUM_DEF = 0xFE
1192 MAC_AX_LBC_TMR_8US = 0,
1203 MAC_AX_LBC_TMR_DEF = 0xFE
1207 MAC_AX_PCIE_DISABLE = 0,
1209 MAC_AX_PCIE_DEFAULT = 0xFE,
1210 MAC_AX_PCIE_IGNORE = 0xFF
1217 MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
1365 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))
1377 #define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0)
1388 #define RTW89_TX_DONE 0x0
1389 #define RTW89_TX_RETRY_LIMIT 0x1
1390 #define RTW89_TX_LIFE_TIME 0x2
1391 #define RTW89_TX_MACID_DROP 0x3
1393 #define RTW89_PCI_RPP_MACID GENMASK(7, 0)
1408 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0)
1449 #define RTW89_RX_TAG_MAX 0x1fff
1457 u16 tag; /* range from 0x0001 ~ 0x1fff */
1567 txwd->len = 0; in rtw89_pci_dequeue_txwd()
1579 memset(txwd->vaddr, 0, wd_ring->page_size); in rtw89_pci_enqueue_txwd()
1586 return val == 0xffffffff || val == 0xeaeaeaea; in rtw89_pci_ltr_is_err_reg_val()
1717 return 0; in rtw89_pci_ops_mac_pre_deinit()