Lines Matching +full:0 +full:x262
28 #define MASKBYTE0 0xff
29 #define MASKBYTE1 0xff00
30 #define MASKBYTE2 0xff0000
31 #define MASKBYTE3 0xff000000
32 #define MASKBYTE4 0xff00000000ULL
33 #define MASKHWORD 0xffff0000
34 #define MASKLWORD 0x0000ffff
35 #define MASKDWORD 0xffffffff
36 #define RFREG_MASK 0xfffff
37 #define INV_RF_DATA 0xffffffff
38 #define BYPASS_CR_DATA 0xbabecafe
52 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
58 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
67 HTC_OM_CHANNEL_WIDTH_20 = 0,
79 #define RTW89_TF_PAD GENMASK(11, 0)
83 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
90 RTW89_CH_2G = 0,
174 RTW89_CORE_RX_TYPE_WIFI = 0,
192 RTW89_TXQ_F_AMPDU = 0,
198 RTW89_NET_TYPE_NO_LINK = 0,
251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
256 RTW89_ADDR_CAM_SEC_NONE = 0,
263 RTW89_SEC_KEY_TYPE_NONE = 0,
277 RTW89_PORT_0 = 0,
286 RTW89_BAND_2G = 0,
293 RTW89_HW_RATE_CCK1 = 0x0,
294 RTW89_HW_RATE_CCK2 = 0x1,
295 RTW89_HW_RATE_CCK5_5 = 0x2,
296 RTW89_HW_RATE_CCK11 = 0x3,
297 RTW89_HW_RATE_OFDM6 = 0x4,
298 RTW89_HW_RATE_OFDM9 = 0x5,
299 RTW89_HW_RATE_OFDM12 = 0x6,
300 RTW89_HW_RATE_OFDM18 = 0x7,
301 RTW89_HW_RATE_OFDM24 = 0x8,
302 RTW89_HW_RATE_OFDM36 = 0x9,
303 RTW89_HW_RATE_OFDM48 = 0xA,
304 RTW89_HW_RATE_OFDM54 = 0xB,
305 RTW89_HW_RATE_MCS0 = 0x80,
306 RTW89_HW_RATE_MCS1 = 0x81,
307 RTW89_HW_RATE_MCS2 = 0x82,
308 RTW89_HW_RATE_MCS3 = 0x83,
309 RTW89_HW_RATE_MCS4 = 0x84,
310 RTW89_HW_RATE_MCS5 = 0x85,
311 RTW89_HW_RATE_MCS6 = 0x86,
312 RTW89_HW_RATE_MCS7 = 0x87,
313 RTW89_HW_RATE_MCS8 = 0x88,
314 RTW89_HW_RATE_MCS9 = 0x89,
315 RTW89_HW_RATE_MCS10 = 0x8A,
316 RTW89_HW_RATE_MCS11 = 0x8B,
317 RTW89_HW_RATE_MCS12 = 0x8C,
318 RTW89_HW_RATE_MCS13 = 0x8D,
319 RTW89_HW_RATE_MCS14 = 0x8E,
320 RTW89_HW_RATE_MCS15 = 0x8F,
321 RTW89_HW_RATE_MCS16 = 0x90,
322 RTW89_HW_RATE_MCS17 = 0x91,
323 RTW89_HW_RATE_MCS18 = 0x92,
324 RTW89_HW_RATE_MCS19 = 0x93,
325 RTW89_HW_RATE_MCS20 = 0x94,
326 RTW89_HW_RATE_MCS21 = 0x95,
327 RTW89_HW_RATE_MCS22 = 0x96,
328 RTW89_HW_RATE_MCS23 = 0x97,
329 RTW89_HW_RATE_MCS24 = 0x98,
330 RTW89_HW_RATE_MCS25 = 0x99,
331 RTW89_HW_RATE_MCS26 = 0x9A,
332 RTW89_HW_RATE_MCS27 = 0x9B,
333 RTW89_HW_RATE_MCS28 = 0x9C,
334 RTW89_HW_RATE_MCS29 = 0x9D,
335 RTW89_HW_RATE_MCS30 = 0x9E,
336 RTW89_HW_RATE_MCS31 = 0x9F,
337 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
338 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
339 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
340 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
341 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
342 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
343 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
344 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
345 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
346 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
347 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
348 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
349 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
350 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
351 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
352 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
353 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
354 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
355 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
356 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
357 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
358 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
359 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
360 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
361 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
362 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
363 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
364 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
365 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
366 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
367 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
368 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
369 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
370 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
371 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
372 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
373 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
374 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
375 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
376 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
377 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
378 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
379 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
380 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
381 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
382 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
383 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
384 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
385 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
386 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
387 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
388 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
389 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
390 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
391 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
392 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
393 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
394 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
395 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
396 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
397 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
398 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
399 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
400 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
401 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
402 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
403 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
404 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
405 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
406 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
407 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
408 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
409 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
410 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
411 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
412 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
413 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
414 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
415 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
416 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
417 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
418 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
419 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
420 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
421 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
422 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
423 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
424 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
426 RTW89_HW_RATE_V1_MCS0 = 0x100,
427 RTW89_HW_RATE_V1_MCS1 = 0x101,
428 RTW89_HW_RATE_V1_MCS2 = 0x102,
429 RTW89_HW_RATE_V1_MCS3 = 0x103,
430 RTW89_HW_RATE_V1_MCS4 = 0x104,
431 RTW89_HW_RATE_V1_MCS5 = 0x105,
432 RTW89_HW_RATE_V1_MCS6 = 0x106,
433 RTW89_HW_RATE_V1_MCS7 = 0x107,
434 RTW89_HW_RATE_V1_MCS8 = 0x108,
435 RTW89_HW_RATE_V1_MCS9 = 0x109,
436 RTW89_HW_RATE_V1_MCS10 = 0x10A,
437 RTW89_HW_RATE_V1_MCS11 = 0x10B,
438 RTW89_HW_RATE_V1_MCS12 = 0x10C,
439 RTW89_HW_RATE_V1_MCS13 = 0x10D,
440 RTW89_HW_RATE_V1_MCS14 = 0x10E,
441 RTW89_HW_RATE_V1_MCS15 = 0x10F,
442 RTW89_HW_RATE_V1_MCS16 = 0x110,
443 RTW89_HW_RATE_V1_MCS17 = 0x111,
444 RTW89_HW_RATE_V1_MCS18 = 0x112,
445 RTW89_HW_RATE_V1_MCS19 = 0x113,
446 RTW89_HW_RATE_V1_MCS20 = 0x114,
447 RTW89_HW_RATE_V1_MCS21 = 0x115,
448 RTW89_HW_RATE_V1_MCS22 = 0x116,
449 RTW89_HW_RATE_V1_MCS23 = 0x117,
450 RTW89_HW_RATE_V1_MCS24 = 0x118,
451 RTW89_HW_RATE_V1_MCS25 = 0x119,
452 RTW89_HW_RATE_V1_MCS26 = 0x11A,
453 RTW89_HW_RATE_V1_MCS27 = 0x11B,
454 RTW89_HW_RATE_V1_MCS28 = 0x11C,
455 RTW89_HW_RATE_V1_MCS29 = 0x11D,
456 RTW89_HW_RATE_V1_MCS30 = 0x11E,
457 RTW89_HW_RATE_V1_MCS31 = 0x11F,
458 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
459 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
460 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
461 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
462 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
463 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
464 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
465 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
466 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
467 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
468 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
469 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
470 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
471 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
472 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
473 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
474 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
475 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
476 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
477 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
478 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
479 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
480 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
481 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
482 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
483 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
484 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
485 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
486 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
487 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
488 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
489 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
490 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
491 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
492 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
493 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
494 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
495 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
496 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
497 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
498 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
499 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
500 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
501 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
502 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
503 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
504 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
505 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
506 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
507 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
508 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
509 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
510 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
511 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
512 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
513 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
514 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
515 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
516 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
517 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
518 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
519 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
520 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
521 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
522 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
523 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
524 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
525 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
526 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
527 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
528 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
529 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
530 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
531 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
532 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
533 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
534 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
535 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
536 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
537 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
538 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
539 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
540 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
541 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
542 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
543 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
544 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
545 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
546 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
547 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
548 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
549 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
550 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
551 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
552 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
553 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
554 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
555 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
556 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
557 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
558 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
559 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
560 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
561 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
562 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
563 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
564 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
565 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
566 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
567 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
568 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
569 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
570 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
571 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
572 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
573 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
574 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
575 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
576 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
577 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
578 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
579 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
580 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
581 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
582 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
583 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
584 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
585 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
586 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
587 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
588 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
589 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
590 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
591 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
592 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
593 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
594 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
595 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
596 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
597 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
598 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
599 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
600 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
601 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
602 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
603 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
604 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
605 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
606 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
607 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
608 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
609 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
610 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
611 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
617 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
619 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
694 RTW89_NSS_1 = 0,
704 RTW89_1TX = 0,
710 RTW89_NONBF = 0,
716 RTW89_NON_OFDMA = 0,
722 RTW89_WW = 0,
742 RTW89_REG_6GHZ_POWER_VLP = 0,
759 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
821 RTW89_MAC_0 = 0,
827 RTW89_PHY_0 = 0,
833 RTW89_CHANCTX_0 = 0,
841 RF_PATH_A = 0,
859 RF_A = BIT(0),
880 RTW89_CHANNEL_WIDTH_20 = 0,
895 RTW89_PS_MODE_NONE = 0,
908 RTW89_PE_DURATION_0 = 0,
915 RTW89_RU26 = 0,
924 RTW89_SC_DONT_CARE = 0,
1199 BTC_NCNT_POWER_ON = 0x0,
1224 BTC_BTINFO_L0 = 0,
1236 BTC_DCNT_RUN = 0x0,
1264 BTC_WCNT_SCANAP = 0x0,
1285 BTC_BCNT_RETRY = 0x0,
1311 BTC_BT_NOPROFILE = 0,
1312 BTC_BT_HFP = BIT(0),
1334 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1337 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1415 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1686 u8 active; /* 0:rlink is under doze */
1802 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1920 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
1921 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
1981 BTC_SCAN_INQ = 0,
1991 CXSCAN_BG = 0,
1997 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2109 BTC_BCNT_RFK_REQ = 0,
2123 BTC_BCNT_RFK_REQ_V105 = 0,
2284 CXECTL_OFF = 0x0, /* tdma off */
2285 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2286 CXECTL_EXT = 0x2,
2297 CXST_OFF = 0x0,
2298 CXST_B2W = 0x1,
2299 CXST_W1 = 0x2,
2300 CXST_W2 = 0x3,
2301 CXST_W2B = 0x4,
2302 CXST_B1 = 0x5,
2303 CXST_B2 = 0x6,
2304 CXST_B3 = 0x7,
2305 CXST_B4 = 0x8,
2306 CXST_LK = 0x9,
2307 CXST_BLK = 0xa,
2308 CXST_E2G = 0xb,
2309 CXST_E5G = 0xc,
2310 CXST_EBT = 0xd,
2311 CXST_ENULL = 0xe,
2312 CXST_WLK = 0xf,
2313 CXST_W1FDD = 0x10,
2314 CXST_B1FDD = 0x11,
2315 CXST_MAX = 0x12,
2319 CXEVNT_TDMA_ENTRY = 0x0,
2349 CXBCN_ALL = 0x0,
2357 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2358 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2363 CXT_BT = 0x0,
2364 CXT_WL = 0x1,
2369 CXT_FLCTRL_OFF = 0x0,
2370 CXT_FLCTRL_ON = 0x1,
2375 CXSTEP_NONE = 0x0,
2376 CXSTEP_EVNT = 0x1,
2377 CXSTEP_SLOT = 0x2,
2382 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2383 RPT_BT_AFH_SEQ_LE = 0x20
2392 __le32 pre_state; /* the debug signal is 1 or 0 */
2474 __le16 cxtbl_l16; /* coex table [15:0] */
2611 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2618 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2623 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2625 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2629 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2636 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2641 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2643 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2651 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2759 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2760 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2761 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2768 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2769 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2770 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2794 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2805 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2856 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2858 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2870 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2941 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
2972 BTF_EVNT_RPT = 0,
2984 BTC_RPT_TYPE_CTRL = 0x0,
3005 REG_MAC = 0x0,
3006 REG_BB = 0x1,
3007 REG_RF = 0x2,
3008 REG_BT_RF = 0x3,
3009 REG_BT_MODEM = 0x4,
3010 REG_BT_BLUEWIZE = 0x5,
3011 REG_BT_VENDOR = 0x6,
3012 REG_BT_LE = 0x7,
3091 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3181 RTW89_BTC_HMSG_TMR_EN = 0x0,
3182 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3183 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3184 RTW89_BTC_HMSG_FW_EV = 0x3,
3185 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3186 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3192 RTW89_RA_MODE_CCK = BIT(0),
3210 RTW89_DIG_NOISY_LEVEL1 = 0,
3217 RTW89_GILTF_LGI_4XHE32 = 0,
3227 RTW89_RX_TYPE_MGNT = 0,
3234 RTW89_EFUSE_BLOCK_SYS = 0,
3680 RTW89_DMA_ACH0 = 0,
3700 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3701 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3704 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3705 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3707 DBCC_LEGACY = 0xffffffff,
3763 #define grp_0 0
3972 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
4361 RTW89_HCIFC_POH = 0,
4379 RTW89_RPR_MODE_POH = 0,
4509 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4510 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4758 RTW89_RFK_STATE_START = 0x0,
4759 RTW89_RFK_STATE_OK = 0x1,
4760 RTW89_RFK_STATE_FAIL = 0x2,
4761 RTW89_RFK_STATE_TIMEOUT = 0x3,
4762 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
4934 RTW89_PKT_BASED_AVG_MODE = 0,
4940 RTW89_PHY_DCFO_STATE_NORMAL = 0,
4947 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4984 RTW89_TSSI_NORMAL = 0,
4989 TSSI_ALIMK_2G = 0,
5054 RTW89_IFS_CLM_INIT = 0,
5064 RTW89_RAC_RELEASE = 0,
5087 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5098 RTW89_CCX_EDCCA_BW20_0 = 0,
5170 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5177 RTW89_LAST_RPWM_PS = 0x0,
5178 RTW89_LAST_RPWM_ACTIVE = 0x6,
5207 RTW89_BB_GAIN_BAND_2G = 0,
5220 RTW89_BB_GAIN_BAND_2G_BE = 0,
5237 RTW89_BB_BW_20_40 = 0,
5252 RTW89_CMAC_BW_20M = 0,
5262 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5263 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5264 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5307 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5310 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5721 int ret = 0; in rtw89_hci_poll_txdma_ch_idle()
5736 int ret = 0; in rtw89_hci_rst_bdram()
5887 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); in rtw89_write32_mask()
5900 mask &= 0xffff; in rtw89_write16_mask()
5914 mask &= 0xff; in rtw89_write8_mask()
6063 case 0 ... 36: in rtw89_he_rua_to_ru_alloc()
6309 return 0x10; in rtw89_chip_get_thermal()
6361 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); in rtw89_chip_cfg_txpwr_ul_tb_offset()
6466 return 0; in rtw89_chip_h2c_dctl_sec_cam()