Lines Matching +full:0 +full:x4f000
21 #define IQK_DONE_8822C 0xaa
57 efuse->country_code[0] = map->country_code[0]; in rtw8822c_read_efuse()
60 efuse->regd = map->rf_board_option & 0x7; in rtw8822c_read_efuse()
65 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; in rtw8822c_read_efuse()
67 for (i = 0; i < 4; i++) in rtw8822c_read_efuse()
85 return 0; in rtw8822c_read_efuse()
115 u32 rf_addr[DACK_RF_8822C] = {0x8f}; in rtw8822c_dac_backup_reg()
116 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, in rtw8822c_dac_backup_reg()
117 0x1c3c, 0x1c24, 0x1d70, 0x9b4, in rtw8822c_dac_backup_reg()
118 0x1a00, 0x1a14, 0x1d58, 0x1c38, in rtw8822c_dac_backup_reg()
119 0x1e24, 0x1e28, 0x1860, 0x4160}; in rtw8822c_dac_backup_reg()
121 for (i = 0; i < DACK_REG_8822C; i++) { in rtw8822c_dac_backup_reg()
127 for (path = 0; path < DACK_PATH_8822C; path++) { in rtw8822c_dac_backup_reg()
128 for (i = 0; i < DACK_RF_8822C; i++) { in rtw8822c_dac_backup_reg()
147 for (path = 0; path < DACK_PATH_8822C; path++) { in rtw8822c_dac_restore_reg()
148 for (i = 0; i < DACK_RF_8822C; i++) { in rtw8822c_dac_restore_reg()
159 if (value >= 0x200) { in rtw8822c_rf_minmax_cmp()
160 if (*min >= 0x200) { in rtw8822c_rf_minmax_cmp()
166 if (*max >= 0x200) { in rtw8822c_rf_minmax_cmp()
171 if (*min < 0x200) { in rtw8822c_rf_minmax_cmp()
176 if (*max >= 0x200) { in rtw8822c_rf_minmax_cmp()
187 if (*v1 >= 0x200 && *v2 >= 0x200) { in __rtw8822c_dac_iq_sort()
190 } else if (*v1 < 0x200 && *v2 < 0x200) { in __rtw8822c_dac_iq_sort()
193 } else if (*v1 < 0x200 && *v2 >= 0x200) { in __rtw8822c_dac_iq_sort()
202 for (i = 0; i < DACK_SN_8822C - 1; i++) { in rtw8822c_dac_iq_sort()
203 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { in rtw8822c_dac_iq_sort()
214 m = 0; in rtw8822c_dac_iq_offset()
215 p = 0; in rtw8822c_dac_iq_offset()
217 if (vec[i] > 0x200) in rtw8822c_dac_iq_offset()
218 m = (0x400 - vec[i]) + m; in rtw8822c_dac_iq_offset()
229 if (t != 0x0) in rtw8822c_dac_iq_offset()
230 t = 0x400 - t; in rtw8822c_dac_iq_offset()
242 base_addr = 0x1800; in rtw8822c_get_path_write_addr()
245 base_addr = 0x4100; in rtw8822c_get_path_write_addr()
261 base_addr = 0x2800; in rtw8822c_get_path_read_addr()
264 base_addr = 0x4500; in rtw8822c_get_path_read_addr()
278 if ((value >= 0x200 && (0x400 - value) > 0x64) || in rtw8822c_dac_iq_check()
279 (value < 0x200 && value > 0x64)) { in rtw8822c_dac_iq_check()
290 int i = 0, cnt = 0; in rtw8822c_dac_cal_iq_sample()
294 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); in rtw8822c_dac_cal_iq_sample()
295 iv[i] = (temp & 0x3ff000) >> 12; in rtw8822c_dac_cal_iq_sample()
296 qv[i] = temp & 0x3ff; in rtw8822c_dac_cal_iq_sample()
308 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; in rtw8822c_dac_cal_iq_search()
311 int i, cnt = 0; in rtw8822c_dac_cal_iq_search()
314 i_min = iv[0]; in rtw8822c_dac_cal_iq_search()
315 i_max = iv[0]; in rtw8822c_dac_cal_iq_search()
316 q_min = qv[0]; in rtw8822c_dac_cal_iq_search()
317 q_max = qv[0]; in rtw8822c_dac_cal_iq_search()
318 for (i = 0; i < DACK_SN_8822C; i++) { in rtw8822c_dac_cal_iq_search()
323 if (i_max < 0x200 && i_min < 0x200) in rtw8822c_dac_cal_iq_search()
325 else if (i_max >= 0x200 && i_min >= 0x200) in rtw8822c_dac_cal_iq_search()
328 i_delta = i_max + (0x400 - i_min); in rtw8822c_dac_cal_iq_search()
330 if (q_max < 0x200 && q_min < 0x200) in rtw8822c_dac_cal_iq_search()
332 else if (q_max >= 0x200 && q_min >= 0x200) in rtw8822c_dac_cal_iq_search()
335 q_delta = q_max + (0x400 - q_min); in rtw8822c_dac_cal_iq_search()
338 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", in rtw8822c_dac_cal_iq_search()
341 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", in rtw8822c_dac_cal_iq_search()
347 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); in rtw8822c_dac_cal_iq_search()
348 iv[0] = (temp & 0x3ff000) >> 12; in rtw8822c_dac_cal_iq_search()
349 qv[0] = temp & 0x3ff; in rtw8822c_dac_cal_iq_search()
350 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); in rtw8822c_dac_cal_iq_search()
351 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; in rtw8822c_dac_cal_iq_search()
352 qv[DACK_SN_8822C - 1] = temp & 0x3ff; in rtw8822c_dac_cal_iq_search()
368 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); in rtw8822c_dac_cal_rf_mode()
369 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); in rtw8822c_dac_cal_rf_mode()
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); in rtw8822c_dac_cal_rf_mode()
372 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); in rtw8822c_dac_cal_rf_mode()
380 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); in rtw8822c_dac_bb_setting()
381 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); in rtw8822c_dac_bb_setting()
382 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); in rtw8822c_dac_bb_setting()
383 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); in rtw8822c_dac_bb_setting()
384 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); in rtw8822c_dac_bb_setting()
385 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); in rtw8822c_dac_bb_setting()
386 rtw_write32(rtwdev, 0x1b00, 0x00000008); in rtw8822c_dac_bb_setting()
387 rtw_write8(rtwdev, 0x1bcc, 0x3f); in rtw8822c_dac_bb_setting()
388 rtw_write32(rtwdev, 0x1b00, 0x0000000a); in rtw8822c_dac_bb_setting()
389 rtw_write8(rtwdev, 0x1bcc, 0x3f); in rtw8822c_dac_bb_setting()
390 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); in rtw8822c_dac_bb_setting()
391 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); in rtw8822c_dac_bb_setting()
398 u32 ic = 0, qc = 0, temp = 0; in rtw8822c_dac_cal_adc()
408 path_sel = 0xa0000; in rtw8822c_dac_cal_adc()
411 path_sel = 0x80000; in rtw8822c_dac_cal_adc()
419 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); in rtw8822c_dac_cal_adc()
421 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); in rtw8822c_dac_cal_adc()
422 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); in rtw8822c_dac_cal_adc()
423 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_adc()
424 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); in rtw8822c_dac_cal_adc()
425 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); in rtw8822c_dac_cal_adc()
426 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); in rtw8822c_dac_cal_adc()
427 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); in rtw8822c_dac_cal_adc()
428 for (i = 0; i < 10; i++) { in rtw8822c_dac_cal_adc()
430 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); in rtw8822c_dac_cal_adc()
431 rtw_write32(rtwdev, 0x1c24, 0x00010002); in rtw8822c_dac_cal_adc()
434 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); in rtw8822c_dac_cal_adc()
437 if (ic != 0x0) { in rtw8822c_dac_cal_adc()
438 ic = 0x400 - ic; in rtw8822c_dac_cal_adc()
441 if (qc != 0x0) { in rtw8822c_dac_cal_adc()
442 qc = 0x400 - qc; in rtw8822c_dac_cal_adc()
445 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); in rtw8822c_dac_cal_adc()
446 rtw_write32(rtwdev, base_addr + 0x68, temp); in rtw8822c_dac_cal_adc()
448 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", in rtw8822c_dac_cal_adc()
449 base_addr + 0x68, temp); in rtw8822c_dac_cal_adc()
451 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); in rtw8822c_dac_cal_adc()
454 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); in rtw8822c_dac_cal_adc()
455 if (ic >= 0x200) in rtw8822c_dac_cal_adc()
456 ic = 0x400 - ic; in rtw8822c_dac_cal_adc()
457 if (qc >= 0x200) in rtw8822c_dac_cal_adc()
458 qc = 0x400 - qc; in rtw8822c_dac_cal_adc()
464 rtw_write32(rtwdev, 0x1c3c, 0x00000003); in rtw8822c_dac_cal_adc()
465 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); in rtw8822c_dac_cal_adc()
466 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); in rtw8822c_dac_cal_adc()
469 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); in rtw8822c_dac_cal_adc()
481 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); in rtw8822c_dac_cal_step1()
482 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_step1()
484 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); in rtw8822c_dac_cal_step1()
485 rtw_write32(rtwdev, 0x1c38, 0xffffffff); in rtw8822c_dac_cal_step1()
487 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step1()
488 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_step1()
489 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); in rtw8822c_dac_cal_step1()
490 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); in rtw8822c_dac_cal_step1()
491 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); in rtw8822c_dac_cal_step1()
492 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); in rtw8822c_dac_cal_step1()
493 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); in rtw8822c_dac_cal_step1()
494 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); in rtw8822c_dac_cal_step1()
495 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); in rtw8822c_dac_cal_step1()
497 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); in rtw8822c_dac_cal_step1()
499 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); in rtw8822c_dac_cal_step1()
500 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); in rtw8822c_dac_cal_step1()
502 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); in rtw8822c_dac_cal_step1()
503 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); in rtw8822c_dac_cal_step1()
505 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_step1()
506 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) in rtw8822c_dac_cal_step1()
508 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); in rtw8822c_dac_cal_step1()
510 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); in rtw8822c_dac_cal_step1()
511 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); in rtw8822c_dac_cal_step1()
512 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step1()
513 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); in rtw8822c_dac_cal_step1()
514 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); in rtw8822c_dac_cal_step1()
524 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); in rtw8822c_dac_cal_step2()
525 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); in rtw8822c_dac_cal_step2()
526 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); in rtw8822c_dac_cal_step2()
527 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); in rtw8822c_dac_cal_step2()
529 rtw_write32(rtwdev, 0x1b00, 0x00000008); in rtw8822c_dac_cal_step2()
530 rtw_write8(rtwdev, 0x1bcc, 0x03f); in rtw8822c_dac_cal_step2()
531 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_step2()
532 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step2()
533 rtw_write32(rtwdev, 0x1c3c, 0x00088103); in rtw8822c_dac_cal_step2()
540 if (ic != 0x0) in rtw8822c_dac_cal_step2()
541 ic = 0x400 - ic; in rtw8822c_dac_cal_step2()
542 if (qc != 0x0) in rtw8822c_dac_cal_step2()
543 qc = 0x400 - qc; in rtw8822c_dac_cal_step2()
544 if (ic < 0x300) { in rtw8822c_dac_cal_step2()
546 ic = ic + 0x80; in rtw8822c_dac_cal_step2()
548 ic = (0x400 - ic) * 2 * 6 / 5; in rtw8822c_dac_cal_step2()
549 ic = 0x7f - ic; in rtw8822c_dac_cal_step2()
551 if (qc < 0x300) { in rtw8822c_dac_cal_step2()
553 qc = qc + 0x80; in rtw8822c_dac_cal_step2()
555 qc = (0x400 - qc) * 2 * 6 / 5; in rtw8822c_dac_cal_step2()
556 qc = 0x7f - qc; in rtw8822c_dac_cal_step2()
562 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); in rtw8822c_dac_cal_step2()
563 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); in rtw8822c_dac_cal_step2()
581 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); in rtw8822c_dac_cal_step3()
582 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step3()
583 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_step3()
584 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); in rtw8822c_dac_cal_step3()
585 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); in rtw8822c_dac_cal_step3()
586 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); in rtw8822c_dac_cal_step3()
587 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); in rtw8822c_dac_cal_step3()
588 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); in rtw8822c_dac_cal_step3()
589 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); in rtw8822c_dac_cal_step3()
590 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); in rtw8822c_dac_cal_step3()
591 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); in rtw8822c_dac_cal_step3()
592 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); in rtw8822c_dac_cal_step3()
593 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); in rtw8822c_dac_cal_step3()
594 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); in rtw8822c_dac_cal_step3()
596 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); in rtw8822c_dac_cal_step3()
598 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); in rtw8822c_dac_cal_step3()
599 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); in rtw8822c_dac_cal_step3()
601 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); in rtw8822c_dac_cal_step3()
602 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); in rtw8822c_dac_cal_step3()
604 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || in rtw8822c_dac_cal_step3()
605 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) in rtw8822c_dac_cal_step3()
607 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); in rtw8822c_dac_cal_step3()
609 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); in rtw8822c_dac_cal_step3()
610 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); in rtw8822c_dac_cal_step3()
613 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); in rtw8822c_dac_cal_step3()
614 rtw_write32(rtwdev, base_addr + 0x68, temp); in rtw8822c_dac_cal_step3()
615 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); in rtw8822c_dac_cal_step3()
616 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); in rtw8822c_dac_cal_step3()
618 if (ic >= 0x10) in rtw8822c_dac_cal_step3()
619 ic = ic - 0x10; in rtw8822c_dac_cal_step3()
621 ic = 0x400 - (0x10 - ic); in rtw8822c_dac_cal_step3()
623 if (qc >= 0x10) in rtw8822c_dac_cal_step3()
624 qc = qc - 0x10; in rtw8822c_dac_cal_step3()
626 qc = 0x400 - (0x10 - qc); in rtw8822c_dac_cal_step3()
631 if (ic >= 0x200) in rtw8822c_dac_cal_step3()
632 ic = 0x400 - ic; in rtw8822c_dac_cal_step3()
633 if (qc >= 0x200) in rtw8822c_dac_cal_step3()
634 qc = 0x400 - qc; in rtw8822c_dac_cal_step3()
640 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); in rtw8822c_dac_cal_step3()
647 rtw_write32(rtwdev, base_addr + 0x68, 0x0); in rtw8822c_dac_cal_step4()
648 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); in rtw8822c_dac_cal_step4()
649 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); in rtw8822c_dac_cal_step4()
650 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); in rtw8822c_dac_cal_step4()
663 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { in rtw8822c_dac_cal_backup_vec()
664 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); in rtw8822c_dac_cal_backup_vec()
665 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); in rtw8822c_dac_cal_backup_vec()
672 u32 w_off = 0x1c; in rtw8822c_dac_cal_backup_path()
673 u32 r_off = 0x2c; in rtw8822c_dac_cal_backup_path()
680 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; in rtw8822c_dac_cal_backup_path()
681 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; in rtw8822c_dac_cal_backup_path()
682 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); in rtw8822c_dac_cal_backup_path()
685 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; in rtw8822c_dac_cal_backup_path()
686 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; in rtw8822c_dac_cal_backup_path()
695 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
696 dm_info->dack_dck[RF_PATH_A][0][0] = val; in rtw8822c_dac_cal_backup_dck()
697 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); in rtw8822c_dac_cal_backup_dck()
698 dm_info->dack_dck[RF_PATH_A][0][1] = val; in rtw8822c_dac_cal_backup_dck()
699 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
700 dm_info->dack_dck[RF_PATH_A][1][0] = val; in rtw8822c_dac_cal_backup_dck()
701 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); in rtw8822c_dac_cal_backup_dck()
704 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
705 dm_info->dack_dck[RF_PATH_B][0][0] = val; in rtw8822c_dac_cal_backup_dck()
706 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); in rtw8822c_dac_cal_backup_dck()
707 dm_info->dack_dck[RF_PATH_B][1][0] = val; in rtw8822c_dac_cal_backup_dck()
708 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); in rtw8822c_dac_cal_backup_dck()
709 dm_info->dack_dck[RF_PATH_B][0][1] = val; in rtw8822c_dac_cal_backup_dck()
710 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); in rtw8822c_dac_cal_backup_dck()
718 temp[0] = rtw_read32(rtwdev, 0x1860); in rtw8822c_dac_cal_backup()
719 temp[1] = rtw_read32(rtwdev, 0x4160); in rtw8822c_dac_cal_backup()
720 temp[2] = rtw_read32(rtwdev, 0x9b4); in rtw8822c_dac_cal_backup()
723 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_backup()
726 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); in rtw8822c_dac_cal_backup()
727 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); in rtw8822c_dac_cal_backup()
731 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); in rtw8822c_dac_cal_backup()
732 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); in rtw8822c_dac_cal_backup()
736 rtw_write32_set(rtwdev, 0x1830, BIT(30)); in rtw8822c_dac_cal_backup()
737 rtw_write32_set(rtwdev, 0x4130, BIT(30)); in rtw8822c_dac_cal_backup()
739 rtw_write32(rtwdev, 0x1860, temp[0]); in rtw8822c_dac_cal_backup()
740 rtw_write32(rtwdev, 0x4160, temp[1]); in rtw8822c_dac_cal_backup()
741 rtw_write32(rtwdev, 0x9b4, temp[2]); in rtw8822c_dac_cal_backup()
750 val = dm_info->dack_dck[RF_PATH_A][0][0]; in rtw8822c_dac_cal_restore_dck()
751 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
752 val = dm_info->dack_dck[RF_PATH_A][0][1]; in rtw8822c_dac_cal_restore_dck()
753 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
756 val = dm_info->dack_dck[RF_PATH_A][1][0]; in rtw8822c_dac_cal_restore_dck()
757 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
759 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
762 val = dm_info->dack_dck[RF_PATH_B][0][0]; in rtw8822c_dac_cal_restore_dck()
763 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
764 val = dm_info->dack_dck[RF_PATH_B][0][1]; in rtw8822c_dac_cal_restore_dck()
765 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
768 val = dm_info->dack_dck[RF_PATH_B][1][0]; in rtw8822c_dac_cal_restore_dck()
769 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); in rtw8822c_dac_cal_restore_dck()
771 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); in rtw8822c_dac_cal_restore_dck()
776 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); in rtw8822c_dac_cal_restore_prepare()
778 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
779 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
780 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
781 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); in rtw8822c_dac_cal_restore_prepare()
783 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); in rtw8822c_dac_cal_restore_prepare()
784 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); in rtw8822c_dac_cal_restore_prepare()
785 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
786 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
788 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); in rtw8822c_dac_cal_restore_prepare()
789 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); in rtw8822c_dac_cal_restore_prepare()
790 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
791 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
793 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
794 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
795 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
796 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
798 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
799 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
800 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
801 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
805 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
806 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
807 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
808 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); in rtw8822c_dac_cal_restore_prepare()
810 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
811 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
813 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
814 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
815 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); in rtw8822c_dac_cal_restore_prepare()
816 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); in rtw8822c_dac_cal_restore_prepare()
818 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
819 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); in rtw8822c_dac_cal_restore_prepare()
820 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
821 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); in rtw8822c_dac_cal_restore_prepare()
823 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
824 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); in rtw8822c_dac_cal_restore_prepare()
830 u32 cnt = 0; in rtw8822c_dac_cal_restore_wait()
833 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); in rtw8822c_dac_cal_restore_wait()
834 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); in rtw8822c_dac_cal_restore_wait()
836 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) in rtw8822c_dac_cal_restore_wait()
847 u32 w_off = 0x1c; in rtw8822c_dac_cal_restore_path()
848 u32 r_off = 0x2c; in rtw8822c_dac_cal_restore_path()
853 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; in rtw8822c_dac_cal_restore_path()
854 r_i = rtw8822c_get_path_read_addr(path) + 0x08; in rtw8822c_dac_cal_restore_path()
855 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; in rtw8822c_dac_cal_restore_path()
856 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; in rtw8822c_dac_cal_restore_path()
858 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) in rtw8822c_dac_cal_restore_path()
861 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { in rtw8822c_dac_cal_restore_path()
862 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
863 value = dm_info->dack_msbk[path][0][i]; in rtw8822c_dac_cal_restore_path()
864 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); in rtw8822c_dac_cal_restore_path()
865 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); in rtw8822c_dac_cal_restore_path()
866 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); in rtw8822c_dac_cal_restore_path()
869 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
871 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) in rtw8822c_dac_cal_restore_path()
874 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { in rtw8822c_dac_cal_restore_path()
875 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
877 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); in rtw8822c_dac_cal_restore_path()
878 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); in rtw8822c_dac_cal_restore_path()
879 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); in rtw8822c_dac_cal_restore_path()
881 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); in rtw8822c_dac_cal_restore_path()
883 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); in rtw8822c_dac_cal_restore_path()
884 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); in rtw8822c_dac_cal_restore_path()
885 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); in rtw8822c_dac_cal_restore_path()
886 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); in rtw8822c_dac_cal_restore_path()
908 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && in rtw8822c_dac_cal_restore()
909 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && in rtw8822c_dac_cal_restore()
910 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && in rtw8822c_dac_cal_restore()
911 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) in rtw8822c_dac_cal_restore()
914 temp[0] = rtw_read32(rtwdev, 0x1860); in rtw8822c_dac_cal_restore()
915 temp[1] = rtw_read32(rtwdev, 0x4160); in rtw8822c_dac_cal_restore()
916 temp[2] = rtw_read32(rtwdev, 0x9b4); in rtw8822c_dac_cal_restore()
919 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_restore()
920 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_restore()
921 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || in rtw8822c_dac_cal_restore()
922 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) in rtw8822c_dac_cal_restore()
930 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); in rtw8822c_dac_cal_restore()
931 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); in rtw8822c_dac_cal_restore()
932 rtw_write32(rtwdev, 0x1860, temp[0]); in rtw8822c_dac_cal_restore()
933 rtw_write32(rtwdev, 0x4160, temp[1]); in rtw8822c_dac_cal_restore()
934 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
935 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
936 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
937 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); in rtw8822c_dac_cal_restore()
938 rtw_write32(rtwdev, 0x9b4, temp[2]); in rtw8822c_dac_cal_restore()
947 u32 ic = 0, qc = 0, i; in rtw8822c_rf_dac_cal()
948 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; in rtw8822c_rf_dac_cal()
949 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; in rtw8822c_rf_dac_cal()
950 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; in rtw8822c_rf_dac_cal()
963 for (i = 0; i < 10; i++) { in rtw8822c_rf_dac_cal()
979 for (i = 0; i < 10; i++) { in rtw8822c_rf_dac_cal()
993 rtw_write32(rtwdev, 0x1b00, 0x00000008); in rtw8822c_rf_dac_cal()
994 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); in rtw8822c_rf_dac_cal()
995 rtw_write8(rtwdev, 0x1bcc, 0x0); in rtw8822c_rf_dac_cal()
996 rtw_write32(rtwdev, 0x1b00, 0x0000000a); in rtw8822c_rf_dac_cal()
997 rtw_write8(rtwdev, 0x1bcc, 0x0); in rtw8822c_rf_dac_cal()
1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); in rtw8822c_rf_dac_cal()
1005 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); in rtw8822c_rf_dac_cal()
1006 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); in rtw8822c_rf_dac_cal()
1007 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); in rtw8822c_rf_dac_cal()
1015 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); in rtw8822c_rf_x2_check()
1017 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); in rtw8822c_rf_x2_check()
1018 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); in rtw8822c_rf_x2_check()
1019 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); in rtw8822c_rf_x2_check()
1028 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ in rtw8822c_set_power_trim()
1029 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ in rtw8822c_set_power_trim()
1031 } while (0) in rtw8822c_set_power_trim()
1034 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_set_power_trim()
1035 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); in rtw8822c_set_power_trim()
1036 RF_SET_POWER_TRIM(path, 0x0, 0); in rtw8822c_set_power_trim()
1037 RF_SET_POWER_TRIM(path, 0x1, 1); in rtw8822c_set_power_trim()
1038 RF_SET_POWER_TRIM(path, 0x2, 2); in rtw8822c_set_power_trim()
1039 RF_SET_POWER_TRIM(path, 0x3, 2); in rtw8822c_set_power_trim()
1040 RF_SET_POWER_TRIM(path, 0x4, 3); in rtw8822c_set_power_trim()
1041 RF_SET_POWER_TRIM(path, 0x5, 4); in rtw8822c_set_power_trim()
1042 RF_SET_POWER_TRIM(path, 0x6, 5); in rtw8822c_set_power_trim()
1043 RF_SET_POWER_TRIM(path, 0x7, 6); in rtw8822c_set_power_trim()
1044 RF_SET_POWER_TRIM(path, 0x8, 7); in rtw8822c_set_power_trim()
1045 RF_SET_POWER_TRIM(path, 0x9, 3); in rtw8822c_set_power_trim()
1046 RF_SET_POWER_TRIM(path, 0xa, 4); in rtw8822c_set_power_trim()
1047 RF_SET_POWER_TRIM(path, 0xb, 5); in rtw8822c_set_power_trim()
1048 RF_SET_POWER_TRIM(path, 0xc, 6); in rtw8822c_set_power_trim()
1049 RF_SET_POWER_TRIM(path, 0xd, 7); in rtw8822c_set_power_trim()
1050 RF_SET_POWER_TRIM(path, 0xe, 7); in rtw8822c_set_power_trim()
1051 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); in rtw8822c_set_power_trim()
1058 u8 pg_pwr = 0xff, i, path, idx; in rtw8822c_power_trim()
1067 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { in rtw8822c_power_trim()
1076 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { in rtw8822c_power_trim()
1077 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_power_trim()
1096 u8 pg_therm = 0xff, thermal[2] = {0}, path; in rtw8822c_thermal_trim()
1098 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_thermal_trim()
1102 /* Efuse value of BIT(0) shall be move to BIT(3), and the value in rtw8822c_thermal_trim()
1106 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); in rtw8822c_thermal_trim()
1107 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); in rtw8822c_thermal_trim()
1115 u8 pg_pa_bias = 0xff, path; in rtw8822c_pa_bias()
1117 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_pa_bias()
1125 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_pa_bias()
1146 u4b_tmp == 0, 20, 600000, false, in rtw8822c_rfk_handshake()
1184 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_rfk_power_save()
1187 is_power_save ? 0 : 1); in rtw8822c_rfk_power_save()
1196 for (i = 0; i < reg_num; i++) { in rtw8822c_txgapk_backup_bb_reg()
1199 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n", in rtw8822c_txgapk_backup_bb_reg()
1210 for (i = 0; i < reg_num; i++) { in rtw8822c_txgapk_reload_bb_reg()
1212 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n", in rtw8822c_txgapk_reload_bb_reg()
1238 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2); in rtw8822c_txgapk_tx_pause()
1252 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1); in rtw8822c_txgapk_bb_dpk()
1254 BIT_IQK_DPK_CLOCK_SRC, 0x1); in rtw8822c_txgapk_bb_dpk()
1256 BIT_IQK_DPK_RESET_SRC, 0x1); in rtw8822c_txgapk_bb_dpk()
1257 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1); in rtw8822c_txgapk_bb_dpk()
1258 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0); in rtw8822c_txgapk_bb_dpk()
1259 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff); in rtw8822c_txgapk_bb_dpk()
1263 BIT_RFTXEN_GCK_FORCE_ON, 0x1); in rtw8822c_txgapk_bb_dpk()
1264 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1); in rtw8822c_txgapk_bb_dpk()
1266 BIT_TX_SCALE_0DB, 0x1); in rtw8822c_txgapk_bb_dpk()
1267 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0); in rtw8822c_txgapk_bb_dpk()
1270 BIT_RFTXEN_GCK_FORCE_ON, 0x1); in rtw8822c_txgapk_bb_dpk()
1272 BIT_DIS_SHARERX_TXGAT, 0x1); in rtw8822c_txgapk_bb_dpk()
1274 BIT_TX_SCALE_0DB, 0x1); in rtw8822c_txgapk_bb_dpk()
1275 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0); in rtw8822c_txgapk_bb_dpk()
1277 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2); in rtw8822c_txgapk_bb_dpk()
1296 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); in rtw8822c_txgapk_afe_dpk()
1297 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); in rtw8822c_txgapk_afe_dpk()
1298 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001); in rtw8822c_txgapk_afe_dpk()
1299 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001); in rtw8822c_txgapk_afe_dpk()
1300 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001); in rtw8822c_txgapk_afe_dpk()
1301 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001); in rtw8822c_txgapk_afe_dpk()
1302 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001); in rtw8822c_txgapk_afe_dpk()
1303 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001); in rtw8822c_txgapk_afe_dpk()
1304 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001); in rtw8822c_txgapk_afe_dpk()
1305 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001); in rtw8822c_txgapk_afe_dpk()
1306 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001); in rtw8822c_txgapk_afe_dpk()
1307 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001); in rtw8822c_txgapk_afe_dpk()
1308 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001); in rtw8822c_txgapk_afe_dpk()
1309 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001); in rtw8822c_txgapk_afe_dpk()
1310 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001); in rtw8822c_txgapk_afe_dpk()
1311 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001); in rtw8822c_txgapk_afe_dpk()
1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); in rtw8822c_txgapk_afe_dpk()
1313 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); in rtw8822c_txgapk_afe_dpk()
1330 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e); in rtw8822c_txgapk_afe_dpk_restore()
1331 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041); in rtw8822c_txgapk_afe_dpk_restore()
1332 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041); in rtw8822c_txgapk_afe_dpk_restore()
1333 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041); in rtw8822c_txgapk_afe_dpk_restore()
1334 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041); in rtw8822c_txgapk_afe_dpk_restore()
1335 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041); in rtw8822c_txgapk_afe_dpk_restore()
1336 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041); in rtw8822c_txgapk_afe_dpk_restore()
1337 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041); in rtw8822c_txgapk_afe_dpk_restore()
1338 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041); in rtw8822c_txgapk_afe_dpk_restore()
1339 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041); in rtw8822c_txgapk_afe_dpk_restore()
1340 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041); in rtw8822c_txgapk_afe_dpk_restore()
1341 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041); in rtw8822c_txgapk_afe_dpk_restore()
1342 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041); in rtw8822c_txgapk_afe_dpk_restore()
1343 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041); in rtw8822c_txgapk_afe_dpk_restore()
1344 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041); in rtw8822c_txgapk_afe_dpk_restore()
1345 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041); in rtw8822c_txgapk_afe_dpk_restore()
1346 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041); in rtw8822c_txgapk_afe_dpk_restore()
1353 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1354 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1355 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1357 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1358 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1359 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1360 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); in rtw8822c_txgapk_bb_dpk_restore()
1361 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1); in rtw8822c_txgapk_bb_dpk_restore()
1362 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1363 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1364 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); in rtw8822c_txgapk_bb_dpk_restore()
1365 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1366 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1370 BIT_RFTXEN_GCK_FORCE_ON, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1371 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1373 BIT_TX_SCALE_0DB, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1374 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3); in rtw8822c_txgapk_bb_dpk_restore()
1377 BIT_RFTXEN_GCK_FORCE_ON, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1379 BIT_DIS_SHARERX_TXGAT, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1381 BIT_TX_SCALE_0DB, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1382 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3); in rtw8822c_txgapk_bb_dpk_restore()
1385 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0); in rtw8822c_txgapk_bb_dpk_restore()
1386 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5); in rtw8822c_txgapk_bb_dpk_restore()
1391 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) && in _rtw8822c_txgapk_gain_valid()
1392 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe)) in _rtw8822c_txgapk_gain_valid()
1402 u32 v, tmp_3f = 0; in _rtw8822c_txgapk_write_gain_bb_table()
1409 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); in _rtw8822c_txgapk_write_gain_bb_table()
1412 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); in _rtw8822c_txgapk_write_gain_bb_table()
1415 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); in _rtw8822c_txgapk_write_gain_bb_table()
1418 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); in _rtw8822c_txgapk_write_gain_bb_table()
1424 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88); in _rtw8822c_txgapk_write_gain_bb_table()
1426 check_txgain = 0; in _rtw8822c_txgapk_write_gain_bb_table()
1427 for (gain = 0; gain < RF_GAIN_NUM; gain++) { in _rtw8822c_txgapk_write_gain_bb_table()
1435 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", in _rtw8822c_txgapk_write_gain_bb_table()
1443 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1); in _rtw8822c_txgapk_write_gain_bb_table()
1444 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0); in _rtw8822c_txgapk_write_gain_bb_table()
1447 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n", in _rtw8822c_txgapk_write_gain_bb_table()
1459 for (band = 0; band < RF_BAND_MAX; band++) { in rtw8822c_txgapk_write_gain_bb_table()
1460 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk_write_gain_bb_table()
1469 static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a}; in rtw8822c_txgapk_read_offset()
1470 static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b}; in rtw8822c_txgapk_read_offset()
1487 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000); in rtw8822c_txgapk_read_offset()
1488 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3); in rtw8822c_txgapk_read_offset()
1489 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312); in rtw8822c_txgapk_read_offset()
1490 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1); in rtw8822c_txgapk_read_offset()
1491 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0); in rtw8822c_txgapk_read_offset()
1492 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1); in rtw8822c_txgapk_read_offset()
1493 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820); in rtw8822c_txgapk_read_offset()
1495 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); in rtw8822c_txgapk_read_offset()
1497 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018); in rtw8822c_txgapk_read_offset()
1509 val == 0x55, 1000, 100000, false, in rtw8822c_txgapk_read_offset()
1512 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2); in rtw8822c_txgapk_read_offset()
1514 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1); in rtw8822c_txgapk_read_offset()
1515 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12); in rtw8822c_txgapk_read_offset()
1516 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3); in rtw8822c_txgapk_read_offset()
1519 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); in rtw8822c_txgapk_read_offset()
1528 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4); in rtw8822c_txgapk_read_offset()
1534 for (i = 0; i < RF_HW_OFFSET_NUM; i++) in rtw8822c_txgapk_read_offset()
1537 0xf0; in rtw8822c_txgapk_read_offset()
1538 for (i = 0; i < RF_HW_OFFSET_NUM; i++) in rtw8822c_txgapk_read_offset()
1550 u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0}; in rtw8822c_txgapk_calculate_offset()
1560 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_calculate_offset()
1562 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); in rtw8822c_txgapk_calculate_offset()
1563 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_calculate_offset()
1564 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); in rtw8822c_txgapk_calculate_offset()
1565 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f); in rtw8822c_txgapk_calculate_offset()
1566 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0); in rtw8822c_txgapk_calculate_offset()
1567 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1); in rtw8822c_txgapk_calculate_offset()
1568 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f); in rtw8822c_txgapk_calculate_offset()
1569 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); in rtw8822c_txgapk_calculate_offset()
1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); in rtw8822c_txgapk_calculate_offset()
1571 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); in rtw8822c_txgapk_calculate_offset()
1572 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); in rtw8822c_txgapk_calculate_offset()
1574 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00); in rtw8822c_txgapk_calculate_offset()
1575 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); in rtw8822c_txgapk_calculate_offset()
1582 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); in rtw8822c_txgapk_calculate_offset()
1584 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); in rtw8822c_txgapk_calculate_offset()
1585 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_txgapk_calculate_offset()
1586 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); in rtw8822c_txgapk_calculate_offset()
1587 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011); in rtw8822c_txgapk_calculate_offset()
1588 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3); in rtw8822c_txgapk_calculate_offset()
1589 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3); in rtw8822c_txgapk_calculate_offset()
1590 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); in rtw8822c_txgapk_calculate_offset()
1592 RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2); in rtw8822c_txgapk_calculate_offset()
1593 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12); in rtw8822c_txgapk_calculate_offset()
1594 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); in rtw8822c_txgapk_calculate_offset()
1595 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); in rtw8822c_txgapk_calculate_offset()
1596 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); in rtw8822c_txgapk_calculate_offset()
1597 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5); in rtw8822c_txgapk_calculate_offset()
1599 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); in rtw8822c_txgapk_calculate_offset()
1603 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); in rtw8822c_txgapk_calculate_offset()
1606 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); in rtw8822c_txgapk_calculate_offset()
1609 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); in rtw8822c_txgapk_calculate_offset()
1625 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3); in rtw8822c_txgapk_rf_restore()
1626 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0); in rtw8822c_txgapk_rf_restore()
1627 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0); in rtw8822c_txgapk_rf_restore()
1639 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n", in rtw8822c_txgapk_cal_gain()
1645 new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0); in rtw8822c_txgapk_cal_gain()
1648 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n", in rtw8822c_txgapk_cal_gain()
1657 u32 i, j, tmp = 0x20, tmp_3f, v; in rtw8822c_txgapk_write_tx_gain()
1658 s8 offset_tmp[RF_GAIN_NUM] = {0}; in rtw8822c_txgapk_write_tx_gain()
1664 tmp = 0x20; in rtw8822c_txgapk_write_tx_gain()
1667 tmp = 0x200; in rtw8822c_txgapk_write_tx_gain()
1670 tmp = 0x280; in rtw8822c_txgapk_write_tx_gain()
1673 tmp = 0x300; in rtw8822c_txgapk_write_tx_gain()
1680 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk_write_tx_gain()
1681 for (i = 0; i < RF_GAIN_NUM; i++) { in rtw8822c_txgapk_write_tx_gain()
1682 offset_tmp[i] = 0; in rtw8822c_txgapk_write_tx_gain()
1695 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", in rtw8822c_txgapk_write_tx_gain()
1705 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000); in rtw8822c_txgapk_write_tx_gain()
1706 for (i = 0; i < RF_GAIN_NUM; i++) { in rtw8822c_txgapk_write_tx_gain()
1717 "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n", in rtw8822c_txgapk_write_tx_gain()
1720 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0); in rtw8822c_txgapk_write_tx_gain()
1729 static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5}; in rtw8822c_txgapk_save_all_tx_gain_table()
1730 static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0}; in rtw8822c_txgapk_save_all_tx_gain_table()
1746 for (band = 0; band < RF_BAND_MAX; band++) { in rtw8822c_txgapk_save_all_tx_gain_table()
1747 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk_save_all_tx_gain_table()
1751 three_wire[path], BIT_3WIRE_EN, 0x0); in rtw8822c_txgapk_save_all_tx_gain_table()
1760 gain = 0; in rtw8822c_txgapk_save_all_tx_gain_table()
1769 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n", in rtw8822c_txgapk_save_all_tx_gain_table()
1776 three_wire[path], BIT_3WIRE_EN, 0x3); in rtw8822c_txgapk_save_all_tx_gain_table()
1794 if (txgapk->read_txgain == 0) { in rtw8822c_txgapk()
1796 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n"); in rtw8822c_txgapk()
1810 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_txgapk()
1853 dm_info->delta_power_index[path] = 0; in rtw8822c_pwrtrack_init()
1855 dm_info->thermal_avg[path] = 0xff; in rtw8822c_pwrtrack_init()
1868 u8 cck_gi_u_bnd_msb = 0; in rtw8822c_phy_set_param()
1869 u8 cck_gi_u_bnd_lsb = 0; in rtw8822c_phy_set_param()
1870 u8 cck_gi_l_bnd_msb = 0; in rtw8822c_phy_set_param()
1871 u8 cck_gi_l_bnd_lsb = 0; in rtw8822c_phy_set_param()
1889 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; in rtw8822c_phy_set_param()
1890 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, in rtw8822c_phy_set_param()
1901 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); in rtw8822c_phy_set_param()
1902 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); in rtw8822c_phy_set_param()
1903 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); in rtw8822c_phy_set_param()
1904 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); in rtw8822c_phy_set_param()
1915 #define WLAN_TXQ_RPT_EN 0x1F
1916 #define WLAN_SLOT_TIME 0x09
1917 #define WLAN_PIFS_TIME 0x1C
1918 #define WLAN_SIFS_CCK_CONT_TX 0x0A
1919 #define WLAN_SIFS_OFDM_CONT_TX 0x0E
1920 #define WLAN_SIFS_CCK_TRX 0x0A
1921 #define WLAN_SIFS_OFDM_TRX 0x10
1922 #define WLAN_NAV_MAX 0xC8
1923 #define WLAN_RDG_NAV 0x05
1924 #define WLAN_TXOP_NAV 0x1B
1925 #define WLAN_CCK_RX_TSF 0x30
1926 #define WLAN_OFDM_RX_TSF 0x30
1927 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
1928 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
1929 #define WLAN_DRV_EARLY_INT 0x04
1930 #define WLAN_BCN_CTRL_CLT0 0x10
1931 #define WLAN_BCN_DMA_TIME 0x02
1932 #define WLAN_BCN_MAX_ERR 0xFF
1933 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1934 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1935 #define WLAN_SIFS_CCK_CTX 0x0A
1936 #define WLAN_SIFS_CCK_IRX 0x0A
1937 #define WLAN_SIFS_OFDM_CTX 0x0E
1938 #define WLAN_SIFS_OFDM_IRX 0x0E
1939 #define WLAN_EIFS_DUR_TUNE 0x40
1940 #define WLAN_EDCA_VO_PARAM 0x002FA226
1941 #define WLAN_EDCA_VI_PARAM 0x005EA328
1942 #define WLAN_EDCA_BE_PARAM 0x005EA42B
1943 #define WLAN_EDCA_BK_PARAM 0x0000A44F
1945 #define WLAN_RX_FILTER0 0xFFFFFFFF
1946 #define WLAN_RX_FILTER2 0xFFFF
1947 #define WLAN_RCR_CFG 0xE400220E
1951 #define WLAN_AMPDU_MAX_TIME 0x70
1952 #define WLAN_RTS_LEN_TH 0xFF
1953 #define WLAN_RTS_TX_TIME_TH 0x08
1954 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f
1955 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f
1956 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1957 #define FAST_EDCA_VO_TH 0x06
1958 #define FAST_EDCA_VI_TH 0x06
1959 #define FAST_EDCA_BE_TH 0x06
1960 #define FAST_EDCA_BK_TH 0x06
1961 #define WLAN_BAR_RETRY_LIMIT 0x01
1962 #define WLAN_BAR_ACK_TYPE 0x05
1963 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1964 #define WLAN_RESP_TXRATE 0x84
1965 #define WLAN_ACK_TO 0x21
1966 #define WLAN_ACK_TO_CCK 0x6A
1967 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1968 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1969 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1970 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1971 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1972 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1973 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1974 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1975 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1976 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1977 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
1978 #define WLAN_MULTI_ADDR 0xFFFFFFFF
1980 #define WLAN_TX_FUNC_CFG1 0x30
1981 #define WLAN_TX_FUNC_CFG2 0x30
1982 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
1983 #define WLAN_MAC_OPT_LB_FUNC1 0x80
1984 #define WLAN_MAC_OPT_FUNC2 0xb0810041
1985 #define WLAN_MAC_INT_MIG_CFG 0x33330000
2002 #define EFUSE_PCB_INFO_OFFSET 0xCA
2039 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); in rtw8822c_mac_init()
2074 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); in rtw8822c_mac_init()
2107 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; in rtw8822c_mac_init()
2111 value16 = 0; in rtw8822c_mac_init()
2117 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); in rtw8822c_mac_init()
2122 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); in rtw8822c_mac_init()
2130 return 0; in rtw8822c_mac_init()
2133 #define FWCD_SIZE_REG_8822C 0x2000
2134 #define FWCD_SIZE_DMEM_8822C 0x10000
2135 #define FWCD_SIZE_IMEM_8822C 0x10000
2136 #define FWCD_SIZE_EMEM_8822C 0x20000
2137 #define FWCD_SIZE_ROM_8822C 0x10000
2159 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C); in rtw8822c_dump_fw_crash()
2175 return 0; in rtw8822c_dump_fw_crash()
2183 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); in rtw8822c_rstb_3wire()
2184 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); in rtw8822c_rstb_3wire()
2185 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); in rtw8822c_rstb_3wire()
2187 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); in rtw8822c_rstb_3wire()
2194 #define RF18_BAND_2G (0) in rtw8822c_set_channel_rf()
2205 u32 rf_reg18 = 0; in rtw8822c_set_channel_rf()
2206 u32 rf_rxbb = 0; in rtw8822c_set_channel_rf()
2208 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822c_set_channel_rf()
2226 rf_rxbb = 0x18; in rtw8822c_set_channel_rf()
2231 rf_rxbb = 0x10; in rtw8822c_set_channel_rf()
2235 rf_rxbb = 0x8; in rtw8822c_set_channel_rf()
2241 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); in rtw8822c_set_channel_rf()
2242 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); in rtw8822c_set_channel_rf()
2243 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); in rtw8822c_set_channel_rf()
2244 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); in rtw8822c_set_channel_rf()
2246 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); in rtw8822c_set_channel_rf()
2247 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); in rtw8822c_set_channel_rf()
2248 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); in rtw8822c_set_channel_rf()
2249 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); in rtw8822c_set_channel_rf()
2261 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); in rtw8822c_toggle_igi()
2262 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); in rtw8822c_toggle_igi()
2263 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); in rtw8822c_toggle_igi()
2264 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); in rtw8822c_toggle_igi()
2265 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); in rtw8822c_toggle_igi()
2276 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); in rtw8822c_set_channel_bb()
2281 0x5); in rtw8822c_set_channel_bb()
2283 0x5); in rtw8822c_set_channel_bb()
2285 0x6); in rtw8822c_set_channel_bb()
2287 0x6); in rtw8822c_set_channel_bb()
2291 0x4); in rtw8822c_set_channel_bb()
2293 0x4); in rtw8822c_set_channel_bb()
2295 0x0); in rtw8822c_set_channel_bb()
2297 0x0); in rtw8822c_set_channel_bb()
2301 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); in rtw8822c_set_channel_bb()
2303 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); in rtw8822c_set_channel_bb()
2305 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); in rtw8822c_set_channel_bb()
2307 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); in rtw8822c_set_channel_bb()
2309 0x4962c931); in rtw8822c_set_channel_bb()
2310 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); in rtw8822c_set_channel_bb()
2311 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); in rtw8822c_set_channel_bb()
2312 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); in rtw8822c_set_channel_bb()
2313 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); in rtw8822c_set_channel_bb()
2315 0xff012455); in rtw8822c_set_channel_bb()
2316 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); in rtw8822c_set_channel_bb()
2318 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); in rtw8822c_set_channel_bb()
2320 0x3e18fec8); in rtw8822c_set_channel_bb()
2321 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); in rtw8822c_set_channel_bb()
2322 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); in rtw8822c_set_channel_bb()
2323 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); in rtw8822c_set_channel_bb()
2325 0x00faf0de); in rtw8822c_set_channel_bb()
2327 0x00122344); in rtw8822c_set_channel_bb()
2329 0x0fffffff); in rtw8822c_set_channel_bb()
2332 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); in rtw8822c_set_channel_bb()
2334 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); in rtw8822c_set_channel_bb()
2340 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); in rtw8822c_set_channel_bb()
2341 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); in rtw8822c_set_channel_bb()
2344 0x1); in rtw8822c_set_channel_bb()
2346 0x1); in rtw8822c_set_channel_bb()
2349 0x2); in rtw8822c_set_channel_bb()
2351 0x2); in rtw8822c_set_channel_bb()
2354 0x3); in rtw8822c_set_channel_bb()
2356 0x3); in rtw8822c_set_channel_bb()
2360 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); in rtw8822c_set_channel_bb()
2362 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); in rtw8822c_set_channel_bb()
2364 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); in rtw8822c_set_channel_bb()
2366 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); in rtw8822c_set_channel_bb()
2368 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); in rtw8822c_set_channel_bb()
2370 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); in rtw8822c_set_channel_bb()
2375 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); in rtw8822c_set_channel_bb()
2376 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); in rtw8822c_set_channel_bb()
2377 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); in rtw8822c_set_channel_bb()
2378 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); in rtw8822c_set_channel_bb()
2379 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); in rtw8822c_set_channel_bb()
2380 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); in rtw8822c_set_channel_bb()
2381 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2382 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); in rtw8822c_set_channel_bb()
2386 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); in rtw8822c_set_channel_bb()
2387 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); in rtw8822c_set_channel_bb()
2388 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); in rtw8822c_set_channel_bb()
2389 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, in rtw8822c_set_channel_bb()
2391 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); in rtw8822c_set_channel_bb()
2392 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2393 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); in rtw8822c_set_channel_bb()
2396 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); in rtw8822c_set_channel_bb()
2397 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); in rtw8822c_set_channel_bb()
2398 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, in rtw8822c_set_channel_bb()
2400 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); in rtw8822c_set_channel_bb()
2401 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); in rtw8822c_set_channel_bb()
2404 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); in rtw8822c_set_channel_bb()
2405 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); in rtw8822c_set_channel_bb()
2406 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); in rtw8822c_set_channel_bb()
2407 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); in rtw8822c_set_channel_bb()
2408 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); in rtw8822c_set_channel_bb()
2409 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); in rtw8822c_set_channel_bb()
2410 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2411 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); in rtw8822c_set_channel_bb()
2414 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); in rtw8822c_set_channel_bb()
2415 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); in rtw8822c_set_channel_bb()
2416 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); in rtw8822c_set_channel_bb()
2417 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); in rtw8822c_set_channel_bb()
2418 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); in rtw8822c_set_channel_bb()
2419 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); in rtw8822c_set_channel_bb()
2420 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); in rtw8822c_set_channel_bb()
2421 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); in rtw8822c_set_channel_bb()
2438 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); in rtw8822c_config_cck_rx_path()
2439 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); in rtw8822c_config_cck_rx_path()
2441 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); in rtw8822c_config_cck_rx_path()
2442 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); in rtw8822c_config_cck_rx_path()
2446 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); in rtw8822c_config_cck_rx_path()
2448 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); in rtw8822c_config_cck_rx_path()
2450 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); in rtw8822c_config_cck_rx_path()
2456 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); in rtw8822c_config_ofdm_rx_path()
2457 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); in rtw8822c_config_ofdm_rx_path()
2458 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); in rtw8822c_config_ofdm_rx_path()
2459 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); in rtw8822c_config_ofdm_rx_path()
2460 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); in rtw8822c_config_ofdm_rx_path()
2462 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); in rtw8822c_config_ofdm_rx_path()
2463 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); in rtw8822c_config_ofdm_rx_path()
2464 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); in rtw8822c_config_ofdm_rx_path()
2465 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); in rtw8822c_config_ofdm_rx_path()
2466 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); in rtw8822c_config_ofdm_rx_path()
2469 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); in rtw8822c_config_ofdm_rx_path()
2470 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); in rtw8822c_config_ofdm_rx_path()
2483 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); in rtw8822c_config_cck_tx_path()
2485 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); in rtw8822c_config_cck_tx_path()
2488 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); in rtw8822c_config_cck_tx_path()
2490 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); in rtw8822c_config_cck_tx_path()
2499 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); in rtw8822c_config_ofdm_tx_path()
2500 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); in rtw8822c_config_ofdm_tx_path()
2502 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); in rtw8822c_config_ofdm_tx_path()
2503 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); in rtw8822c_config_ofdm_tx_path()
2506 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); in rtw8822c_config_ofdm_tx_path()
2507 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); in rtw8822c_config_ofdm_tx_path()
2509 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32); in rtw8822c_config_ofdm_tx_path()
2510 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); in rtw8822c_config_ofdm_tx_path()
2512 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); in rtw8822c_config_ofdm_tx_path()
2513 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); in rtw8822c_config_ofdm_tx_path()
2533 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); in rtw8822c_config_trx_mode()
2535 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); in rtw8822c_config_trx_mode()
2537 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); in rtw8822c_config_trx_mode()
2539 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); in rtw8822c_config_trx_mode()
2579 if (channel != 0) in query_phy_status_page0()
2587 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page0()
2606 u8 evm_dbm = 0; in query_phy_status_page1()
2616 if (rxsc == 0) in query_phy_status_page1()
2647 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page1()
2662 if (rx_evm < 0) { in query_phy_status_page1()
2664 evm_dbm = 0; in query_phy_status_page1()
2678 page = *phy_status & 0xf; in query_phy_status()
2681 case 0: in query_phy_status()
2701 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8822c_query_rx_desc()
2740 u32 txref_cck[2] = {0x18a0, 0x41a0}; in rtw8822c_set_write_tx_power_ref()
2741 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; in rtw8822c_set_write_tx_power_ref()
2744 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822c_set_write_tx_power_ref()
2745 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); in rtw8822c_set_write_tx_power_ref()
2746 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, in rtw8822c_set_write_tx_power_ref()
2749 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822c_set_write_tx_power_ref()
2750 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); in rtw8822c_set_write_tx_power_ref()
2751 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, in rtw8822c_set_write_tx_power_ref()
2759 u32 offset_txagc = 0x3a00; in rtw8822c_set_tx_power_diff()
2760 u8 rate_idx = rate & 0xfc; in rtw8822c_set_tx_power_diff()
2765 for (i = 0; i < 4; i++) in rtw8822c_set_tx_power_diff()
2766 pwr_idx[i] = diff_idx[i] & 0x7f; in rtw8822c_set_tx_power_diff()
2768 phy_pwr_idx = pwr_idx[0] | in rtw8822c_set_tx_power_diff()
2773 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); in rtw8822c_set_tx_power_diff()
2791 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { in rtw8822c_set_tx_power_index()
2792 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8822c_set_tx_power_index()
2796 if (rs == 0) { in rtw8822c_set_tx_power_index()
2797 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; in rtw8822c_set_tx_power_index()
2800 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; in rtw8822c_set_tx_power_index()
2823 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); in rtw8822c_set_antenna()
2833 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); in rtw8822c_set_antenna()
2842 return 0; in rtw8822c_set_antenna()
2876 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); in rtw8822c_false_alarm_statistics()
2878 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); in rtw8822c_false_alarm_statistics()
2879 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); in rtw8822c_false_alarm_statistics()
2881 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); in rtw8822c_false_alarm_statistics()
2890 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; in rtw8822c_false_alarm_statistics()
2892 crc32_cnt = rtw_read32(rtwdev, 0x2c04); in rtw8822c_false_alarm_statistics()
2893 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2894 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2895 crc32_cnt = rtw_read32(rtwdev, 0x2c14); in rtw8822c_false_alarm_statistics()
2896 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2897 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2898 crc32_cnt = rtw_read32(rtwdev, 0x2c10); in rtw8822c_false_alarm_statistics()
2899 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2900 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2901 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); in rtw8822c_false_alarm_statistics()
2902 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2903 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822c_false_alarm_statistics()
2905 cca32_cnt = rtw_read32(rtwdev, 0x2c08); in rtw8822c_false_alarm_statistics()
2906 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); in rtw8822c_false_alarm_statistics()
2907 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; in rtw8822c_false_alarm_statistics()
2912 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); in rtw8822c_false_alarm_statistics()
2914 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); in rtw8822c_false_alarm_statistics()
2928 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010); in rtw8822c_do_lck()
2929 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA); in rtw8822c_do_lck()
2931 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000); in rtw8822c_do_lck()
2932 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001); in rtw8822c_do_lck()
2933 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000, in rtw8822c_do_lck()
2934 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000); in rtw8822c_do_lck()
2935 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8); in rtw8822c_do_lck()
2936 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010); in rtw8822c_do_lck()
2938 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); in rtw8822c_do_lck()
2939 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000); in rtw8822c_do_lck()
2941 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); in rtw8822c_do_lck()
2946 struct rtw_iqk_para para = {0}; in rtw8822c_do_iqk()
2958 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); in rtw8822c_do_iqk()
2968 /* 0x790[5:0]=0x5 */ in rtw8822c_coex_cfg_init()
2969 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8822c_coex_cfg_init()
2972 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8822c_coex_cfg_init()
2988 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000); in rtw8822c_coex_cfg_init()
3003 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) in rtw8822c_coex_cfg_gnt_fix()
3004 rf_0x1 = 0x40021; in rtw8822c_coex_cfg_gnt_fix()
3006 rf_0x1 = 0x40000; in rtw8822c_coex_cfg_gnt_fix()
3012 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); in rtw8822c_coex_cfg_gnt_fix()
3016 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 in rtw8822c_coex_cfg_gnt_fix()
3018 * enable "DAC off if GNT_WL = 0" for non-shared-antenna in rtw8822c_coex_cfg_gnt_fix()
3019 * disable 0x1c30[22] = 0, in rtw8822c_coex_cfg_gnt_fix()
3020 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 in rtw8822c_coex_cfg_gnt_fix()
3024 BIT_ANAPAR_BTPS >> 16, 0); in rtw8822c_coex_cfg_gnt_fix()
3029 BIT_DAC_OFF_ENABLE, 0); in rtw8822c_coex_cfg_gnt_fix()
3052 BIT_PI_IGNORE_GNT_BT, 0); in rtw8822c_coex_cfg_gnt_fix()
3062 BIT_PI_IGNORE_GNT_BT, 0); in rtw8822c_coex_cfg_gnt_fix()
3065 BIT_NOMASK_TXBT_ENABLE, 0); in rtw8822c_coex_cfg_gnt_fix()
3072 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822c_coex_cfg_gnt_debug()
3073 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822c_coex_cfg_gnt_debug()
3074 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); in rtw8822c_coex_cfg_gnt_debug()
3075 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822c_coex_cfg_gnt_debug()
3076 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); in rtw8822c_coex_cfg_gnt_debug()
3086 coex_rfe->ant_switch_polarity = 0; in rtw8822c_coex_cfg_rfe_type()
3097 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); in rtw8822c_coex_cfg_rfe_type()
3098 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822c_coex_cfg_rfe_type()
3099 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822c_coex_cfg_rfe_type()
3127 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22); in rtw8822c_coex_cfg_wl_rx_gain()
3128 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36); in rtw8822c_coex_cfg_wl_rx_gain()
3129 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22); in rtw8822c_coex_cfg_wl_rx_gain()
3130 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36); in rtw8822c_coex_cfg_wl_rx_gain()
3136 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20); in rtw8822c_coex_cfg_wl_rx_gain()
3137 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0); in rtw8822c_coex_cfg_wl_rx_gain()
3138 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20); in rtw8822c_coex_cfg_wl_rx_gain()
3139 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0); in rtw8822c_coex_cfg_wl_rx_gain()
3147 u8 csi_rsc = 0; in rtw8822c_bf_enable_bfee_su()
3160 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); in rtw8822c_bf_enable_bfee_su()
3217 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); in rtw8822c_dpk_set_gnt_wl()
3218 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); in rtw8822c_dpk_set_gnt_wl()
3219 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); in rtw8822c_dpk_set_gnt_wl()
3220 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); in rtw8822c_dpk_set_gnt_wl()
3222 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, in rtw8822c_dpk_set_gnt_wl()
3224 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); in rtw8822c_dpk_set_gnt_wl()
3233 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_restore_registers()
3234 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); in rtw8822c_dpk_restore_registers()
3243 for (i = 0; i < reg_num; i++) { in rtw8822c_dpk_backup_registers()
3256 for (i = 0; i < DPK_RF_REG_NUM; i++) { in rtw8822c_dpk_backup_rf_registers()
3270 for (i = 0; i < DPK_RF_REG_NUM; i++) { in rtw8822c_dpk_reload_rf_registers()
3284 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822c_dpk_information()
3288 dpk_info->dpk_ch = FIELD_GET(0xff, reg); in rtw8822c_dpk_information()
3289 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); in rtw8822c_dpk_information()
3294 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); in rtw8822c_dpk_rxbb_dc_cal()
3296 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); in rtw8822c_dpk_rxbb_dc_cal()
3298 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); in rtw8822c_dpk_rxbb_dc_cal()
3306 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); in rtw8822c_dpk_dc_corr_check()
3308 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); in rtw8822c_dpk_dc_corr_check()
3311 dc_i = 0x1000 - dc_i; in rtw8822c_dpk_dc_corr_check()
3313 dc_q = 0x1000 - dc_q; in rtw8822c_dpk_dc_corr_check()
3315 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); in rtw8822c_dpk_dc_corr_check()
3316 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); in rtw8822c_dpk_dc_corr_check()
3322 return 0; in rtw8822c_dpk_dc_corr_check()
3329 u16 count = 0; in rtw8822c_dpk_tx_pause()
3331 rtw_write8(rtwdev, 0x522, 0xff); in rtw8822c_dpk_tx_pause()
3332 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); in rtw8822c_dpk_tx_pause()
3335 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); in rtw8822c_dpk_tx_pause()
3336 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); in rtw8822c_dpk_tx_pause()
3360 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_pre_setting()
3361 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); in rtw8822c_dpk_pre_setting()
3362 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); in rtw8822c_dpk_pre_setting()
3364 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); in rtw8822c_dpk_pre_setting()
3366 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); in rtw8822c_dpk_pre_setting()
3367 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); in rtw8822c_dpk_pre_setting()
3368 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); in rtw8822c_dpk_pre_setting()
3370 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_pre_setting()
3371 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); in rtw8822c_dpk_pre_setting()
3372 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); in rtw8822c_dpk_pre_setting()
3379 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); in rtw8822c_dpk_rf_setting()
3382 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); in rtw8822c_dpk_rf_setting()
3383 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); in rtw8822c_dpk_rf_setting()
3384 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0); in rtw8822c_dpk_rf_setting()
3388 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1); in rtw8822c_dpk_rf_setting()
3389 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); in rtw8822c_dpk_rf_setting()
3391 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); in rtw8822c_dpk_rf_setting()
3392 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); in rtw8822c_dpk_rf_setting()
3393 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); in rtw8822c_dpk_rf_setting()
3394 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); in rtw8822c_dpk_rf_setting()
3397 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); in rtw8822c_dpk_rf_setting()
3398 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); in rtw8822c_dpk_rf_setting()
3399 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); in rtw8822c_dpk_rf_setting()
3402 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); in rtw8822c_dpk_rf_setting()
3404 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); in rtw8822c_dpk_rf_setting()
3406 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); in rtw8822c_dpk_rf_setting()
3410 return ori_txbb & 0x1f; in rtw8822c_dpk_rf_setting()
3416 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; in rtw8822c_dpk_get_cmd()
3420 cmd = 0x14 + path; in rtw8822c_dpk_get_cmd()
3423 cmd = 0x16 + path + bw; in rtw8822c_dpk_get_cmd()
3426 cmd = 0x1a + path; in rtw8822c_dpk_get_cmd()
3429 cmd = 0x1c + path + bw; in rtw8822c_dpk_get_cmd()
3432 return 0; in rtw8822c_dpk_get_cmd()
3435 return (cmd << 8) | 0x48; in rtw8822c_dpk_get_cmd()
3441 u8 result = 0; in rtw8822c_dpk_one_shot()
3446 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); in rtw8822c_dpk_one_shot()
3447 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); in rtw8822c_dpk_one_shot()
3448 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); in rtw8822c_dpk_one_shot()
3450 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { in rtw8822c_dpk_one_shot()
3456 0x8 | (path << 1)); in rtw8822c_dpk_one_shot()
3457 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); in rtw8822c_dpk_one_shot()
3463 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { in rtw8822c_dpk_one_shot()
3468 0x8 | (path << 1)); in rtw8822c_dpk_one_shot()
3469 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); in rtw8822c_dpk_one_shot()
3474 rtw_write8(rtwdev, 0x1b10, 0x0); in rtw8822c_dpk_one_shot()
3483 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_dgain_read()
3484 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); in rtw8822c_dpk_dgain_read()
3493 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); in rtw8822c_dpk_thermal_read()
3494 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); in rtw8822c_dpk_thermal_read()
3495 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); in rtw8822c_dpk_thermal_read()
3498 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); in rtw8822c_dpk_thermal_read()
3505 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); in rtw8822c_dpk_pas_read()
3506 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); in rtw8822c_dpk_pas_read()
3507 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); in rtw8822c_dpk_pas_read()
3508 rtw_write32(rtwdev, 0x1b4c, 0x00000000); in rtw8822c_dpk_pas_read()
3509 rtw_write32(rtwdev, 0x1b4c, 0x00080000); in rtw8822c_dpk_pas_read()
3515 i_val = 0x10000 - i_val; in rtw8822c_dpk_pas_read()
3517 q_val = 0x10000 - q_val; in rtw8822c_dpk_pas_read()
3519 rtw_write32(rtwdev, 0x1b4c, 0x00000000); in rtw8822c_dpk_pas_read()
3528 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, in rtw8822c_psd_log2base()
3530 42, 32, 23, 15, 7, 0}; in rtw8822c_psd_log2base()
3532 if (val == 0) in rtw8822c_psd_log2base()
3533 return 0; in rtw8822c_psd_log2base()
3554 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_gainloss_result()
3555 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); in rtw8822c_dpk_gainloss_result()
3556 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); in rtw8822c_dpk_gainloss_result()
3558 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); in rtw8822c_dpk_gainloss_result()
3560 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); in rtw8822c_dpk_gainloss_result()
3568 u8 result = 0; in rtw8822c_dpk_agc_gain_chk()
3587 if (loss < 0x4000000) in rtw8822c_dpk_agc_loss_chk()
3644 if (pga > 0xe) in rtw8822c_gain_large_state()
3645 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); in rtw8822c_gain_large_state()
3646 else if (pga > 0xb && pga < 0xf) in rtw8822c_gain_large_state()
3647 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); in rtw8822c_gain_large_state()
3648 else if (pga < 0xc) in rtw8822c_gain_large_state()
3659 if (pga < 0xc) in rtw8822c_gain_less_state()
3660 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); in rtw8822c_gain_less_state()
3661 else if (pga > 0xb && pga < 0xf) in rtw8822c_gain_less_state()
3662 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); in rtw8822c_gain_less_state()
3663 else if (pga > 0xe) in rtw8822c_gain_less_state()
3672 u8 txbb_bound[] = {0x1f, 0}; in rtw8822c_gl_state()
3683 data->limited_pga = 0; in rtw8822c_gl_state()
3697 return rtw8822c_gl_state(rtwdev, data, 0); in rtw8822c_gl_less_state()
3721 struct rtw8822c_dpk_data data = {0}; in rtw8822c_dpk_pas_agc()
3742 if (coef_i == 0x1000 || coef_i == 0x0fff || in rtw8822c_dpk_coef_iq_check()
3743 coef_q == 0x1000 || coef_q == 0x0fff) in rtw8822c_dpk_coef_iq_check()
3751 u32 reg = 0; in rtw8822c_dpk_coef_transfer()
3752 u16 coef_i = 0, coef_q = 0; in rtw8822c_dpk_coef_transfer()
3756 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; in rtw8822c_dpk_coef_transfer()
3757 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; in rtw8822c_dpk_coef_transfer()
3759 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; in rtw8822c_dpk_coef_transfer()
3767 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
3768 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
3769 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
3770 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
3778 for (i = 0; i < 20; i++) { in rtw8822c_dpk_coef_tbl_apply()
3787 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); in rtw8822c_dpk_get_coef()
3790 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); in rtw8822c_dpk_get_coef()
3791 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); in rtw8822c_dpk_get_coef()
3793 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); in rtw8822c_dpk_get_coef()
3794 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); in rtw8822c_dpk_get_coef()
3806 for (addr = 0; addr < 20; addr++) { in rtw8822c_dpk_coef_read()
3807 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); in rtw8822c_dpk_coef_read()
3808 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); in rtw8822c_dpk_coef_read()
3811 result = 0; in rtw8822c_dpk_coef_read()
3821 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; in rtw8822c_dpk_coef_write()
3825 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); in rtw8822c_dpk_coef_write()
3826 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); in rtw8822c_dpk_coef_write()
3828 for (addr = 0; addr < 20; addr++) { in rtw8822c_dpk_coef_write()
3829 if (result == 0) { in rtw8822c_dpk_coef_write()
3831 coef = 0x04001fff; in rtw8822c_dpk_coef_write()
3833 coef = 0x00001fff; in rtw8822c_dpk_coef_write()
3846 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_fill_result()
3851 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); in rtw8822c_dpk_fill_result()
3882 tx_bb = 0; in rtw8822c_dpk_gainloss()
3903 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_by_path()
3907 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); in rtw8822c_dpk_by_path()
3917 u32 tmp_gs = 0; in rtw8822c_dpk_cal_gs()
3919 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_cal_gs()
3920 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); in rtw8822c_dpk_cal_gs()
3921 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_dpk_cal_gs()
3922 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); in rtw8822c_dpk_cal_gs()
3923 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); in rtw8822c_dpk_cal_gs()
3924 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_cal_gs()
3925 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); in rtw8822c_dpk_cal_gs()
3929 0x1066680); in rtw8822c_dpk_cal_gs()
3930 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); in rtw8822c_dpk_cal_gs()
3933 0x1066680); in rtw8822c_dpk_cal_gs()
3934 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); in rtw8822c_dpk_cal_gs()
3938 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); in rtw8822c_dpk_cal_gs()
3939 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); in rtw8822c_dpk_cal_gs()
3940 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); in rtw8822c_dpk_cal_gs()
3941 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); in rtw8822c_dpk_cal_gs()
3942 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); in rtw8822c_dpk_cal_gs()
3944 0x05020000 | (BIT(path) << 28)); in rtw8822c_dpk_cal_gs()
3946 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); in rtw8822c_dpk_cal_gs()
3947 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); in rtw8822c_dpk_cal_gs()
3948 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); in rtw8822c_dpk_cal_gs()
3949 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); in rtw8822c_dpk_cal_gs()
3950 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); in rtw8822c_dpk_cal_gs()
3952 0x05020008 | (BIT(path) << 28)); in rtw8822c_dpk_cal_gs()
3955 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); in rtw8822c_dpk_cal_gs()
3959 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); in rtw8822c_dpk_cal_gs()
3960 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_cal_gs()
3961 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); in rtw8822c_dpk_cal_gs()
3962 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); in rtw8822c_dpk_cal_gs()
3963 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_cal_gs()
3966 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); in rtw8822c_dpk_cal_gs()
3968 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); in rtw8822c_dpk_cal_gs()
3970 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); in rtw8822c_dpk_cal_gs()
3987 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; in rtw8822c_dpk_cal_coef1()
3991 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); in rtw8822c_dpk_cal_coef1()
3992 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); in rtw8822c_dpk_cal_coef1()
3993 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); in rtw8822c_dpk_cal_coef1()
3994 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); in rtw8822c_dpk_cal_coef1()
3996 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); in rtw8822c_dpk_cal_coef1()
3998 rtw_write8(rtwdev, 0x1b10, 0x0); in rtw8822c_dpk_cal_coef1()
3999 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); in rtw8822c_dpk_cal_coef1()
4001 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_cal_coef1()
4002 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; in rtw8822c_dpk_cal_coef1()
4004 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, in rtw8822c_dpk_cal_coef1()
4007 GENMASK(31, 28), 0x9); in rtw8822c_dpk_cal_coef1()
4009 GENMASK(31, 28), 0x1); in rtw8822c_dpk_cal_coef1()
4011 GENMASK(31, 28), 0x0); in rtw8822c_dpk_cal_coef1()
4013 BIT(14), 0x0); in rtw8822c_dpk_cal_coef1()
4023 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); in rtw8822c_dpk_on()
4024 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); in rtw8822c_dpk_on()
4054 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_result_reset()
4057 0x8 | (path << 1)); in rtw8822c_dpk_result_reset()
4058 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); in rtw8822c_dpk_result_reset()
4060 dpk_info->dpk_txagc[path] = 0; in rtw8822c_dpk_result_reset()
4061 dpk_info->result[path] = 0; in rtw8822c_dpk_result_reset()
4062 dpk_info->dpk_gs[path] = 0x5b; in rtw8822c_dpk_result_reset()
4063 dpk_info->pre_pwsf[path] = 0; in rtw8822c_dpk_result_reset()
4104 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_enable_disable()
4112 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); in rtw8822c_dpk_enable_disable()
4116 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); in rtw8822c_dpk_enable_disable()
4128 dpk_info->dpk_ch == 0) in rtw8822c_dpk_reload_data()
4131 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8822c_dpk_reload_data()
4133 0x8 | (path << 1)); in rtw8822c_dpk_reload_data()
4135 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); in rtw8822c_dpk_reload_data()
4137 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); in rtw8822c_dpk_reload_data()
4146 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); in rtw8822c_dpk_reload_data()
4165 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); in rtw8822c_dpk_reload()
4183 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, in rtw8822c_do_dpk()
4184 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, in rtw8822c_do_dpk()
4185 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; in rtw8822c_do_dpk()
4187 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; in rtw8822c_do_dpk()
4214 for (path = 0; path < rtwdev->hal.rf_path_num; path++) in rtw8822c_do_dpk()
4232 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; in rtw8822c_dpk_track()
4235 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) in rtw8822c_dpk_track()
4238 for (path = 0; path < DPK_RF_PATH_NUM; path++) { in rtw8822c_dpk_track()
4248 offset[path] &= 0x7f; in rtw8822c_dpk_track()
4252 0x8 | (path << 1)); in rtw8822c_dpk_track()
4253 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), in rtw8822c_dpk_track()
4265 u32 val = 0; in rtw8822c_set_crystal_cap_reg()
4310 s32 cfo_avg, cfo_path_sum = 0, cfo_rpt_sum; in rtw8822c_cfo_calc_avg()
4313 for (i = 0; i < path_num; i++) { in rtw8822c_cfo_calc_avg()
4319 cfo_avg = 0; in rtw8822c_cfo_calc_avg()
4324 for (i = 0; i < path_num; i++) { in rtw8822c_cfo_calc_avg()
4325 cfo->cfo_tail[i] = 0; in rtw8822c_cfo_calc_avg()
4326 cfo->cfo_cnt[i] = 0; in rtw8822c_cfo_calc_avg()
4357 s32 cfo_avg = 0; in rtw8822c_cfo_track()
4377 crystal_cap = clamp_t(s8, crystal_cap, 0, XCAP_MASK); in rtw8822c_cfo_track()
4385 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
4386 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
4389 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
4390 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
4431 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n", in rtw8822c_phy_cck_pd_set_reg()
4438 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; in rtw8822c_phy_cck_pd_set()
4439 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; in rtw8822c_phy_cck_pd_set()
4443 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); in rtw8822c_phy_cck_pd_set()
4444 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); in rtw8822c_phy_cck_pd_set()
4465 #define PWR_TRACK_MASK 0x7f
4472 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, in rtw8822c_pwrtrack_set()
4476 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, in rtw8822c_pwrtrack_set()
4488 if (rtwdev->efuse.thermal_meter[path] == 0xff) in rtw8822c_pwr_track_stats()
4491 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); in rtw8822c_pwr_track_stats()
4516 for (i = 0; i < rtwdev->hal.rf_path_num; i++) in __rtw8822c_pwr_track()
4520 for (i = 0; i < rtwdev->hal.rf_path_num; i++) in __rtw8822c_pwr_track()
4529 if (efuse->power_track_type != 0) in rtw8822c_pwr_track()
4533 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4534 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); in rtw8822c_pwr_track()
4535 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4537 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4538 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); in rtw8822c_pwr_track()
4539 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); in rtw8822c_pwr_track()
4567 igi = dm_info->igi_history[0]; in rtw8822c_adaptivity()
4595 {0x0086,
4599 RTW_PWR_CMD_WRITE, BIT(0), 0},
4600 {0x0086,
4605 {0x002E,
4610 {0x002D,
4614 RTW_PWR_CMD_WRITE, BIT(0), 0},
4615 {0x007F,
4619 RTW_PWR_CMD_WRITE, BIT(7), 0},
4620 {0x004A,
4624 RTW_PWR_CMD_WRITE, BIT(0), 0},
4625 {0x0005,
4629 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
4630 {0xFFFF,
4633 0,
4634 RTW_PWR_CMD_END, 0, 0},
4638 {0x0000,
4642 RTW_PWR_CMD_WRITE, BIT(5), 0},
4643 {0x0005,
4647 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
4648 {0x0075,
4652 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4653 {0x0006,
4658 {0x0075,
4662 RTW_PWR_CMD_WRITE, BIT(0), 0},
4663 {0xFF1A,
4667 RTW_PWR_CMD_WRITE, 0xFF, 0},
4668 {0x002E,
4672 RTW_PWR_CMD_WRITE, BIT(3), 0},
4673 {0x0006,
4677 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4678 {0x0005,
4682 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
4683 {0x1018,
4688 {0x0005,
4692 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4693 {0x0005,
4697 RTW_PWR_CMD_POLLING, BIT(0), 0},
4698 {0x0074,
4703 {0x0071,
4707 RTW_PWR_CMD_WRITE, BIT(4), 0},
4708 {0x0062,
4714 {0x0061,
4718 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
4719 {0x001F,
4724 {0x00EF,
4729 {0x1045,
4734 {0x0010,
4739 {0x1064,
4744 {0xFFFF,
4747 0,
4748 RTW_PWR_CMD_END, 0, 0},
4752 {0x0093,
4756 RTW_PWR_CMD_WRITE, BIT(3), 0},
4757 {0x001F,
4761 RTW_PWR_CMD_WRITE, 0xFF, 0},
4762 {0x00EF,
4766 RTW_PWR_CMD_WRITE, 0xFF, 0},
4767 {0x1045,
4771 RTW_PWR_CMD_WRITE, BIT(4), 0},
4772 {0xFF1A,
4776 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
4777 {0x0049,
4781 RTW_PWR_CMD_WRITE, BIT(1), 0},
4782 {0x0006,
4786 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4787 {0x0002,
4791 RTW_PWR_CMD_WRITE, BIT(1), 0},
4792 {0x0005,
4797 {0x0005,
4801 RTW_PWR_CMD_POLLING, BIT(1), 0},
4802 {0x0000,
4807 {0xFFFF,
4810 0,
4811 RTW_PWR_CMD_END, 0, 0},
4815 {0x0005,
4820 {0x0007,
4824 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
4825 {0x0067,
4829 RTW_PWR_CMD_WRITE, BIT(5), 0},
4830 {0x004A,
4834 RTW_PWR_CMD_WRITE, BIT(0), 0},
4835 {0x0081,
4839 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
4840 {0x0090,
4844 RTW_PWR_CMD_WRITE, BIT(1), 0},
4845 {0x0092,
4849 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
4850 {0x0093,
4854 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
4855 {0x0005,
4860 {0x0005,
4865 {0x0086,
4869 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4870 {0xFFFF,
4873 0,
4874 RTW_PWR_CMD_END, 0, 0},
4890 {0xFFFF, 0x00,
4897 {0xFFFF, 0x0000,
4904 {0xFFFF, 0x0000,
4911 {0xFFFF, 0x0000,
4929 [0] = RTW_DEF_RFE(8822c, 0, 0),
4930 [1] = RTW_DEF_RFE(8822c, 0, 0),
4931 [2] = RTW_DEF_RFE(8822c, 0, 0),
4932 [3] = RTW_DEF_RFE(8822c, 0, 0),
4933 [4] = RTW_DEF_RFE(8822c, 0, 0),
4934 [5] = RTW_DEF_RFE(8822c, 0, 5),
4935 [6] = RTW_DEF_RFE(8822c, 0, 0),
4939 [0] = { .addr = 0x1d70, .mask = 0x7f },
4940 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
4952 {64, 64, 0, 0, 1},
4953 {64, 64, 64, 0, 1},
5030 {0xffffffff, 0xffffffff}, /* case-0 */
5031 {0x55555555, 0x55555555},
5032 {0x66555555, 0x66555555},
5033 {0xaaaaaaaa, 0xaaaaaaaa},
5034 {0x5a5a5a5a, 0x5a5a5a5a},
5035 {0xfafafafa, 0xfafafafa}, /* case-5 */
5036 {0x6a5a5555, 0xaaaaaaaa},
5037 {0x6a5a56aa, 0x6a5a56aa},
5038 {0x6a5a5a5a, 0x6a5a5a5a},
5039 {0x66555555, 0x5a5a5a5a},
5040 {0x66555555, 0x6a5a5a5a}, /* case-10 */
5041 {0x66555555, 0x6a5a5aaa},
5042 {0x66555555, 0x5a5a5aaa},
5043 {0x66555555, 0x6aaa5aaa},
5044 {0x66555555, 0xaaaa5aaa},
5045 {0x66555555, 0xaaaaaaaa}, /* case-15 */
5046 {0xffff55ff, 0xfafafafa},
5047 {0xffff55ff, 0x6afa5afa},
5048 {0xaaffffaa, 0xfafafafa},
5049 {0xaa5555aa, 0x5a5a5a5a},
5050 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
5051 {0xaa5555aa, 0xaaaaaaaa},
5052 {0xffffffff, 0x5a5a5a5a},
5053 {0xffffffff, 0x5a5a5a5a},
5054 {0xffffffff, 0x55555555},
5055 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
5056 {0x55555555, 0x5a5a5a5a},
5057 {0x55555555, 0xaaaaaaaa},
5058 {0x55555555, 0x6a5a6a5a},
5059 {0x66556655, 0x66556655},
5060 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
5061 {0xffffffff, 0x5aaa5aaa},
5062 {0x56555555, 0x5a5a5aaa},
5063 {0xdaffdaff, 0xdaffdaff},
5064 {0xddffddff, 0xddffddff},
5069 {0xffffffff, 0xffffffff}, /* case-100 */
5070 {0x55555555, 0x55555555},
5071 {0x66555555, 0x66555555},
5072 {0xaaaaaaaa, 0xaaaaaaaa},
5073 {0x5a5a5a5a, 0x5a5a5a5a},
5074 {0xfafafafa, 0xfafafafa}, /* case-105 */
5075 {0x5afa5afa, 0x5afa5afa},
5076 {0x55555555, 0xfafafafa},
5077 {0x66555555, 0xfafafafa},
5078 {0x66555555, 0x5a5a5a5a},
5079 {0x66555555, 0x6a5a5a5a}, /* case-110 */
5080 {0x66555555, 0xaaaaaaaa},
5081 {0xffff55ff, 0xfafafafa},
5082 {0xffff55ff, 0x5afa5afa},
5083 {0xffff55ff, 0xaaaaaaaa},
5084 {0xffff55ff, 0xffff55ff}, /* case-115 */
5085 {0xaaffffaa, 0x5afa5afa},
5086 {0xaaffffaa, 0xaaaaaaaa},
5087 {0xffffffff, 0xfafafafa},
5088 {0xffffffff, 0x5afa5afa},
5089 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
5090 {0x55ff55ff, 0x5afa5afa},
5091 {0x55ff55ff, 0xaaaaaaaa},
5092 {0x55ff55ff, 0x55ff55ff}
5097 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
5098 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
5099 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5100 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5101 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5102 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
5103 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5104 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5105 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5106 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5107 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
5108 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5109 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5110 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5111 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5112 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
5113 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5114 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5115 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5116 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5117 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
5118 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
5119 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
5120 { {0x55, 0x08, 0x03, 0x10, 0x54} },
5121 { {0x65, 0x10, 0x03, 0x11, 0x10} },
5122 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
5123 { {0x51, 0x08, 0x03, 0x10, 0x50} },
5124 { {0x61, 0x08, 0x03, 0x11, 0x11} }
5129 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
5130 { {0x61, 0x45, 0x03, 0x11, 0x11} },
5131 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5132 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5133 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5134 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
5135 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5136 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5137 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5138 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5139 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
5140 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5141 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5142 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5143 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5144 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
5145 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5146 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5147 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5148 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5149 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
5150 { {0x51, 0x08, 0x03, 0x10, 0x50} }
5156 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
5160 {0, 0, false, 7}, /* for normal */
5161 {0, 16, false, 7}, /* for WL-CPT */
5166 {0, 21, true, 4} /* for gamg hid */
5170 {0, 0, false, 7}, /* for normal */
5171 {0, 16, false, 7}, /* for WL-CPT */
5175 {0, 28, true, 5},
5176 {0, 28, true, 5} /* for gamg hid */
5183 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5186 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5189 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5196 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5199 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5202 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5209 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5212 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5215 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5222 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5225 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5228 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5234 0, 1, 2, 3, 4, 4, 5, 6, 7, 8,
5240 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5246 0, 1, 2, 2, 3, 4, 4, 5, 6, 6,
5252 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5258 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5264 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5270 0, 1, 2, 3, 3, 4, 5, 6, 6, 7,
5276 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5306 {.addr = 0x84c, .mask = MASKBYTE2}, .offset = 0x80
5309 {.addr = 0x84c, .mask = MASKBYTE3}, .offset = 0x80
5326 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8},
5327 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8},
5328 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8},
5329 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32},
5330 {0, 0, RTW_REG_DOMAIN_NL},
5331 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5332 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5333 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5334 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5335 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
5336 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5337 {0, 0, RTW_REG_DOMAIN_NL},
5338 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
5339 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
5340 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
5341 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
5342 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
5343 {0, 0, RTW_REG_DOMAIN_NL},
5344 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5345 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5346 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
5347 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5368 .max_power_index = 0x7f,
5372 .dig_min = 0x20,
5379 .sys_func_en = 0xD8,
5388 .rf_base_addr = {0x3c00, 0x4c00},
5389 .rf_sipi_addr = {0x1808, 0x4108},
5418 .coex_para_ver = 0x22020720,
5419 .bt_desired_ver = 0x20,
5441 .bt_afh_span_bw20 = 0x24,
5442 .bt_afh_span_bw40 = 0x36,
5449 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},