Lines Matching +full:0 +full:x261
55 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8822b_read_efuse()
56 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8822b_read_efuse()
58 efuse->country_code[0] = map->country_code[0]; in rtw8822b_read_efuse()
61 efuse->regd = map->rf_board_option & 0x7; in rtw8822b_read_efuse()
65 for (i = 0; i < 4; i++) in rtw8822b_read_efuse()
83 return 0; in rtw8822b_read_efuse()
89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); in rtw8822b_phy_rfe_init()
90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); in rtw8822b_phy_rfe_init()
91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); in rtw8822b_phy_rfe_init()
94 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); in rtw8822b_phy_rfe_init()
95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
98 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); in rtw8822b_phy_rfe_init()
99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
104 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
105 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
106 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
107 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
112 u8 i = 0; in rtw8822b_get_swing_index()
115 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); in rtw8822b_get_swing_index()
116 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { in rtw8822b_get_swing_index()
138 dm_info->delta_power_index[path] = 0; in rtw8822b_pwrtrack_init()
149 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8822b_phy_bf_init()
170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8822b_phy_set_param()
171 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); in rtw8822b_phy_set_param()
172 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); in rtw8822b_phy_set_param()
188 #define WLAN_SLOT_TIME 0x09
189 #define WLAN_PIFS_TIME 0x19
190 #define WLAN_SIFS_CCK_CONT_TX 0xA
191 #define WLAN_SIFS_OFDM_CONT_TX 0xE
192 #define WLAN_SIFS_CCK_TRX 0x10
193 #define WLAN_SIFS_OFDM_TRX 0x10
194 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
195 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
196 #define WLAN_RDG_NAV 0x05
197 #define WLAN_TXOP_NAV 0x1B
198 #define WLAN_CCK_RX_TSF 0x30
199 #define WLAN_OFDM_RX_TSF 0x30
200 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
201 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
202 #define WLAN_DRV_EARLY_INT 0x04
203 #define WLAN_BCN_DMA_TIME 0x02
205 #define WLAN_RX_FILTER0 0x0FFFFFFF
206 #define WLAN_RX_FILTER2 0xFFFF
207 #define WLAN_RCR_CFG 0xE400220E
211 #define WLAN_AMPDU_MAX_TIME 0x70
212 #define WLAN_RTS_LEN_TH 0xFF
213 #define WLAN_RTS_TX_TIME_TH 0x08
214 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
215 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
216 #define FAST_EDCA_VO_TH 0x06
217 #define FAST_EDCA_VI_TH 0x06
218 #define FAST_EDCA_BE_TH 0x06
219 #define FAST_EDCA_BK_TH 0x06
220 #define WLAN_BAR_RETRY_LIMIT 0x01
221 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
223 #define WLAN_TX_FUNC_CFG1 0x30
224 #define WLAN_TX_FUNC_CFG2 0x30
225 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
226 #define WLAN_MAC_OPT_LB_FUNC1 0x80
227 #define WLAN_MAC_OPT_FUNC2 0xb0810041
260 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); in rtw8822b_mac_init()
287 return 0; in rtw8822b_mac_init()
295 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); in rtw8822b_set_channel_rfe_efem()
296 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_efem()
297 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); in rtw8822b_set_channel_rfe_efem()
299 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); in rtw8822b_set_channel_rfe_efem()
300 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_efem()
301 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); in rtw8822b_set_channel_rfe_efem()
304 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_efem()
309 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_efem()
312 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_efem()
315 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_efem()
325 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); in rtw8822b_set_channel_rfe_ifem()
326 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_ifem()
329 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); in rtw8822b_set_channel_rfe_ifem()
330 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_ifem()
333 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_ifem()
339 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_ifem()
342 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_ifem()
345 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_ifem()
348 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); in rtw8822b_set_channel_rfe_ifem()
367 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
368 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
369 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
373 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
374 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
375 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
379 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
380 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
381 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
476 reg830 = 0x79a0ea28; in rtw8822b_set_channel_cca()
484 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); in rtw8822b_set_channel_cca()
487 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); in rtw8822b_set_channel_cca()
490 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
491 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
492 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
493 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
494 0x6, 0x5, 0x0, 0x0, 0x7};
495 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
496 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
501 #define RF18_BAND_2G (0) in rtw8822b_set_channel_rf()
516 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822b_set_channel_rf()
544 rf_reg_be = 0x0; in rtw8822b_set_channel_rf()
556 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ in rtw8822b_set_channel_rf()
558 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); in rtw8822b_set_channel_rf()
560 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); in rtw8822b_set_channel_rf()
562 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
564 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
566 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8822b_set_channel_rf()
580 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); in rtw8822b_toggle_igi()
581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); in rtw8822b_toggle_igi()
582 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); in rtw8822b_toggle_igi()
583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); in rtw8822b_toggle_igi()
584 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); in rtw8822b_toggle_igi()
586 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); in rtw8822b_toggle_igi()
595 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
596 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); in rtw8822b_set_channel_rxdfir()
597 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
600 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
601 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
602 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
605 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
606 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
607 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8822b_set_channel_rxdfir()
619 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8822b_set_channel_bb()
620 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8822b_set_channel_bb()
621 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8822b_set_channel_bb()
622 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8822b_set_channel_bb()
624 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); in rtw8822b_set_channel_bb()
625 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8822b_set_channel_bb()
627 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); in rtw8822b_set_channel_bb()
628 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8822b_set_channel_bb()
630 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); in rtw8822b_set_channel_bb()
631 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); in rtw8822b_set_channel_bb()
634 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); in rtw8822b_set_channel_bb()
636 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8822b_set_channel_bb()
637 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8822b_set_channel_bb()
638 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8822b_set_channel_bb()
639 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); in rtw8822b_set_channel_bb()
642 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); in rtw8822b_set_channel_bb()
644 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); in rtw8822b_set_channel_bb()
646 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); in rtw8822b_set_channel_bb()
649 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8822b_set_channel_bb()
651 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8822b_set_channel_bb()
653 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8822b_set_channel_bb()
655 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8822b_set_channel_bb()
657 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); in rtw8822b_set_channel_bb()
664 val32 &= 0xFFCFFC00; in rtw8822b_set_channel_bb()
668 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
677 val32 &= 0xFF3FF300; in rtw8822b_set_channel_bb()
678 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); in rtw8822b_set_channel_bb()
681 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
685 val32 &= 0xFCEFCF00; in rtw8822b_set_channel_bb()
686 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); in rtw8822b_set_channel_bb()
689 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
692 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); in rtw8822b_set_channel_bb()
693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); in rtw8822b_set_channel_bb()
698 val32 &= 0xEFEEFE00; in rtw8822b_set_channel_bb()
702 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
703 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
707 val32 &= 0xEFFEFF00; in rtw8822b_set_channel_bb()
711 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
712 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
754 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
756 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
759 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
761 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
763 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); in rtw8822b_config_trx_mode()
764 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); in rtw8822b_config_trx_mode()
765 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); in rtw8822b_config_trx_mode()
768 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); in rtw8822b_config_trx_mode()
769 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); in rtw8822b_config_trx_mode()
771 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); in rtw8822b_config_trx_mode()
772 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); in rtw8822b_config_trx_mode()
776 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); in rtw8822b_config_trx_mode()
778 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); in rtw8822b_config_trx_mode()
785 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); in rtw8822b_config_trx_mode()
786 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); in rtw8822b_config_trx_mode()
790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); in rtw8822b_config_trx_mode()
791 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); in rtw8822b_config_trx_mode()
794 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); in rtw8822b_config_trx_mode()
796 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); in rtw8822b_config_trx_mode()
802 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); in rtw8822b_config_trx_mode()
803 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); in rtw8822b_config_trx_mode()
804 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); in rtw8822b_config_trx_mode()
806 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); in rtw8822b_config_trx_mode()
807 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); in rtw8822b_config_trx_mode()
808 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); in rtw8822b_config_trx_mode()
811 for (counter = 100; counter > 0; counter--) { in rtw8822b_config_trx_mode()
814 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
815 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
818 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); in rtw8822b_config_trx_mode()
820 if (rf_reg33 == 0x00001) in rtw8822b_config_trx_mode()
824 if (WARN(counter <= 0, "write RF mode table fail\n")) in rtw8822b_config_trx_mode()
827 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
828 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
829 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); in rtw8822b_config_trx_mode()
830 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); in rtw8822b_config_trx_mode()
831 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
832 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
862 u8 evm_dbm = 0; in query_phy_status_page1()
899 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page1()
907 if (rx_evm < 0) { in query_phy_status_page1()
909 evm_dbm = 0; in query_phy_status_page1()
922 page = *phy_status & 0xf; in query_phy_status()
925 case 0: in query_phy_status()
945 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8822b_query_rx_desc()
982 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8822b_set_tx_power_index_by_rate()
987 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8822b_set_tx_power_index_by_rate()
990 shift = rate & 0x3; in rtw8822b_set_tx_power_index_by_rate()
992 if (shift == 0x3) { in rtw8822b_set_tx_power_index_by_rate()
993 rate_idx = rate & 0xfc; in rtw8822b_set_tx_power_index_by_rate()
996 phy_pwr_idx = 0; in rtw8822b_set_tx_power_index_by_rate()
1006 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822b_set_tx_power_index()
1007 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) in rtw8822b_set_tx_power_index()
1030 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", in rtw8822b_set_antenna()
1034 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); in rtw8822b_set_antenna()
1039 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); in rtw8822b_set_antenna()
1048 return 0; in rtw8822b_set_antenna()
1069 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); in rtw8822b_false_alarm_statistics()
1070 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); in rtw8822b_false_alarm_statistics()
1071 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); in rtw8822b_false_alarm_statistics()
1076 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; in rtw8822b_false_alarm_statistics()
1078 crc32_cnt = rtw_read32(rtwdev, 0xf04); in rtw8822b_false_alarm_statistics()
1079 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1080 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1081 crc32_cnt = rtw_read32(rtwdev, 0xf14); in rtw8822b_false_alarm_statistics()
1082 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1083 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1084 crc32_cnt = rtw_read32(rtwdev, 0xf10); in rtw8822b_false_alarm_statistics()
1085 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1086 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1087 crc32_cnt = rtw_read32(rtwdev, 0xf0c); in rtw8822b_false_alarm_statistics()
1088 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1089 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1091 cca32_cnt = rtw_read32(rtwdev, 0xf08); in rtw8822b_false_alarm_statistics()
1092 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); in rtw8822b_false_alarm_statistics()
1095 cca32_cnt = rtw_read32(rtwdev, 0xfcc); in rtw8822b_false_alarm_statistics()
1096 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1100 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1101 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1102 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1103 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1104 rtw_write32_set(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1105 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1111 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8822b_do_iqk()
1118 for (counter = 0; counter < 300; counter++) { in rtw8822b_do_iqk()
1120 if (rf_reg == 0xabcde) in rtw8822b_do_iqk()
1124 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8822b_do_iqk()
1127 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8822b_do_iqk()
1129 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8822b_do_iqk()
1144 /* 0x790[5:0]=0x5 */ in rtw8822b_coex_cfg_init()
1145 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8822b_coex_cfg_init()
1148 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8822b_coex_cfg_init()
1169 u8 regval = 0; in rtw8822b_coex_cfg_ant_switch()
1185 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1186 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1187 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1188 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1190 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); in rtw8822b_coex_cfg_ant_switch()
1193 if (coex_rfe->rfe_module_type != 0x4 && in rtw8822b_coex_cfg_ant_switch()
1194 coex_rfe->rfe_module_type != 0x2) in rtw8822b_coex_cfg_ant_switch()
1195 regval = 0x3; in rtw8822b_coex_cfg_ant_switch()
1197 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1199 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1201 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8822b_coex_cfg_ant_switch()
1207 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1208 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1209 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1210 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1212 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); in rtw8822b_coex_cfg_ant_switch()
1214 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1218 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1219 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1220 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1221 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1222 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); in rtw8822b_coex_cfg_ant_switch()
1225 /* 0x4c[23] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1226 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); in rtw8822b_coex_cfg_ant_switch()
1228 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1232 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1233 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1234 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1235 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1238 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1239 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1240 /* 0x4c[24] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1241 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); in rtw8822b_coex_cfg_ant_switch()
1252 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1253 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1254 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1255 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822b_coex_cfg_gnt_debug()
1256 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1267 coex_rfe->ant_switch_polarity = 0; in rtw8822b_coex_cfg_rfe_type()
1269 if (coex_rfe->rfe_module_type == 0x12 || in rtw8822b_coex_cfg_rfe_type()
1270 coex_rfe->rfe_module_type == 0x15 || in rtw8822b_coex_cfg_rfe_type()
1271 coex_rfe->rfe_module_type == 0x16) in rtw8822b_coex_cfg_rfe_type()
1293 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); in rtw8822b_coex_cfg_rfe_type()
1294 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); in rtw8822b_coex_cfg_rfe_type()
1295 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); in rtw8822b_coex_cfg_rfe_type()
1298 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); in rtw8822b_coex_cfg_rfe_type()
1301 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1304 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1311 static const u16 reg_addr[] = {0xc58, 0xe58}; in rtw8822b_coex_cfg_wl_tx_power()
1312 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; in rtw8822b_coex_cfg_wl_tx_power()
1325 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) in rtw8822b_coex_cfg_wl_tx_power()
1326 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); in rtw8822b_coex_cfg_wl_tx_power()
1335 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, in rtw8822b_coex_cfg_wl_rx_gain()
1336 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1337 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, in rtw8822b_coex_cfg_wl_rx_gain()
1338 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1339 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, in rtw8822b_coex_cfg_wl_rx_gain()
1340 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, in rtw8822b_coex_cfg_wl_rx_gain()
1341 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1342 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, in rtw8822b_coex_cfg_wl_rx_gain()
1343 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1348 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1349 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1350 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, in rtw8822b_coex_cfg_wl_rx_gain()
1351 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1352 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, in rtw8822b_coex_cfg_wl_rx_gain()
1353 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, in rtw8822b_coex_cfg_wl_rx_gain()
1354 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1355 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, in rtw8822b_coex_cfg_wl_rx_gain()
1356 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1367 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1371 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1372 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1373 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1374 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1377 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1378 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); in rtw8822b_coex_cfg_wl_rx_gain()
1381 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1382 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1383 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1384 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1395 u8 swing_lower_bound = 0; in rtw8822b_txagc_swing_offset()
1396 u8 max_tx_pwr_idx_offset = 0xf; in rtw8822b_txagc_swing_offset()
1397 s8 agc_index = 0; in rtw8822b_txagc_swing_offset()
1402 if (delta_pwr_idx >= 0) { in rtw8822b_txagc_swing_offset()
1420 agc_index = 0; in rtw8822b_txagc_swing_offset()
1439 reg1 = 0xc94; in rtw8822b_pwrtrack_set_pwr()
1440 reg2 = 0xc1c; in rtw8822b_pwrtrack_set_pwr()
1442 reg1 = 0xe94; in rtw8822b_pwrtrack_set_pwr()
1443 reg2 = 0xe1c; in rtw8822b_pwrtrack_set_pwr()
1506 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) in rtw8822b_phy_pwrtrack()
1509 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8822b_phy_pwrtrack()
1519 for (path = 0; path < rtwdev->hal.rf_path_num; path++) in rtw8822b_phy_pwrtrack()
1532 if (efuse->power_track_type != 0) in rtw8822b_pwr_track()
1537 GENMASK(17, 16), 0x03); in rtw8822b_pwr_track()
1586 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0); in rtw8822b_adaptivity_init()
1598 igi = dm_info->igi_history[0]; in rtw8822b_adaptivity()
1620 {0x0086,
1624 RTW_PWR_CMD_WRITE, BIT(0), 0},
1625 {0x0086,
1630 {0x004A,
1634 RTW_PWR_CMD_WRITE, BIT(0), 0},
1635 {0x0005,
1639 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1640 {0x0300,
1644 RTW_PWR_CMD_WRITE, 0xFF, 0},
1645 {0x0301,
1649 RTW_PWR_CMD_WRITE, 0xFF, 0},
1650 {0xFFFF,
1653 0,
1654 RTW_PWR_CMD_END, 0, 0},
1658 {0x0012,
1662 RTW_PWR_CMD_WRITE, BIT(1), 0},
1663 {0x0012,
1667 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1668 {0x0020,
1672 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1673 {0x0001,
1678 {0x0000,
1682 RTW_PWR_CMD_WRITE, BIT(5), 0},
1683 {0x0005,
1687 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1688 {0x0075,
1692 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1693 {0x0006,
1698 {0x0075,
1702 RTW_PWR_CMD_WRITE, BIT(0), 0},
1703 {0xFF1A,
1707 RTW_PWR_CMD_WRITE, 0xFF, 0},
1708 {0x0006,
1712 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1713 {0x0005,
1717 RTW_PWR_CMD_WRITE, BIT(7), 0},
1718 {0x0005,
1722 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1723 {0x10C3,
1727 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1728 {0x0005,
1732 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1733 {0x0005,
1737 RTW_PWR_CMD_POLLING, BIT(0), 0},
1738 {0x0020,
1743 {0x10A8,
1747 RTW_PWR_CMD_WRITE, 0xFF, 0},
1748 {0x10A9,
1752 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1753 {0x10AA,
1757 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1758 {0x0068,
1763 {0x0029,
1767 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1768 {0x0024,
1772 RTW_PWR_CMD_WRITE, BIT(2), 0},
1773 {0x0074,
1778 {0x00AF,
1783 {0xFFFF,
1786 0,
1787 RTW_PWR_CMD_END, 0, 0},
1791 {0x0003,
1795 RTW_PWR_CMD_WRITE, BIT(2), 0},
1796 {0x0093,
1800 RTW_PWR_CMD_WRITE, BIT(3), 0},
1801 {0x001F,
1805 RTW_PWR_CMD_WRITE, 0xFF, 0},
1806 {0x00EF,
1810 RTW_PWR_CMD_WRITE, 0xFF, 0},
1811 {0xFF1A,
1815 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1816 {0x0049,
1820 RTW_PWR_CMD_WRITE, BIT(1), 0},
1821 {0x0006,
1825 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1826 {0x0002,
1830 RTW_PWR_CMD_WRITE, BIT(1), 0},
1831 {0x10C3,
1835 RTW_PWR_CMD_WRITE, BIT(0), 0},
1836 {0x0005,
1841 {0x0005,
1845 RTW_PWR_CMD_POLLING, BIT(1), 0},
1846 {0x0020,
1850 RTW_PWR_CMD_WRITE, BIT(3), 0},
1851 {0x0000,
1856 {0xFFFF,
1859 0,
1860 RTW_PWR_CMD_END, 0, 0},
1864 {0x0005,
1869 {0x0007,
1873 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1874 {0x0067,
1878 RTW_PWR_CMD_WRITE, BIT(5), 0},
1879 {0x0005,
1884 {0x004A,
1888 RTW_PWR_CMD_WRITE, BIT(0), 0},
1889 {0x0067,
1893 RTW_PWR_CMD_WRITE, BIT(5), 0},
1894 {0x0067,
1898 RTW_PWR_CMD_WRITE, BIT(4), 0},
1899 {0x004F,
1903 RTW_PWR_CMD_WRITE, BIT(0), 0},
1904 {0x0067,
1908 RTW_PWR_CMD_WRITE, BIT(1), 0},
1909 {0x0046,
1914 {0x0067,
1918 RTW_PWR_CMD_WRITE, BIT(2), 0},
1919 {0x0046,
1924 {0x0062,
1929 {0x0081,
1933 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1934 {0x0005,
1939 {0x0086,
1943 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1944 {0x0086,
1948 RTW_PWR_CMD_POLLING, BIT(1), 0},
1949 {0x0090,
1953 RTW_PWR_CMD_WRITE, BIT(1), 0},
1954 {0x0044,
1958 RTW_PWR_CMD_WRITE, 0xFF, 0},
1959 {0x0040,
1963 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1964 {0x0041,
1968 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1969 {0x0042,
1973 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1974 {0xFFFF,
1977 0,
1978 RTW_PWR_CMD_END, 0, 0},
1994 {0xFFFF, 0x00,
2001 {0x0001, 0xA841,
2005 {0xFFFF, 0x0000,
2012 {0x0001, 0xA841,
2016 {0x0002, 0x60C6,
2020 {0x0008, 0x3596,
2024 {0x0009, 0x321C,
2028 {0x000A, 0x9623,
2032 {0x0020, 0x94FF,
2036 {0x0021, 0xFFCF,
2040 {0x0026, 0xC006,
2044 {0x0029, 0xFF0E,
2048 {0x002A, 0x1840,
2052 {0xFFFF, 0x0000,
2059 {0x0001, 0xA841,
2063 {0x0002, 0x60C6,
2067 {0x0008, 0x3597,
2071 {0x0009, 0x321C,
2075 {0x000A, 0x9623,
2079 {0x0020, 0x94FF,
2083 {0x0021, 0xFFCF,
2087 {0x0026, 0xC006,
2091 {0x0029, 0xFF0E,
2095 {0x002A, 0x3040,
2099 {0xFFFF, 0x0000,
2118 [3] = RTW_DEF_RFE(8822b, 3, 0),
2123 [0] = { .addr = 0xc50, .mask = 0x7f },
2124 [1] = { .addr = 0xe50, .mask = 0x7f },
2136 {64, 64, 0, 0, 1},
2137 {64, 64, 64, 0, 1},
2207 {0xffffffff, 0xffffffff}, /* case-0 */
2208 {0x55555555, 0x55555555},
2209 {0x66555555, 0x66555555},
2210 {0xaaaaaaaa, 0xaaaaaaaa},
2211 {0x5a5a5a5a, 0x5a5a5a5a},
2212 {0xfafafafa, 0xfafafafa}, /* case-5 */
2213 {0x6a5a5555, 0xaaaaaaaa},
2214 {0x6a5a56aa, 0x6a5a56aa},
2215 {0x6a5a5a5a, 0x6a5a5a5a},
2216 {0x66555555, 0x5a5a5a5a},
2217 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2218 {0x66555555, 0xfafafafa},
2219 {0x66555555, 0x5a5a5aaa},
2220 {0x66555555, 0x6aaa5aaa},
2221 {0x66555555, 0xaaaa5aaa},
2222 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2223 {0xffff55ff, 0xfafafafa},
2224 {0xffff55ff, 0x6afa5afa},
2225 {0xaaffffaa, 0xfafafafa},
2226 {0xaa5555aa, 0x5a5a5a5a},
2227 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2228 {0xaa5555aa, 0xaaaaaaaa},
2229 {0xffffffff, 0x5a5a5a5a},
2230 {0xffffffff, 0x5a5a5a5a},
2231 {0xffffffff, 0x55555555},
2232 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2233 {0x55555555, 0x5a5a5a5a},
2234 {0x55555555, 0xaaaaaaaa},
2235 {0x55555555, 0x6a5a6a5a},
2236 {0x66556655, 0x66556655},
2237 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2238 {0xffffffff, 0x5aaa5aaa},
2239 {0x56555555, 0x5a5a5aaa},
2244 {0xffffffff, 0xffffffff}, /* case-100 */
2245 {0x55555555, 0x55555555},
2246 {0x66555555, 0x66555555},
2247 {0xaaaaaaaa, 0xaaaaaaaa},
2248 {0x5a5a5a5a, 0x5a5a5a5a},
2249 {0xfafafafa, 0xfafafafa}, /* case-105 */
2250 {0x5afa5afa, 0x5afa5afa},
2251 {0x55555555, 0xfafafafa},
2252 {0x66555555, 0xfafafafa},
2253 {0x66555555, 0x5a5a5a5a},
2254 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2255 {0x66555555, 0xaaaaaaaa},
2256 {0xffff55ff, 0xfafafafa},
2257 {0xffff55ff, 0x5afa5afa},
2258 {0xffff55ff, 0xaaaaaaaa},
2259 {0xffff55ff, 0xffff55ff}, /* case-115 */
2260 {0xaaffffaa, 0x5afa5afa},
2261 {0xaaffffaa, 0xaaaaaaaa},
2262 {0xffffffff, 0xfafafafa},
2263 {0xffffffff, 0x5afa5afa},
2264 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2265 {0x55ff55ff, 0x5afa5afa},
2266 {0x55ff55ff, 0xaaaaaaaa},
2267 {0x55ff55ff, 0x55ff55ff}
2272 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2273 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2274 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2275 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2276 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2277 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2278 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2279 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2280 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2281 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2282 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2283 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2284 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2285 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2286 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2287 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2288 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2289 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2290 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2291 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2292 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2293 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2294 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2295 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2296 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2297 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2298 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2299 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2304 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2305 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2306 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2307 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2308 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2309 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2310 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2311 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2312 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2313 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2314 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2315 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2316 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2317 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2318 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2319 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2320 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2321 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2322 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2323 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2324 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2325 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2334 {0, 0, false, 7}, /* for normal */
2335 {0, 16, false, 7}, /* for WL-CPT */
2336 {4, 0, true, 1},
2343 {0, 0, false, 7}, /* for normal */
2344 {0, 16, false, 7}, /* for WL-CPT */
2345 {4, 0, true, 1},
2376 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2379 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2382 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2389 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2392 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2395 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2402 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2405 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2408 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2415 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2418 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2421 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2427 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2433 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2439 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2445 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2451 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2457 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2463 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2469 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2498 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2499 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2500 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2501 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2502 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2503 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2504 {0, 0, RTW_REG_DOMAIN_NL},
2505 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2506 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2507 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2508 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2509 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2510 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2511 {0, 0, RTW_REG_DOMAIN_NL},
2512 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2513 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2514 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2515 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2516 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
2517 {0, 0, RTW_REG_DOMAIN_NL},
2518 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2519 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2520 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2521 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2525 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0},
2526 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0},
2547 .max_power_index = 0x3f,
2548 .csi_buf_pg_num = 0,
2551 .dig_min = 0x1c,
2556 .sys_func_en = 0xDC,
2565 .rf_base_addr = {0x2800, 0x2c00},
2566 .rf_sipi_addr = {0xc90, 0xe90},
2585 .coex_para_ver = 0x20070206,
2586 .bt_desired_ver = 0x6,
2608 .bt_afh_span_bw20 = 0x24,
2609 .bt_afh_span_bw40 = 0x36,
2616 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},