Lines Matching +full:12 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8821cu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8821cs_efuse_parsing()
50 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_read_efuse()
51 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
57 efuse->rfe_option = map->rfe_option & 0x1f; in rtw8821c_read_efuse()
58 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
59 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
60 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
61 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
62 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
63 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
64 efuse->channel_plan = map->channel_plan; in rtw8821c_read_efuse()
65 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
66 efuse->country_code[1] = map->country_code[1]; in rtw8821c_read_efuse()
67 efuse->bt_setting = map->rf_bt_setting; in rtw8821c_read_efuse()
68 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
69 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
70 efuse->thermal_meter_k = map->thermal_meter; in rtw8821c_read_efuse()
71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; in rtw8821c_read_efuse()
72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; in rtw8821c_read_efuse()
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
76 switch (efuse->rfe_option) { in rtw8821c_read_efuse()
83 hal->rfe_btg = true; in rtw8821c_read_efuse()
88 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; in rtw8821c_read_efuse()
90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) in rtw8821c_read_efuse()
91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; in rtw8821c_read_efuse()
105 return -ENOTSUPP; in rtw8821c_read_efuse()
135 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_init()
139 dm_info->default_ofdm_index = 24; in rtw8821c_pwrtrack_init()
141 dm_info->default_ofdm_index = swing_idx; in rtw8821c_pwrtrack_init()
143 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); in rtw8821c_pwrtrack_init()
144 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
145 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
146 dm_info->pwr_trk_triggered = false; in rtw8821c_pwrtrack_init()
147 dm_info->pwr_trk_init_trigger = true; in rtw8821c_pwrtrack_init()
148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8821c_pwrtrack_init()
160 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_phy_set_param()
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); in rtw8821c_phy_set_param()
197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); in rtw8821c_phy_set_param()
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
241 /* Set beacon cotnrol - enable TSF and other related functions */ in rtw8821c_mac_init()
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
312 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_channel_rf()
344 if (hal->rfe_btg) in rtw8821c_set_channel_rf()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
386 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_cck_tx_filter_srrc()
424 hal->ch_param[0]); in rtw8821c_cck_tx_filter_srrc()
426 hal->ch_param[1] & MASKLWORD); in rtw8821c_cck_tx_filter_srrc()
428 hal->ch_param[2]); in rtw8821c_cck_tx_filter_srrc()
446 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_channel_bb()
450 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
451 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
452 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
470 hal->ch_param[0]); in rtw8821c_set_channel_bb()
472 hal->ch_param[1] & MASKLWORD); in rtw8821c_set_channel_bb()
474 hal->ch_param[2]); in rtw8821c_set_channel_bb()
477 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
478 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
479 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
508 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
512 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
514 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
522 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
531 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
539 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
540 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
548 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
549 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
556 struct rtw_efuse efuse = rtwdev->efuse; in rtw8821c_get_bb_swing()
588 struct rtw_efuse *efuse = &rtwdev->efuse; in get_cck_rx_pwr()
594 if (efuse->rfe_option == 0) { in get_cck_rx_pwr()
604 return -120; in get_cck_rx_pwr()
608 rx_pwr_all = lna_gain - 2 * vga_idx; in get_cck_rx_pwr()
616 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page0()
626 pkt_stat->rx_power[RF_PATH_A] = rx_power; in query_phy_status_page0()
627 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page0()
628 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page0()
629 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; in query_phy_status_page0()
630 pkt_stat->signal_power = rx_power; in query_phy_status_page0()
636 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page1()
638 s8 min_rx_power = -120; in query_phy_status_page1()
640 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) in query_phy_status_page1()
647 else if (rxsc >= 9 && rxsc <= 12) in query_phy_status_page1()
654 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; in query_phy_status_page1()
655 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page1()
656 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page1()
657 pkt_stat->bw = bw; in query_phy_status_page1()
658 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page1()
687 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; in rtw8821c_query_rx_desc()
692 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); in rtw8821c_query_rx_desc()
693 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); in rtw8821c_query_rx_desc()
694 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); in rtw8821c_query_rx_desc()
695 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && in rtw8821c_query_rx_desc()
697 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); in rtw8821c_query_rx_desc()
698 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); in rtw8821c_query_rx_desc()
699 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); in rtw8821c_query_rx_desc()
700 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); in rtw8821c_query_rx_desc()
701 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); in rtw8821c_query_rx_desc()
702 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); in rtw8821c_query_rx_desc()
703 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); in rtw8821c_query_rx_desc()
704 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); in rtw8821c_query_rx_desc()
706 /* drv_info_sz is in unit of 8-bytes */ in rtw8821c_query_rx_desc()
707 pkt_stat->drv_info_sz *= 8; in rtw8821c_query_rx_desc()
710 if (pkt_stat->is_c2h) in rtw8821c_query_rx_desc()
713 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + in rtw8821c_query_rx_desc()
714 pkt_stat->drv_info_sz); in rtw8821c_query_rx_desc()
715 if (pkt_stat->phy_status) { in rtw8821c_query_rx_desc()
716 phy_status = rx_desc + desc_sz + pkt_stat->shift; in rtw8821c_query_rx_desc()
726 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index_by_rate()
734 pwr_index = hal->tx_pwr_tbl[path][rate]; in rtw8821c_set_tx_power_index_by_rate()
748 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index()
751 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
763 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_false_alarm_statistics()
770 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
774 dm_info->cck_fa_cnt = cck_fa_cnt; in rtw8821c_false_alarm_statistics()
775 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
776 dm_info->total_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
778 dm_info->total_fa_cnt += cck_fa_cnt; in rtw8821c_false_alarm_statistics()
781 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
782 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
785 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
786 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
789 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
790 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
793 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
794 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
797 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); in rtw8821c_false_alarm_statistics()
798 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; in rtw8821c_false_alarm_statistics()
801 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
802 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; in rtw8821c_false_alarm_statistics()
805 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
806 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
807 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
808 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
809 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
810 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
834 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); in rtw8821c_do_iqk()
858 /* enable PTA (3-wire function form BT side) */ in rtw8821c_coex_cfg_init()
869 /* beacon queue always hi-pri */ in rtw8821c_coex_cfg_init()
877 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_ant_switch()
878 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_ant_switch()
879 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_ant_switch()
884 if (switch_status == coex_dm->cur_switch_status) in rtw8821c_coex_cfg_ant_switch()
887 if (coex_rfe->wlg_at_btg) { in rtw8821c_coex_cfg_ant_switch()
890 if (coex_rfe->ant_switch_polarity) in rtw8821c_coex_cfg_ant_switch()
896 coex_dm->cur_switch_status = switch_status; in rtw8821c_coex_cfg_ant_switch()
898 if (coex_rfe->ant_switch_diversity && in rtw8821c_coex_cfg_ant_switch()
902 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); in rtw8821c_coex_cfg_ant_switch()
914 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
915 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
986 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_rfe_type()
987 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_rfe_type()
988 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_rfe_type()
990 coex_rfe->rfe_module_type = efuse->rfe_option; in rtw8821c_coex_cfg_rfe_type()
991 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
992 coex_rfe->ant_switch_exist = true; in rtw8821c_coex_cfg_rfe_type()
993 coex_rfe->wlg_at_btg = false; in rtw8821c_coex_cfg_rfe_type()
995 switch (coex_rfe->rfe_module_type) { in rtw8821c_coex_cfg_rfe_type()
999 case 9: /* 1-Ant, Main, WLG */ in rtw8821c_coex_cfg_rfe_type()
1000 default: /* 2-Ant, DPDT, WLG */ in rtw8821c_coex_cfg_rfe_type()
1003 case 10: /* 1-Ant, Main, BTG */ in rtw8821c_coex_cfg_rfe_type()
1005 case 15: /* 2-Ant, DPDT, BTG */ in rtw8821c_coex_cfg_rfe_type()
1006 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
1009 case 11: /* 1-Ant, Aux, WLG */ in rtw8821c_coex_cfg_rfe_type()
1010 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
1013 case 12: /* 1-Ant, Aux, BTG */ in rtw8821c_coex_cfg_rfe_type()
1014 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
1015 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
1018 case 13: /* 2-Ant, no switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
1020 case 14: /* 2-Ant, no antenna switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
1021 coex_rfe->ant_switch_exist = false; in rtw8821c_coex_cfg_rfe_type()
1028 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_wl_tx_power()
1029 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_wl_tx_power()
1030 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_wl_tx_power()
1031 bool share_ant = efuse->share_ant; in rtw8821c_coex_cfg_wl_tx_power()
1036 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) in rtw8821c_coex_cfg_wl_tx_power()
1039 coex_dm->cur_wl_pwr_lvl = wl_pwr; in rtw8821c_coex_cfg_wl_tx_power()
1050 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_txagc_swing_offset()
1051 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_txagc_swing_offset()
1052 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; in rtw8821c_txagc_swing_offset()
1056 u8 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1059 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); in rtw8821c_txagc_swing_offset()
1064 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1067 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
1068 delta_pwr_idx - pwr_idx_offset; in rtw8821c_txagc_swing_offset()
1074 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1076 if (dm_info->default_ofdm_index > in rtw8821c_txagc_swing_offset()
1077 (pwr_idx_offset_lower - delta_pwr_idx)) in rtw8821c_txagc_swing_offset()
1078 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
1079 delta_pwr_idx - pwr_idx_offset_lower; in rtw8821c_txagc_swing_offset()
1089 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; in rtw8821c_txagc_swing_offset()
1111 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_set()
1114 u8 channel = rtwdev->hal.current_channel; in rtw8821c_pwrtrack_set()
1115 u8 band_width = rtwdev->hal.current_band_width; in rtw8821c_pwrtrack_set()
1117 u8 tx_rate = dm_info->tx_rate; in rtw8821c_pwrtrack_set()
1118 u8 max_pwr_idx = rtwdev->chip->max_power_index; in rtw8821c_pwrtrack_set()
1125 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1126 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1133 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_pwrtrack()
1139 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
1146 if (dm_info->pwr_trk_init_trigger) in rtw8821c_phy_pwrtrack()
1147 dm_info->pwr_trk_init_trigger = false; in rtw8821c_phy_pwrtrack()
1154 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw8821c_phy_pwrtrack()
1156 dm_info->delta_power_index[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1159 if (dm_info->delta_power_index[RF_PATH_A] == in rtw8821c_phy_pwrtrack()
1160 dm_info->delta_power_index_last[RF_PATH_A]) in rtw8821c_phy_pwrtrack()
1163 dm_info->delta_power_index_last[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1164 dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_phy_pwrtrack()
1174 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_pwr_track()
1175 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwr_track()
1177 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
1180 if (!dm_info->pwr_trk_triggered) { in rtw8821c_pwr_track()
1183 dm_info->pwr_trk_triggered = true; in rtw8821c_pwr_track()
1188 dm_info->pwr_trk_triggered = false; in rtw8821c_pwr_track()
1214 if (bfee->role == RTW_BFEE_SU) in rtw8821c_bf_config_bfee()
1216 else if (bfee->role == RTW_BFEE_MU) in rtw8821c_bf_config_bfee()
1224 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_cck_pd_set()
1228 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", in rtw8821c_phy_cck_pd_set()
1229 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); in rtw8821c_phy_cck_pd_set()
1231 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) in rtw8821c_phy_cck_pd_set()
1239 dm_info->cck_pd_default + new_lvl * 2, in rtw8821c_phy_cck_pd_set()
1240 pd[new_lvl], dm_info->cck_fa_avg); in rtw8821c_phy_cck_pd_set()
1242 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw8821c_phy_cck_pd_set()
1244 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; in rtw8821c_phy_cck_pd_set()
1247 dm_info->cck_pd_default + new_lvl * 2); in rtw8821c_phy_cck_pd_set()
1262 RTW_PWR_CMD_WRITE, BIT(0), 0},
1267 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1272 RTW_PWR_CMD_WRITE, BIT(0), 0},
1277 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1300 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1310 RTW_PWR_CMD_WRITE, BIT(5), 0},
1315 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1320 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1325 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1330 RTW_PWR_CMD_WRITE, BIT(0), 0},
1335 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1340 RTW_PWR_CMD_WRITE, BIT(7), 0},
1345 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1350 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1355 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1360 RTW_PWR_CMD_POLLING, BIT(0), 0},
1365 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1370 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1375 RTW_PWR_CMD_WRITE, BIT(1), 0},
1380 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1381 (BIT(7) | BIT(6) | BIT(5))},
1386 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1391 RTW_PWR_CMD_WRITE, BIT(1), 0},
1404 RTW_PWR_CMD_WRITE, BIT(3), 0},
1414 RTW_PWR_CMD_WRITE, BIT(1), 0},
1419 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1424 RTW_PWR_CMD_WRITE, BIT(1), 0},
1429 RTW_PWR_CMD_WRITE, BIT(0), 0},
1434 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1439 RTW_PWR_CMD_POLLING, BIT(1), 0},
1444 RTW_PWR_CMD_WRITE, BIT(3), 0},
1449 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1467 RTW_PWR_CMD_WRITE, BIT(5), 0},
1472 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1477 RTW_PWR_CMD_WRITE, BIT(0), 0},
1482 RTW_PWR_CMD_WRITE, BIT(5), 0},
1487 RTW_PWR_CMD_WRITE, BIT(4), 0},
1492 RTW_PWR_CMD_WRITE, BIT(0), 0},
1497 RTW_PWR_CMD_WRITE, BIT(1), 0},
1502 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1507 RTW_PWR_CMD_WRITE, BIT(2), 0},
1512 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1517 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1522 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1527 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1532 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1537 RTW_PWR_CMD_POLLING, BIT(1), 0},
1542 RTW_PWR_CMD_WRITE, BIT(1), 0},
1715 /* rssi in percentage % (dbm = % - 100) */
1719 /* Shared-Antenna Coex Table */
1721 {0x55555555, 0x55555555}, /* case-0 */
1726 {0xfafafafa, 0xfafafafa}, /* case-5 */
1731 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1736 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1741 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1746 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1751 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1756 /* Non-Shared-Antenna Coex Table */
1758 {0xffffffff, 0xffffffff}, /* case-100 */
1763 {0xffffffff, 0xffffffff}, /* case-105 */
1768 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1773 {0xffff55ff, 0xffff55ff}, /* case-115 */
1778 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1784 /* Shared-Antenna TDMA */
1786 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1787 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1791 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1796 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1801 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1806 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1811 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1816 /* Non-Shared-Antenna TDMA */
1818 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1823 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1828 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1833 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1838 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1847 {0, 20, false, 7}, /* for WL-CPT */
1856 {0, 20, false, 7}, /* for WL-CPT */
1867 11, 11, 12, 12, 12, 12, 12},
1869 11, 12, 12, 12, 12, 12, 12, 12},
1871 11, 12, 12, 12, 12, 12, 12},
1876 12, 12, 12, 12, 12, 12, 12},
1878 12, 12, 12, 12, 12, 12, 12, 12},
1880 11, 12, 12, 12, 12, 12, 12, 12},
1885 11, 11, 12, 12, 12, 12, 12},
1887 11, 12, 12, 12, 12, 12, 12, 12},
1889 11, 12, 12, 12, 12, 12, 12},
1894 12, 12, 12, 12, 12, 12, 12},
1896 12, 12, 12, 12, 12, 12, 12, 12},
1898 11, 12, 12, 12, 12, 12, 12, 12},
1973 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1976 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1977 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1978 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1979 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1984 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2014 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),