Lines Matching +full:0 +full:x20020000
57 efuse->rfe_option = map->rfe_option & 0x1f; in rtw8821c_read_efuse()
62 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
63 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
65 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
68 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
69 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
77 case 0x2: in rtw8821c_read_efuse()
78 case 0x4: in rtw8821c_read_efuse()
79 case 0x7: in rtw8821c_read_efuse()
80 case 0xa: in rtw8821c_read_efuse()
81 case 0xc: in rtw8821c_read_efuse()
82 case 0xf: in rtw8821c_read_efuse()
87 for (i = 0; i < 4; i++) in rtw8821c_read_efuse()
91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; in rtw8821c_read_efuse()
108 return 0; in rtw8821c_read_efuse()
112 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
113 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
114 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
115 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
120 u8 i = 0; in rtw8821c_get_swing_index()
123 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); in rtw8821c_get_swing_index()
124 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { in rtw8821c_get_swing_index()
144 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
145 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
155 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8821c_phy_bf_init()
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); in rtw8821c_phy_set_param()
190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); in rtw8821c_phy_set_param()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
216 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); in rtw8821c_mac_init()
232 rtw_write16(rtwdev, REG_TXPAUSE, 0); in rtw8821c_mac_init()
257 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); in rtw8821c_mac_init()
264 return 0; in rtw8821c_mac_init()
315 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8821c_set_channel_rf()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
349 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
355 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
389 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); in rtw8821c_cck_tx_filter_srrc()
390 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); in rtw8821c_cck_tx_filter_srrc()
391 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8821c_cck_tx_filter_srrc()
392 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); in rtw8821c_cck_tx_filter_srrc()
394 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); in rtw8821c_cck_tx_filter_srrc()
395 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); in rtw8821c_cck_tx_filter_srrc()
396 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
397 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); in rtw8821c_cck_tx_filter_srrc()
398 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
399 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); in rtw8821c_cck_tx_filter_srrc()
400 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
401 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); in rtw8821c_cck_tx_filter_srrc()
402 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
403 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
406 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe); in rtw8821c_cck_tx_filter_srrc()
407 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c); in rtw8821c_cck_tx_filter_srrc()
408 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810); in rtw8821c_cck_tx_filter_srrc()
409 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667); in rtw8821c_cck_tx_filter_srrc()
411 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); in rtw8821c_cck_tx_filter_srrc()
412 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); in rtw8821c_cck_tx_filter_srrc()
413 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); in rtw8821c_cck_tx_filter_srrc()
414 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); in rtw8821c_cck_tx_filter_srrc()
415 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); in rtw8821c_cck_tx_filter_srrc()
416 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); in rtw8821c_cck_tx_filter_srrc()
417 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029); in rtw8821c_cck_tx_filter_srrc()
418 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); in rtw8821c_cck_tx_filter_srrc()
419 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026); in rtw8821c_cck_tx_filter_srrc()
420 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
422 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); in rtw8821c_cck_tx_filter_srrc()
424 hal->ch_param[0]); in rtw8821c_cck_tx_filter_srrc()
430 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); in rtw8821c_cck_tx_filter_srrc()
431 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); in rtw8821c_cck_tx_filter_srrc()
432 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
433 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); in rtw8821c_cck_tx_filter_srrc()
434 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
435 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); in rtw8821c_cck_tx_filter_srrc()
436 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
437 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); in rtw8821c_cck_tx_filter_srrc()
438 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
439 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
450 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
451 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
452 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
453 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
455 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); in rtw8821c_set_channel_bb()
456 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8821c_set_channel_bb()
465 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); in rtw8821c_set_channel_bb()
466 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8821c_set_channel_bb()
467 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); in rtw8821c_set_channel_bb()
470 hal->ch_param[0]); in rtw8821c_set_channel_bb()
477 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
478 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
479 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
480 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
483 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); in rtw8821c_set_channel_bb()
485 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); in rtw8821c_set_channel_bb()
487 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); in rtw8821c_set_channel_bb()
490 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8821c_set_channel_bb()
492 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8821c_set_channel_bb()
494 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8821c_set_channel_bb()
496 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8821c_set_channel_bb()
504 val32 &= 0xffcffc00; in rtw8821c_set_channel_bb()
505 val32 |= 0x10010000; in rtw8821c_set_channel_bb()
508 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
517 val32 &= 0xff3ff300; in rtw8821c_set_channel_bb()
518 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
522 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
526 val32 &= 0xfcffcf00; in rtw8821c_set_channel_bb()
527 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
531 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
535 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
536 val32 |= 0x200240; in rtw8821c_set_channel_bb()
539 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
540 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
544 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
545 val32 |= 0x300380; in rtw8821c_set_channel_bb()
548 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
549 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
558 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; in rtw8821c_get_bb_swing()
563 tx_bb_swing = 0; in rtw8821c_get_bb_swing()
591 s8 rx_pwr_all = 0; in get_cck_rx_pwr()
592 s8 lna_gain = 0; in get_cck_rx_pwr()
594 if (efuse->rfe_option == 0) { in get_cck_rx_pwr()
618 u8 lna_idx = 0; in query_phy_status_page0()
619 u8 vga_idx = 0; in query_phy_status_page0()
667 page = *phy_status & 0xf; in query_phy_status()
670 case 0: in query_phy_status()
690 memset(pkt_stat, 0, sizeof(*pkt_stat)); in rtw8821c_query_rx_desc()
727 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8821c_set_tx_power_index_by_rate()
732 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8821c_set_tx_power_index_by_rate()
735 shift = rate & 0x3; in rtw8821c_set_tx_power_index_by_rate()
737 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { in rtw8821c_set_tx_power_index_by_rate()
738 rate_idx = rate & 0xfc; in rtw8821c_set_tx_power_index_by_rate()
741 phy_pwr_idx = 0; in rtw8821c_set_tx_power_index_by_rate()
751 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
752 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { in rtw8821c_set_tx_power_index()
781 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
785 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
789 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
793 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
801 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
809 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
810 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
816 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8821c_do_iqk()
826 for (counter = 0; counter < 300; counter++) { in rtw8821c_do_iqk()
828 if (rf_reg == 0xabcde) in rtw8821c_do_iqk()
832 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8821c_do_iqk()
835 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8821c_do_iqk()
837 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8821c_do_iqk()
853 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8821c_coex_cfg_init()
882 u8 regval = 0; in rtw8821c_coex_cfg_ant_switch()
914 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
915 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
916 regval = 0x3; in rtw8821c_coex_cfg_ant_switch()
918 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
920 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
922 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8821c_coex_cfg_ant_switch()
935 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
948 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8821c_coex_cfg_ant_switch()
991 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
996 case 0: in rtw8821c_coex_cfg_rfe_type()
1053 u8 swing_lower_bound = 0; in rtw8821c_txagc_swing_offset()
1054 u8 max_pwr_idx_offset = 0xf; in rtw8821c_txagc_swing_offset()
1055 s8 agc_index = 0; in rtw8821c_txagc_swing_offset()
1061 if (delta_pwr_idx >= 0) { in rtw8821c_txagc_swing_offset()
1071 } else if (delta_pwr_idx < 0) { in rtw8821c_txagc_swing_offset()
1126 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1139 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
1142 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8821c_phy_pwrtrack()
1177 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
1182 GENMASK(17, 16), 0x03); in rtw8821c_pwr_track()
1237 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", in rtw8821c_phy_cck_pd_set()
1245 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); in rtw8821c_phy_cck_pd_set()
1246 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, in rtw8821c_phy_cck_pd_set()
1258 {0x0086,
1262 RTW_PWR_CMD_WRITE, BIT(0), 0},
1263 {0x0086,
1268 {0x004A,
1272 RTW_PWR_CMD_WRITE, BIT(0), 0},
1273 {0x0005,
1277 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1278 {0x0300,
1282 RTW_PWR_CMD_WRITE, 0xFF, 0},
1283 {0x0301,
1287 RTW_PWR_CMD_WRITE, 0xFF, 0},
1288 {0xFFFF,
1291 0,
1292 RTW_PWR_CMD_END, 0, 0},
1296 {0x0020,
1300 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1301 {0x0001,
1306 {0x0000,
1310 RTW_PWR_CMD_WRITE, BIT(5), 0},
1311 {0x0005,
1315 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1316 {0x0075,
1320 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1321 {0x0006,
1326 {0x0075,
1330 RTW_PWR_CMD_WRITE, BIT(0), 0},
1331 {0x0006,
1335 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1336 {0x0005,
1340 RTW_PWR_CMD_WRITE, BIT(7), 0},
1341 {0x0005,
1345 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1346 {0x10C3,
1350 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1351 {0x0005,
1355 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1356 {0x0005,
1360 RTW_PWR_CMD_POLLING, BIT(0), 0},
1361 {0x0020,
1366 {0x0074,
1371 {0x0022,
1375 RTW_PWR_CMD_WRITE, BIT(1), 0},
1376 {0x0062,
1382 {0x0061,
1386 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1387 {0x007C,
1391 RTW_PWR_CMD_WRITE, BIT(1), 0},
1392 {0xFFFF,
1395 0,
1396 RTW_PWR_CMD_END, 0, 0},
1400 {0x0093,
1404 RTW_PWR_CMD_WRITE, BIT(3), 0},
1405 {0x001F,
1409 RTW_PWR_CMD_WRITE, 0xFF, 0},
1410 {0x0049,
1414 RTW_PWR_CMD_WRITE, BIT(1), 0},
1415 {0x0006,
1419 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1420 {0x0002,
1424 RTW_PWR_CMD_WRITE, BIT(1), 0},
1425 {0x10C3,
1429 RTW_PWR_CMD_WRITE, BIT(0), 0},
1430 {0x0005,
1435 {0x0005,
1439 RTW_PWR_CMD_POLLING, BIT(1), 0},
1440 {0x0020,
1444 RTW_PWR_CMD_WRITE, BIT(3), 0},
1445 {0x0000,
1450 {0xFFFF,
1453 0,
1454 RTW_PWR_CMD_END, 0, 0},
1458 {0x0007,
1462 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1463 {0x0067,
1467 RTW_PWR_CMD_WRITE, BIT(5), 0},
1468 {0x0005,
1473 {0x004A,
1477 RTW_PWR_CMD_WRITE, BIT(0), 0},
1478 {0x0067,
1482 RTW_PWR_CMD_WRITE, BIT(5), 0},
1483 {0x0067,
1487 RTW_PWR_CMD_WRITE, BIT(4), 0},
1488 {0x004F,
1492 RTW_PWR_CMD_WRITE, BIT(0), 0},
1493 {0x0067,
1497 RTW_PWR_CMD_WRITE, BIT(1), 0},
1498 {0x0046,
1503 {0x0067,
1507 RTW_PWR_CMD_WRITE, BIT(2), 0},
1508 {0x0046,
1513 {0x0062,
1518 {0x0081,
1522 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1523 {0x0005,
1528 {0x0086,
1532 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1533 {0x0086,
1537 RTW_PWR_CMD_POLLING, BIT(1), 0},
1538 {0x0090,
1542 RTW_PWR_CMD_WRITE, BIT(1), 0},
1543 {0x0044,
1547 RTW_PWR_CMD_WRITE, 0xFF, 0},
1548 {0x0040,
1552 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1553 {0x0041,
1557 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1558 {0x0042,
1562 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1563 {0xFFFF,
1566 0,
1567 RTW_PWR_CMD_END, 0, 0},
1583 {0xFFFF, 0x00,
1590 {0xFFFF, 0x0000,
1597 {0x0009, 0x6380,
1601 {0xFFFF, 0x0000,
1608 {0xFFFF, 0x0000,
1626 [0] = RTW_DEF_RFE(8821c, 0, 0),
1627 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1628 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1629 [6] = RTW_DEF_RFE(8821c, 0, 0),
1633 [0] = { .addr = 0xc50, .mask = 0x7f },
1643 /* not sure what [0] stands for */
1646 {16, 16, 0, 0, 1},
1647 {16, 16, 16, 0, 1},
1652 /* not sure what [0] stands for */
1721 {0x55555555, 0x55555555}, /* case-0 */
1722 {0x55555555, 0x55555555},
1723 {0x66555555, 0x66555555},
1724 {0xaaaaaaaa, 0xaaaaaaaa},
1725 {0x5a5a5a5a, 0x5a5a5a5a},
1726 {0xfafafafa, 0xfafafafa}, /* case-5 */
1727 {0x6a5a5555, 0xaaaaaaaa},
1728 {0x6a5a56aa, 0x6a5a56aa},
1729 {0x6a5a5a5a, 0x6a5a5a5a},
1730 {0x66555555, 0x5a5a5a5a},
1731 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1732 {0x66555555, 0xaaaaaaaa},
1733 {0x66555555, 0x6a5a5aaa},
1734 {0x66555555, 0x6aaa6aaa},
1735 {0x66555555, 0x6a5a5aaa},
1736 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1737 {0xffff55ff, 0xfafafafa},
1738 {0xffff55ff, 0x6afa5afa},
1739 {0xaaffffaa, 0xfafafafa},
1740 {0xaa5555aa, 0x5a5a5a5a},
1741 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1742 {0xaa5555aa, 0xaaaaaaaa},
1743 {0xffffffff, 0x55555555},
1744 {0xffffffff, 0x5a5a5a5a},
1745 {0xffffffff, 0x5a5a5a5a},
1746 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1747 {0x55555555, 0x5a5a5a5a},
1748 {0x55555555, 0xaaaaaaaa},
1749 {0x66555555, 0x6a5a6a5a},
1750 {0x66556655, 0x66556655},
1751 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1752 {0xffffffff, 0x5aaa5aaa},
1753 {0x56555555, 0x5a5a5aaa}
1758 {0xffffffff, 0xffffffff}, /* case-100 */
1759 {0xffff55ff, 0xfafafafa},
1760 {0x66555555, 0x66555555},
1761 {0xaaaaaaaa, 0xaaaaaaaa},
1762 {0x5a5a5a5a, 0x5a5a5a5a},
1763 {0xffffffff, 0xffffffff}, /* case-105 */
1764 {0x5afa5afa, 0x5afa5afa},
1765 {0x55555555, 0xfafafafa},
1766 {0x66555555, 0xfafafafa},
1767 {0x66555555, 0x5a5a5a5a},
1768 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1769 {0x66555555, 0xaaaaaaaa},
1770 {0xffff55ff, 0xfafafafa},
1771 {0xffff55ff, 0x5afa5afa},
1772 {0xffff55ff, 0xaaaaaaaa},
1773 {0xffff55ff, 0xffff55ff}, /* case-115 */
1774 {0xaaffffaa, 0x5afa5afa},
1775 {0xaaffffaa, 0xaaaaaaaa},
1776 {0xffffffff, 0xfafafafa},
1777 {0xffff55ff, 0xfafafafa},
1778 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1779 {0xffff55ff, 0x5afa5afa},
1780 {0xffff55ff, 0x5afa5afa},
1781 {0x55ff55ff, 0x55ff55ff}
1786 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1787 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1788 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1789 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1790 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1791 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1792 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1793 { {0x61, 0x35, 0x03, 0x11, 0x10} },
1794 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1795 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1796 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1797 { {0x61, 0x08, 0x03, 0x11, 0x15} },
1798 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1799 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1800 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1801 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1802 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1803 { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1804 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1805 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1806 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1807 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1808 { {0x51, 0x08, 0x03, 0x30, 0x54} },
1809 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1810 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1811 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1812 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1813 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1818 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1819 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1820 { {0x61, 0x25, 0x03, 0x11, 0x11} },
1821 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1822 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1823 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1824 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1825 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1826 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1827 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1828 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1829 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1830 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1831 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1832 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1833 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1834 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1835 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1836 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1837 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1838 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1839 { {0x51, 0x10, 0x03, 0x10, 0x50} }
1842 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1846 {0, 0, false, 7}, /* for normal */
1847 {0, 20, false, 7}, /* for WL-CPT */
1855 {0, 0, false, 7}, /* for normal */
1856 {0, 20, false, 7}, /* for WL-CPT */
1860 {0, 28, true, 5}
1866 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1868 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1870 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1875 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1877 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1879 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1884 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1886 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1888 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1893 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1895 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1897 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1902 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1907 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1912 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1917 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1922 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1927 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1932 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1937 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1942 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1945 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1948 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1951 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1965 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1966 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1967 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1968 {0, 0, RTW_REG_DOMAIN_NL},
1969 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1970 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1971 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1972 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1973 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1974 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1975 {0, 0, RTW_REG_DOMAIN_NL},
1976 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1977 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1978 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1979 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1980 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1981 {0, 0, RTW_REG_DOMAIN_NL},
1982 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1983 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1984 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1985 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1986 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2006 .max_power_index = 0x3f,
2007 .csi_buf_pg_num = 0,
2010 .dig_min = 0x1c,
2015 .sys_func_en = 0xD8,
2023 .rf_base_addr = {0x2800, 0x2c00},
2024 .rf_sipi_addr = {0xc90, 0xe90},
2040 .coex_para_ver = 0x19092746,
2041 .bt_desired_ver = 0x46,
2063 .bt_afh_span_bw20 = 0x24,
2064 .bt_afh_span_bw40 = 0x36,