17 #define WLAN_RL_VAL 0x3030
19 #define WLAN_BAR_VAL 0x0201ffff
20 #define WLAN_PIFS_VAL 0
21 #define WLAN_RX_PKT_LIMIT 0x18
22 #define WLAN_SLOT_TIME 0x09
23 #define WLAN_SPEC_SIFS 0x100a
24 #define WLAN_MAX_AGG_NR 0x1f
25 #define WLAN_AMPDU_MAX_TIME 0x70
28 #define TBTT_PROHIBIT_SETUP_TIME 0x04
29 #define TBTT_PROHIBIT_HOLD_TIME 0x80
30 #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64
36 	0xFFFF,				\
39 	0,				\
40 	RTW_PWR_CMD_END, 0, 0
48 static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} };
54 	{0, 0, false, 7},  /* for normal */
55 	{0, 10, false, 7}, /* for WL-CPT */
56 	{1, 0, true, 4},
63 	{0, 0, false, 7},  /* for normal */
64 	{0, 10, false, 7}, /* for WL-CPT */
65 	{1, 0, true, 5},
72 	0x0b40002d, /* 0,  -15.0dB */
73 	0x0c000030, /* 1,  -14.5dB */
74 	0x0cc00033, /* 2,  -14.0dB */
75 	0x0d800036, /* 3,  -13.5dB */
76 	0x0e400039, /* 4,  -13.0dB */
77 	0x0f00003c, /* 5,  -12.5dB */
78 	0x10000040, /* 6,  -12.0dB */
79 	0x11000044, /* 7,  -11.5dB */
80 	0x12000048, /* 8,  -11.0dB */
81 	0x1300004c, /* 9,  -10.5dB */
82 	0x14400051, /* 10, -10.0dB */
83 	0x15800056, /* 11, -9.5dB */
84 	0x16c0005b, /* 12, -9.0dB */
85 	0x18000060, /* 13, -8.5dB */
86 	0x19800066, /* 14, -8.0dB */
87 	0x1b00006c, /* 15, -7.5dB */
88 	0x1c800072, /* 16, -7.0dB */
89 	0x1e400079, /* 17, -6.5dB */
90 	0x20000080, /* 18, -6.0dB */
91 	0x22000088, /* 19, -5.5dB */
92 	0x24000090, /* 20, -5.0dB */
93 	0x26000098, /* 21, -4.5dB */
94 	0x288000a2, /* 22, -4.0dB */
95 	0x2ac000ab, /* 23, -3.5dB */
96 	0x2d4000b5, /* 24, -3.0dB */
97 	0x300000c0, /* 25, -2.5dB */
98 	0x32c000cb, /* 26, -2.0dB */
99 	0x35c000d7, /* 27, -1.5dB */
100 	0x390000e4, /* 28, -1.0dB */
101 	0x3c8000f2, /* 29, -0.5dB */
102 	0x40000100, /* 30, +0dB */
103 	0x43c0010f, /* 31, +0.5dB */
104 	0x47c0011f, /* 32, +1.0dB */
105 	0x4c000130, /* 33, +1.5dB */
106 	0x50800142, /* 34, +2.0dB */
107 	0x55400155, /* 35, +2.5dB */
108 	0x5a400169, /* 36, +3.0dB */
109 	0x5fc0017f, /* 37, +3.5dB */
110 	0x65400195, /* 38, +4.0dB */
111 	0x6b8001ae, /* 39, +4.5dB */
112 	0x71c001c7, /* 40, +5.0dB */
113 	0x788001e2, /* 41, +5.5dB */
114 	0x7f8001fe /* 42, +6.0dB */
118 	0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29,
119 	0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3,
123 	{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02,
124 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/
125 	{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02,
126 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/
127 	{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02,
128 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/
129 	{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02,
130 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/
131 	{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02,
132 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/
133 	{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02,
134 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/
135 	{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02,
136 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/
137 	{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02,
138 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/
139 	{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03,
140 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/
141 	{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03,
142 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/
143 	{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03,
144 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/
145 	{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03,
146 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/
147 	{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03,
148 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/
149 	{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03,
150 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/
151 	{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04,
152 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/
153 	{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04,
154 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/
155 	{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04,
156 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/
157 	{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04,
158 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/
159 	{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04,
160 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/
161 	{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05,
162 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/
163 	{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05,
164 	 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/
178 	{0x0069,
188 	 RTW_PWR_CMD_WRITE, 0xff, 0},
193 	{0x0005,
197 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
202 	{0x0023,
207 	{0x0007,
211 	 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
212 	{0x0006,
216 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
217 	{0x0005,
226 	{0x0020,
230 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
231 	{0x0067,
235 	 RTW_PWR_CMD_WRITE, BIT(4), 0},
236 	{0x0001,
241 	{0x0000,
245 	 RTW_PWR_CMD_WRITE, BIT(5), 0},
246 	{0x0005,
250 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
251 	{0x0075,
255 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
256 	{0x0004,
261 	{0x0004,
265 	 RTW_PWR_CMD_WRITE, BIT(3), 0},
267 	{0x0006,
272 	{0x0075,
276 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
277 	{0x0006,
281 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
282 	{0x0005,
286 	 RTW_PWR_CMD_WRITE, BIT(7), 0},
287 	{0x0005,
291 	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
292 	{0x0005,
296 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
297 	{0x0005,
301 	 RTW_PWR_CMD_POLLING, BIT(0), 0},
302 	{0x0010,
307 	{0x0049,
312 	{0x0063,
317 	{0x0062,
321 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
322 	{0x0058,
326 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
327 	{0x005A,
332 	{0x0068,
337 	{0x0069,
346 	{0x001f,
350 	 RTW_PWR_CMD_WRITE, 0xff, 0},
351 	{0x0049,
355 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
356 	{0x0006,
360 	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
361 	{0x0005,
366 	{0x0005,
370 	 RTW_PWR_CMD_POLLING, BIT(1), 0},
371 	{0x0010,
375 	 RTW_PWR_CMD_WRITE, BIT(6), 0},
376 	{0x0000,
381 	{0x0020,
385 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
394 	 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0},
400 	 RTW_PWR_CMD_WRITE, 0xff, 0},
406 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
411 	 RTW_PWR_CMD_WRITE, BIT(0), 1},
416 	{0x0301,
420 	 RTW_PWR_CMD_WRITE, 0xff, 0xff},
421 	{0x0522,
425 	 RTW_PWR_CMD_WRITE, 0xff, 0xff},
426 	{0x05f8,
430 	 RTW_PWR_CMD_POLLING, 0xff, 0},
431 	{0x05f9,
435 	 RTW_PWR_CMD_POLLING, 0xff, 0},
436 	{0x05fa,
440 	 RTW_PWR_CMD_POLLING, 0xff, 0},
441 	{0x05fb,
445 	 RTW_PWR_CMD_POLLING, 0xff, 0},
446 	{0x0002,
450 	 RTW_PWR_CMD_WRITE, BIT(0), 0},
451 	{0x0002,
455 	 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
456 	{0x0002,
460 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
461 	{0x0100,
465 	 RTW_PWR_CMD_WRITE, 0xff, 0x03},
466 	{0x0101,
470 	 RTW_PWR_CMD_WRITE, BIT(1), 0},
471 	{0x0093,
475 	 RTW_PWR_CMD_WRITE, 0xff, 0},
476 	{0x0553,
500 	[0] = { .phy_pg_tbl	= &rtw8703b_bb_pg_tbl,
505 	{12, 2, 2, 0, 1},
506 	{12, 2, 2, 0, 1},
507 	{12, 2, 2, 0, 1},
508 	{12, 2, 2, 0, 1},
509 	{12, 2, 2, 0, 1},
531  * contain valid data. Replaces EFUSE data from offset 0x10 (start of
535 	0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D,
536 	0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02
547 		if (ret == 0) {  in try_mac_from_devicetree()
557 		# name "=0x%x\n", rtwdev->efuse.name)
567 	if (ret != 0)  in rtw8703b_read_efuse()
576 	for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++)  in rtw8703b_read_efuse()
577 		if (pwr[i] != 0xff) {  in rtw8703b_read_efuse()
582 		for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++)  in rtw8703b_read_efuse()
591 	if (efuse->bt_setting == 0xff) {  in rtw8703b_read_efuse()
593 		efuse->bt_setting |= BIT(0);  in rtw8703b_read_efuse()
602 	 * should be 0 if there's no valid data.  in rtw8703b_read_efuse()
604 	if (efuse->rf_board_option == 0xff) {  in rtw8703b_read_efuse()
605 		efuse->regd = 0;  in rtw8703b_read_efuse()
606 		efuse->rf_board_option &= GENMASK(5, 0);  in rtw8703b_read_efuse()
613 	if (efuse->crystal_cap == 0xff) {  in rtw8703b_read_efuse()
614 		efuse->crystal_cap = 0x20;  in rtw8703b_read_efuse()
618 	return 0;  in rtw8703b_read_efuse()
637 		dm_info->delta_power_index[path] = 0;  in rtw8703b_pwrtrack_init()
642 	dm_info->txagc_remnant_cck = 0;  in rtw8703b_pwrtrack_init()
643 	dm_info->txagc_remnant_ofdm = 0;  in rtw8703b_pwrtrack_init()
648 	u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;  in rtw8703b_phy_set_param()
655 	rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780);  in rtw8703b_phy_set_param()
656 	rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);  in rtw8703b_phy_set_param()
661 	/* 0xff is from vendor driver, rtw8723d uses  in rtw8703b_phy_set_param()
666 	rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);  in rtw8703b_phy_set_param()
679 	rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);  in rtw8703b_phy_set_param()
680 	rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);  in rtw8703b_phy_set_param()
681 	rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);  in rtw8703b_phy_set_param()
682 	rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);  in rtw8703b_phy_set_param()
685 	rtw_write8(rtwdev, REG_ACKTO, 0x40);  in rtw8703b_phy_set_param()
700 		   TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);  in rtw8703b_phy_set_param()
702 		   (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0)  in rtw8703b_phy_set_param()
716 	rtw_write16(rtwdev, REG_ATIMWND, 0x2);  in rtw8703b_phy_set_param()
720 	if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) {  in rtw8703b_phy_set_param()
723 		rtwdev->dm_info.rx_cck_agc_report_type = 0;  in rtw8703b_phy_set_param()
729 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);  in rtw8703b_phy_set_param()
730 	rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);  in rtw8703b_phy_set_param()
757 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);  in rtw8703b_cfg_notch()
758 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8703b_cfg_notch()
759 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
760 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
761 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
762 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8703b_cfg_notch()
763 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8703b_cfg_notch()
771 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);  in rtw8703b_cfg_notch()
772 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
773 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000);  in rtw8703b_cfg_notch()
774 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
775 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
776 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8703b_cfg_notch()
777 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
780 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4);  in rtw8703b_cfg_notch()
781 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
782 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600);  in rtw8703b_cfg_notch()
783 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
784 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
785 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);  in rtw8703b_cfg_notch()
786 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
789 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3);  in rtw8703b_cfg_notch()
790 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
791 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
792 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
793 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
794 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000);  in rtw8703b_cfg_notch()
795 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
798 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa);  in rtw8703b_cfg_notch()
799 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
800 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
801 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
802 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
803 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380);  in rtw8703b_cfg_notch()
804 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
807 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);  in rtw8703b_cfg_notch()
808 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);  in rtw8703b_cfg_notch()
809 		rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);  in rtw8703b_cfg_notch()
810 		rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);  in rtw8703b_cfg_notch()
811 		rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);  in rtw8703b_cfg_notch()
812 		rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000);  in rtw8703b_cfg_notch()
813 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);  in rtw8703b_cfg_notch()
819 		rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);  in rtw8703b_cfg_notch()
820 		rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);  in rtw8703b_cfg_notch()
856 	u32 rf_rck = 0x00000C08;  in rtw8703b_set_channel_rf()
873 		rf_rck = 0x00000C4C;  in rtw8703b_set_channel_rf()
888 	[0] = {
889 		{ .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD },
890 		{ .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B },
893 		{ .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 },
894 		{ .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 },
904 	cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];  in rtw8703b_set_channel_bb()
906 	for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++)  in rtw8703b_set_channel_bb()
911 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8703b_set_channel_bb()
912 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);  in rtw8703b_set_channel_bb()
914 				 GENMASK(31, 20), 0x0);  in rtw8703b_set_channel_bb()
915 		rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000);  in rtw8703b_set_channel_bb()
916 		rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000);  in rtw8703b_set_channel_bb()
919 		rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8703b_set_channel_bb()
920 		rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);  in rtw8703b_set_channel_bb()
921 		rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000);  in rtw8703b_set_channel_bb()
922 		rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000);  in rtw8703b_set_channel_bb()
924 				 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0);  in rtw8703b_set_channel_bb()
925 		rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00,  in rtw8703b_set_channel_bb()
945  * known valid values are positive, so use 0x7f as "invalid".
947 #define LNA_IDX_INVALID 0x7f
957 	s8 lna_gain = 0;  in get_cck_rx_pwr()
962 	if (lna_gain >= 0) {  in get_cck_rx_pwr()
999 	val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F;  in query_phy_status_ofdm()
1006 	pkt_stat->signal_power = (val_s8 & 0x7f) - 110;  in query_phy_status_ofdm()
1017 	/* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0  in query_phy_status_ofdm()
1021 	val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64);  in query_phy_status_ofdm()
1022 	val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */  in query_phy_status_ofdm()
1043 	memset(pkt_stat, 0, sizeof(*pkt_stat));  in rtw8703b_query_rx_desc()
1056 	pkt_stat->ppdu_cnt = 0;  in rtw8703b_query_rx_desc()
1080 	if (pkt_stat->pkt_len == 0) {  in rtw8703b_query_rx_desc()
1086 #define ADDA_ON_VAL_8703B 0x03c00014
1092 	rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F);  in rtw8703b_iqk_config_mac()
1098 #define IQK_LTE_WRITE_VAL_8703B 0x00007700
1113 	rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000);  in rtw8703b_iqk_one_shot()
1114 	rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);  in rtw8703b_iqk_one_shot()
1118 	ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000,  in rtw8703b_iqk_one_shot()
1140 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0);  in rtw8703b_iqk_txrx_path_post()
1148 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",  in rtw8703b_iqk_check_tx_failed()
1150 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",  in rtw8703b_iqk_check_tx_failed()
1154 		"[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n",  in rtw8703b_iqk_check_tx_failed()
1156 		rtw_read32(rtwdev, 0xe98));  in rtw8703b_iqk_check_tx_failed()
1167 	return 0;  in rtw8703b_iqk_check_tx_failed()
1175 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",  in rtw8703b_iqk_check_rx_failed()
1180 		"[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n",  in rtw8703b_iqk_check_rx_failed()
1181 		rtw_read32(rtwdev, 0xea0),  in rtw8703b_iqk_check_rx_failed()
1182 		rtw_read32(rtwdev, 0xea8));  in rtw8703b_iqk_check_rx_failed()
1196 	return 0;  in rtw8703b_iqk_check_rx_failed()
1207 	rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);  in rtw8703b_iqk_tx_path()
1208 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8703b_iqk_tx_path()
1209 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);  in rtw8703b_iqk_tx_path()
1210 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);  in rtw8703b_iqk_tx_path()
1211 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_tx_path()
1212 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_tx_path()
1213 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f);  in rtw8703b_iqk_tx_path()
1214 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);  in rtw8703b_iqk_tx_path()
1215 	rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);  in rtw8703b_iqk_tx_path()
1216 	rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);  in rtw8703b_iqk_tx_path()
1219 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);  in rtw8703b_iqk_tx_path()
1222 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_tx_path()
1225 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);  in rtw8703b_iqk_tx_path()
1226 	rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7);  in rtw8703b_iqk_tx_path()
1227 	rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400);  in rtw8703b_iqk_tx_path()
1244 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n",  in rtw8703b_iqk_rx_path()
1246 	rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000);  in rtw8703b_iqk_rx_path()
1252 	rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);  in rtw8703b_iqk_rx_path()
1253 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8703b_iqk_rx_path()
1256 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);  in rtw8703b_iqk_rx_path()
1257 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1258 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1259 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1260 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8216000f);  in rtw8703b_iqk_rx_path()
1261 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000);  in rtw8703b_iqk_rx_path()
1262 	rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x28110000);  in rtw8703b_iqk_rx_path()
1263 	rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);  in rtw8703b_iqk_rx_path()
1266 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);  in rtw8703b_iqk_rx_path()
1269 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);  in rtw8703b_iqk_rx_path()
1270 	rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);  in rtw8703b_iqk_rx_path()
1271 	rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);  in rtw8703b_iqk_rx_path()
1272 	rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7);  in rtw8703b_iqk_rx_path()
1276 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_rx_path()
1287 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",  in rtw8703b_iqk_rx_path()
1292 	rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n",  in rtw8703b_iqk_rx_path()
1296 	rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);  in rtw8703b_iqk_rx_path()
1297 	rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1298 	rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);  in rtw8703b_iqk_rx_path()
1299 	rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1300 	rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtw8703b_iqk_rx_path()
1301 	rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000);  in rtw8703b_iqk_rx_path()
1302 	rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f);  in rtw8703b_iqk_rx_path()
1303 	rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000);  in rtw8703b_iqk_rx_path()
1304 	rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000);  in rtw8703b_iqk_rx_path()
1307 	rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);  in rtw8703b_iqk_rx_path()
1310 	rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000);  in rtw8703b_iqk_rx_path()
1312 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1);  in rtw8703b_iqk_rx_path()
1314 	rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000);  in rtw8703b_iqk_rx_path()
1315 	rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007);  in rtw8703b_iqk_rx_path()
1316 	rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77);  in rtw8703b_iqk_rx_path()
1319 	rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1);  in rtw8703b_iqk_rx_path()
1320 	rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5);  in rtw8703b_iqk_rx_path()
1343 	rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);  in rtw8703b_iqk_one_round()
1344 	rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600);  in rtw8703b_iqk_one_round()
1345 	rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);  in rtw8703b_iqk_one_round()
1346 	rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000);  in rtw8703b_iqk_one_round()
1348 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8703b_iqk_one_round()
1363 		result[t][IQK_S1_TX_X] = 0x100;  in rtw8703b_iqk_one_round()
1364 		result[t][IQK_S1_TX_Y] = 0x0;  in rtw8703b_iqk_one_round()
1367 	for (i = 0; i < PATH_IQK_RETRY; i++) {  in rtw8703b_iqk_one_round()
1382 		result[t][IQK_S1_RX_X] = 0x100;  in rtw8703b_iqk_one_round()
1383 		result[t][IQK_S1_RX_Y] = 0x0;  in rtw8703b_iqk_one_round()
1386 	if (a_ok == 0x0)  in rtw8703b_iqk_one_round()
1396 	u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16);  in rtw8703b_iqk_fill_a_matrix()
1402 	if (result[IQK_S1_TX_X] == 0)  in rtw8703b_iqk_fill_a_matrix()
1425 		"[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",  in rtw8703b_iqk_fill_a_matrix()
1428 		"[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);  in rtw8703b_iqk_fill_a_matrix()
1430 	if (result[IQK_S1_RX_X] == 0)  in rtw8703b_iqk_fill_a_matrix()
1454 	memset(result, 0, sizeof(result));  in rtw8703b_phy_calibration()
1487 		s32 reg_tmp = 0;  in rtw8703b_phy_calibration()
1489 		for (i = 0; i < IQK_NR; i++)  in rtw8703b_phy_calibration()
1492 		if (reg_tmp != 0) {  in rtw8703b_phy_calibration()
1520 			result[i][0], result[i][1], result[i][2], result[i][3],  in rtw8703b_phy_calibration()
1525 		"[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",  in rtw8703b_phy_calibration()
1531 		"[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",  in rtw8703b_phy_calibration()
1574 		/* write new elements A, C, D, and element B is always 0 */  in rtw8703b_set_iqk_matrix_by_result()
1587 		/* write new elements A, C, D, and element B is always 0 */  in rtw8703b_set_iqk_matrix_by_result()
1608 	ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1);  in rtw8703b_set_iqk_matrix()
1622 				 0x00);  in rtw8703b_set_iqk_matrix()
1632 				 0x00);  in rtw8703b_set_iqk_matrix()
1659 	swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1);  in rtw8703b_pwrtrack_set_cck_pwr()
1662 		     != ARRAY_SIZE(rtw8703b_cck_swing_table[0]));  in rtw8703b_pwrtrack_set_cck_pwr()
1664 	for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++)  in rtw8703b_pwrtrack_set_cck_pwr()
1688 	else if (final_ofdm_swing_index < 0)  in rtw8703b_pwrtrack_set()
1689 		rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0,  in rtw8703b_pwrtrack_set()
1692 		rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);  in rtw8703b_pwrtrack_set()
1697 	else if (final_cck_swing_index < 0)  in rtw8703b_pwrtrack_set()
1698 		rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0,  in rtw8703b_pwrtrack_set()
1701 		rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);  in rtw8703b_pwrtrack_set()
1715 	if (rtwdev->efuse.thermal_meter[0] == 0xff)  in rtw8703b_phy_pwrtrack()
1718 	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);  in rtw8703b_phy_pwrtrack()
1737 	for (path = 0; path < rtwdev->hal.rf_path_num; path++) {  in rtw8703b_phy_pwrtrack()
1762 	if (efuse->power_track_type != 0) {  in rtw8703b_pwr_track()
1769 			     GENMASK(17, 16), 0x03);  in rtw8703b_pwr_track()
1792 	coex_rfe->ant_switch_polarity = 0;  in rtw8703b_coex_set_rfe_type()
1799 	rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);  in rtw8703b_coex_set_rfe_type()
1800 	rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8703b_coex_set_rfe_type()
1801 	rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);  in rtw8703b_coex_set_rfe_type()
1813 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1818 	0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1823 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1828 	0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7,
1833 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1838 	0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1843 	0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6,
1848 	0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6,
1853 	0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3,
1854 	-4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1
1858 	0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1,
1877 	{0xffffffff, 0xffffffff}, /* case-0 */
1878 	{0x55555555, 0x55555555},
1879 	{0x66555555, 0x66555555},
1880 	{0xaaaaaaaa, 0xaaaaaaaa},
1881 	{0x5a5a5a5a, 0x5a5a5a5a},
1882 	{0xfafafafa, 0xfafafafa}, /* case-5 */
1883 	{0x6a5a5555, 0xaaaaaaaa},
1884 	{0x6a5a56aa, 0x6a5a56aa},
1885 	{0x6a5a5a5a, 0x6a5a5a5a},
1886 	{0x66555555, 0x5a5a5a5a},
1887 	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1888 	{0x66555555, 0x6a5a5aaa},
1889 	{0x66555555, 0x5a5a5aaa},
1890 	{0x66555555, 0x6aaa5aaa},
1891 	{0x66555555, 0xaaaa5aaa},
1892 	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1893 	{0xffff55ff, 0xfafafafa},
1894 	{0xffff55ff, 0x6afa5afa},
1895 	{0xaaffffaa, 0xfafafafa},
1896 	{0xaa5555aa, 0x5a5a5a5a},
1897 	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1898 	{0xaa5555aa, 0xaaaaaaaa},
1899 	{0xffffffff, 0x5a5a5a5a},
1900 	{0xffffffff, 0x5a5a5a5a},
1901 	{0xffffffff, 0x55555555},
1902 	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
1903 	{0x55555555, 0x5a5a5a5a},
1904 	{0x55555555, 0xaaaaaaaa},
1905 	{0x55555555, 0x6a5a6a5a},
1906 	{0x66556655, 0x66556655},
1907 	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1908 	{0xffffffff, 0x5aaa5aaa},
1909 	{0x56555555, 0x5a5a5aaa},
1914 	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1915 	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1916 	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
1917 	{ {0x61, 0x30, 0x03, 0x11, 0x11} },
1918 	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1919 	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1920 	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1921 	{ {0x61, 0x3a, 0x03, 0x11, 0x10} },
1922 	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1923 	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1924 	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1925 	{ {0x61, 0x08, 0x03, 0x11, 0x14} },
1926 	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1927 	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1928 	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1929 	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1930 	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1931 	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
1932 	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1933 	{ {0x51, 0x20, 0x03, 0x10, 0x50} },
1934 	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1935 	{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
1936 	{ {0x51, 0x0c, 0x03, 0x10, 0x54} },
1937 	{ {0x55, 0x08, 0x03, 0x10, 0x54} },
1938 	{ {0x65, 0x10, 0x03, 0x11, 0x10} },
1939 	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1940 	{ {0x51, 0x08, 0x03, 0x10, 0x50} },
1941 	{ {0x61, 0x08, 0x03, 0x11, 0x11} },
1964 	 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only
2008 	.csi_buf_pg_num = 0,
2009 	.dig_min = 0x20,
2014 	.max_power_index = 0x3f,
2021 	.lps_deep_mode_supported = 0,
2023 	.sys_func_en = 0xFD,
2035 	.rf_sipi_addr = {0x840, 0x844},
2059 	.coex_para_ver = 0x0133ed6a,
2060 	.bt_desired_ver = 0x1c,
2076 	.table_nsant_num = 0,
2080 	.tdma_nsant_num = 0,
2085 	.bt_afh_span_bw20 = 0x20,
2086 	.bt_afh_span_bw40 = 0x30,
2093 	 * (by address, 0x0067), comment: "0x67[0] = 0 to disable
2100 	.coex_info_hw_regs_num = 0,