Lines Matching +full:sar +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
13 #include "sar.h"
113 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd_init()
118 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0; in rtw_phy_cck_pd_init()
121 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw_phy_cck_pd_init()
126 struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th; in rtw_phy_set_edcca_th()
141 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_set_mode()
142 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_adaptivity_set_mode()
146 dm_info->edcca_mode = RTW_EDCCA_NORMAL; in rtw_phy_adaptivity_set_mode()
151 switch (rtwdev->regd.dfs_region) { in rtw_phy_adaptivity_set_mode()
153 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY; in rtw_phy_adaptivity_set_mode()
154 dm_info->l2h_th_ini = chip->l2h_th_ini_ad; in rtw_phy_adaptivity_set_mode()
157 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY; in rtw_phy_adaptivity_set_mode()
158 dm_info->l2h_th_ini = chip->l2h_th_ini_cs; in rtw_phy_adaptivity_set_mode()
161 dm_info->edcca_mode = RTW_EDCCA_NORMAL; in rtw_phy_adaptivity_set_mode()
168 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_init()
171 if (chip->ops->adaptivity_init) in rtw_phy_adaptivity_init()
172 chip->ops->adaptivity_init(rtwdev); in rtw_phy_adaptivity_init()
177 if (rtwdev->chip->ops->adaptivity) in rtw_phy_adaptivity()
178 rtwdev->chip->ops->adaptivity(rtwdev); in rtw_phy_adaptivity()
183 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_init()
185 if (chip->ops->cfo_init) in rtw_phy_cfo_init()
186 chip->ops->cfo_init(rtwdev); in rtw_phy_cfo_init()
191 struct rtw_path_div *path_div = &rtwdev->dm_path_div; in rtw_phy_tx_path_div_init()
193 path_div->current_tx_path = rtwdev->chip->default_1ss_tx_path; in rtw_phy_tx_path_div_init()
194 path_div->path_a_cnt = 0; in rtw_phy_tx_path_div_init()
195 path_div->path_a_sum = 0; in rtw_phy_tx_path_div_init()
196 path_div->path_b_cnt = 0; in rtw_phy_tx_path_div_init()
197 path_div->path_b_sum = 0; in rtw_phy_tx_path_div_init()
202 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_init()
203 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_init()
206 dm_info->fa_history[3] = 0; in rtw_phy_init()
207 dm_info->fa_history[2] = 0; in rtw_phy_init()
208 dm_info->fa_history[1] = 0; in rtw_phy_init()
209 dm_info->fa_history[0] = 0; in rtw_phy_init()
210 dm_info->igi_bitmap = 0; in rtw_phy_init()
211 dm_info->igi_history[3] = 0; in rtw_phy_init()
212 dm_info->igi_history[2] = 0; in rtw_phy_init()
213 dm_info->igi_history[1] = 0; in rtw_phy_init()
215 addr = chip->dig[0].addr; in rtw_phy_init()
216 mask = chip->dig[0].mask; in rtw_phy_init()
217 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask); in rtw_phy_init()
220 dm_info->iqk.done = false; in rtw_phy_init()
229 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_dig_write()
230 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_dig_write()
234 if (chip->dig_cck) { in rtw_phy_dig_write()
235 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0]; in rtw_phy_dig_write()
236 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1); in rtw_phy_dig_write()
239 for (path = 0; path < hal->rf_path_num; path++) { in rtw_phy_dig_write()
240 addr = chip->dig[path].addr; in rtw_phy_dig_write()
241 mask = chip->dig[path].mask; in rtw_phy_dig_write()
248 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_stat_false_alarm()
250 chip->ops->false_alarm_statistics(rtwdev); in rtw_phy_stat_false_alarm()
284 struct rtw_dev *rtwdev = iter_data->rtwdev; in rtw_phy_stat_rssi_iter()
285 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_phy_stat_rssi_iter()
288 rssi = ewma_rssi_read(&si->avg_rssi); in rtw_phy_stat_rssi_iter()
289 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi); in rtw_phy_stat_rssi_iter()
293 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi); in rtw_phy_stat_rssi_iter()
298 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_stat_rssi()
305 dm_info->pre_min_rssi = dm_info->min_rssi; in rtw_phy_stat_rssi()
306 dm_info->min_rssi = data.min_rssi; in rtw_phy_stat_rssi()
311 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_stat_rate_cnt()
313 dm_info->last_pkt_count = dm_info->cur_pkt_count; in rtw_phy_stat_rate_cnt()
314 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count)); in rtw_phy_stat_rate_cnt()
350 min_rssi = dm_info->min_rssi; in rtw_phy_dig_check_damping()
351 if (dm_info->damping) { in rtw_phy_dig_check_damping()
352 damping_rssi = dm_info->damping_rssi; in rtw_phy_dig_check_damping()
353 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi : in rtw_phy_dig_check_damping()
354 damping_rssi - min_rssi; in rtw_phy_dig_check_damping()
355 if (diff > 3 || dm_info->damping_cnt++ > 20) { in rtw_phy_dig_check_damping()
356 dm_info->damping = false; in rtw_phy_dig_check_damping()
363 igi_history = dm_info->igi_history; in rtw_phy_dig_check_damping()
364 fa_history = dm_info->fa_history; in rtw_phy_dig_check_damping()
365 igi_bitmap = dm_info->igi_bitmap & 0xf; in rtw_phy_dig_check_damping()
368 /* down -> up -> down -> up */ in rtw_phy_dig_check_damping()
371 igi_history[0] - igi_history[1] >= 2 && in rtw_phy_dig_check_damping()
372 igi_history[2] - igi_history[3] >= 2 && in rtw_phy_dig_check_damping()
378 /* up -> down -> down -> up */ in rtw_phy_dig_check_damping()
381 igi_history[0] - igi_history[1] >= 4 && in rtw_phy_dig_check_damping()
382 igi_history[3] - igi_history[2] >= 2 && in rtw_phy_dig_check_damping()
392 dm_info->damping = true; in rtw_phy_dig_check_damping()
393 dm_info->damping_cnt = 0; in rtw_phy_dig_check_damping()
394 dm_info->damping_rssi = min_rssi; in rtw_phy_dig_check_damping()
410 dig_min = rtwdev->chip->dig_min; in rtw_phy_dig_get_boundary()
411 min_rssi = max_t(u8, dm_info->min_rssi, dig_min); in rtw_phy_dig_get_boundary()
431 min_rssi = dm_info->min_rssi; in rtw_phy_dig_get_threshold()
432 pre_min_rssi = dm_info->pre_min_rssi; in rtw_phy_dig_get_threshold()
460 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe; in rtw_phy_dig_recorder()
461 igi_history = dm_info->igi_history; in rtw_phy_dig_recorder()
462 fa_history = dm_info->fa_history; in rtw_phy_dig_recorder()
477 dm_info->igi_bitmap = igi_bitmap; in rtw_phy_dig_recorder()
482 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_dig()
490 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags)) in rtw_phy_dig()
496 linked = !!rtwdev->sta_cnt; in rtw_phy_dig()
498 fa_cnt = dm_info->total_fa_cnt; in rtw_phy_dig()
499 pre_igi = dm_info->igi_history[0]; in rtw_phy_dig()
503 /* test the false alarm count from the highest threshold level first, in rtw_phy_dig()
506 * note that the step size is offset by -2, compensate it afterall in rtw_phy_dig()
515 cur_igi -= 2; in rtw_phy_dig()
537 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_phy_ra_info_update_iter()
544 if (rtwdev->watch_dog_cnt & 0x3) in rtw_phy_ra_info_update()
557 rate_order -= DESC_RATEVHT4SS_MCS0; in rtw_phy_get_rrsr_mask()
559 rate_order -= DESC_RATEVHT3SS_MCS0; in rtw_phy_get_rrsr_mask()
561 rate_order -= DESC_RATEVHT2SS_MCS0; in rtw_phy_get_rrsr_mask()
563 rate_order -= DESC_RATEVHT1SS_MCS0; in rtw_phy_get_rrsr_mask()
565 rate_order -= DESC_RATEMCS24; in rtw_phy_get_rrsr_mask()
567 rate_order -= DESC_RATEMCS16; in rtw_phy_get_rrsr_mask()
569 rate_order -= DESC_RATEMCS8; in rtw_phy_get_rrsr_mask()
571 rate_order -= DESC_RATEMCS0; in rtw_phy_get_rrsr_mask()
573 rate_order -= DESC_RATE6M; in rtw_phy_get_rrsr_mask()
575 rate_order -= DESC_RATE1M; in rtw_phy_get_rrsr_mask()
580 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0); in rtw_phy_get_rrsr_mask()
586 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; in rtw_phy_rrsr_mask_min_iter()
587 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_rrsr_mask_min_iter()
590 mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate); in rtw_phy_rrsr_mask_min_iter()
591 if (mask < dm_info->rrsr_mask_min) in rtw_phy_rrsr_mask_min_iter()
592 dm_info->rrsr_mask_min = mask; in rtw_phy_rrsr_mask_min_iter()
597 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_rrsr_update()
599 dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX; in rtw_phy_rrsr_update()
601 rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min); in rtw_phy_rrsr_update()
606 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_dpk_track()
608 if (chip->ops->dpk_track) in rtw_phy_dpk_track()
609 chip->ops->dpk_track(rtwdev); in rtw_phy_dpk_track()
623 struct rtw_dev *rtwdev = iter_data->rtwdev; in rtw_phy_parsing_cfo_iter()
624 struct rtw_rx_pkt_stat *pkt_stat = iter_data->pkt_stat; in rtw_phy_parsing_cfo_iter()
625 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_parsing_cfo_iter()
626 struct rtw_cfo_track *cfo = &dm_info->cfo_track; in rtw_phy_parsing_cfo_iter()
627 u8 *bssid = iter_data->bssid; in rtw_phy_parsing_cfo_iter()
630 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) in rtw_phy_parsing_cfo_iter()
633 for (i = 0; i < rtwdev->hal.rf_path_num; i++) { in rtw_phy_parsing_cfo_iter()
634 cfo->cfo_tail[i] += pkt_stat->cfo_tail[i]; in rtw_phy_parsing_cfo_iter()
635 cfo->cfo_cnt[i]++; in rtw_phy_parsing_cfo_iter()
638 cfo->packet_count++; in rtw_phy_parsing_cfo_iter()
644 struct ieee80211_hdr *hdr = pkt_stat->hdr; in rtw_phy_parsing_cfo()
647 if (pkt_stat->crc_err || pkt_stat->icv_err || !pkt_stat->phy_status || in rtw_phy_parsing_cfo()
648 ieee80211_is_ctl(hdr->frame_control)) in rtw_phy_parsing_cfo()
662 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_track()
664 if (chip->ops->cfo_track) in rtw_phy_cfo_track()
665 chip->ops->cfo_track(rtwdev); in rtw_phy_cfo_track()
673 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd_lv_unlink()
674 u32 cck_fa_avg = dm_info->cck_fa_avg; in rtw_phy_cck_pd_lv_unlink()
694 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd_lv_link()
695 u8 igi = dm_info->igi_history[0]; in rtw_phy_cck_pd_lv_link()
696 u8 rssi = dm_info->min_rssi; in rtw_phy_cck_pd_lv_link()
697 u32 cck_fa_avg = dm_info->cck_fa_avg; in rtw_phy_cck_pd_lv_link()
723 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cck_pd()
724 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_cck_pd()
725 u32 cck_fa = dm_info->cck_fa_cnt; in rtw_phy_cck_pd()
728 if (rtwdev->hal.current_band_type != RTW_BAND_2G) in rtw_phy_cck_pd()
731 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET) in rtw_phy_cck_pd()
732 dm_info->cck_fa_avg = cck_fa; in rtw_phy_cck_pd()
734 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2; in rtw_phy_cck_pd()
737 dm_info->igi_history[0], dm_info->min_rssi, in rtw_phy_cck_pd()
738 dm_info->fa_history[0]); in rtw_phy_cck_pd()
740 dm_info->cck_fa_avg, dm_info->cck_pd_default); in rtw_phy_cck_pd()
747 if (chip->ops->cck_pd_set) in rtw_phy_cck_pd()
748 chip->ops->cck_pd_set(rtwdev, level); in rtw_phy_cck_pd()
753 rtwdev->chip->ops->pwr_track(rtwdev); in rtw_phy_pwr_track()
775 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_ADAPTIVITY)) in rtw_phy_dynamic_mechanism()
785 if (power <= -100 || power >= 20) in rtw_phy_power_2_db()
804 i = (power_db - 1) >> 3; in rtw_phy_db_2_linear()
805 j = (power_db - 1) - (i << 3); in rtw_phy_db_2_linear()
836 if (db_invert_table[i][0] - linear > in rtw_phy_linear_2_db()
837 linear - db_invert_table[i - 1][7]) { in rtw_phy_linear_2_db()
838 i = i - 1; in rtw_phy_linear_2_db()
842 if (db_invert_table[3][0] - linear > in rtw_phy_linear_2_db()
843 linear - db_invert_table[2][7]) { in rtw_phy_linear_2_db()
849 if (db_invert_table[i][j] - linear > in rtw_phy_linear_2_db()
850 linear - db_invert_table[i][j - 1]) { in rtw_phy_linear_2_db()
851 j = j - 1; in rtw_phy_linear_2_db()
875 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; in rtw_phy_rf_power_2_rssi()
897 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_read_rf()
898 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_read_rf()
899 const u32 *base_addr = chip->rf_base_addr; in rtw_phy_read_rf()
902 if (rf_path >= hal->rf_phy_num) { in rtw_phy_read_rf()
920 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_read_rf_sipi()
921 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_read_rf_sipi()
929 if (rf_path >= hal->rf_phy_num) { in rtw_phy_read_rf_sipi()
934 if (!chip->rf_sipi_read_addr) { in rtw_phy_read_rf_sipi()
939 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path]; in rtw_phy_read_rf_sipi()
940 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A]; in rtw_phy_read_rf_sipi()
944 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2); in rtw_phy_read_rf_sipi()
946 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32); in rtw_phy_read_rf_sipi()
949 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2); in rtw_phy_read_rf_sipi()
950 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK); in rtw_phy_read_rf_sipi()
951 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK); in rtw_phy_read_rf_sipi()
955 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8)); in rtw_phy_read_rf_sipi()
956 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read; in rtw_phy_read_rf_sipi()
969 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_write_rf_reg_sipi()
970 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_write_rf_reg_sipi()
971 const u32 *sipi_addr = chip->rf_sipi_addr; in rtw_phy_write_rf_reg_sipi()
976 if (rf_path >= hal->rf_phy_num) { in rtw_phy_write_rf_reg_sipi()
985 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK); in rtw_phy_write_rf_reg_sipi()
1009 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_write_rf_reg()
1010 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_write_rf_reg()
1011 const u32 *base_addr = chip->rf_base_addr; in rtw_phy_write_rf_reg()
1014 if (rf_path >= hal->rf_phy_num) { in rtw_phy_write_rf_reg()
1042 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_setup_phy_cond()
1043 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_phy_setup_phy_cond()
1046 cond.cut = hal->cut_version ? hal->cut_version : 15; in rtw_phy_setup_phy_cond()
1049 cond.rfe = efuse->rfe_option; in rtw_phy_setup_phy_cond()
1064 hal->phy_cond = cond; in rtw_phy_setup_phy_cond()
1066 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond)); in rtw_phy_setup_phy_cond()
1071 struct rtw_hal *hal = &rtwdev->hal; in check_positive()
1072 struct rtw_phy_cond drv_cond = hal->phy_cond; in check_positive()
1091 const union phy_table_tile *p = tbl->data; in rtw_parse_tbl_phy_cond()
1092 const union phy_table_tile *end = p + tbl->size / 2; in rtw_parse_tbl_phy_cond()
1099 if (p->cond.pos) { in rtw_parse_tbl_phy_cond()
1100 switch (p->cond.branch) { in rtw_parse_tbl_phy_cond()
1111 pos_cond = p->cond; in rtw_parse_tbl_phy_cond()
1114 } else if (p->cond.neg) { in rtw_parse_tbl_phy_cond()
1127 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data); in rtw_parse_tbl_phy_cond()
1137 if (rtwdev->chip->is_pwr_by_rate_dec) in tbl_to_dec_pwr_by_rate()
1182 pwr_by_rate[i - 1] = in rtw_phy_get_rate_values_of_txpwr_by_rate()
1236 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev, in rtw_phy_get_rate_values_of_txpwr_by_rate()
1452 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_store_tx_power_by_rate()
1472 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset; in rtw_phy_store_tx_power_by_rate()
1474 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset; in rtw_phy_store_tx_power_by_rate()
1482 const struct rtw_phy_pg_cfg_pair *p = tbl->data; in rtw_parse_tbl_bb_pg()
1483 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size; in rtw_parse_tbl_bb_pg()
1486 if (p->addr == 0xfe || p->addr == 0xffe) { in rtw_parse_tbl_bb_pg()
1490 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path, in rtw_parse_tbl_bb_pg()
1491 p->tx_num, p->addr, p->bitmask, in rtw_parse_tbl_bb_pg()
1492 p->data); in rtw_parse_tbl_bb_pg()
1512 ch_idx = channel - 1; in rtw_channel_to_idx()
1520 return -1; in rtw_channel_to_idx()
1524 return -1; in rtw_channel_to_idx()
1532 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_limit()
1533 u8 max_power_index = rtwdev->chip->max_power_index; in rtw_phy_set_tx_power_limit()
1538 -max_power_index, max_power_index); in rtw_phy_set_tx_power_limit()
1550 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1551 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1553 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1555 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; in rtw_phy_set_tx_power_limit()
1556 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; in rtw_phy_set_tx_power_limit()
1558 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; in rtw_phy_set_tx_power_limit()
1562 /* cross-reference 5G power limits if values are not assigned */
1567 struct rtw_hal *hal = &rtwdev->hal; in rtw_xref_5g_txpwr_lmt()
1568 u8 max_power_index = rtwdev->chip->max_power_index; in rtw_xref_5g_txpwr_lmt()
1569 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx]; in rtw_xref_5g_txpwr_lmt()
1570 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx]; in rtw_xref_5g_txpwr_lmt()
1576 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht; in rtw_xref_5g_txpwr_lmt()
1579 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht; in rtw_xref_5g_txpwr_lmt()
1582 /* cross-reference power limits for ht and vht */
1598 /* cross-reference power limits for 5G channels */
1608 /* cross-reference power limits for 20/40M bandwidth */
1618 /* cross-reference power limits */
1633 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = in __cfg_txpwr_lmt_by_alt()
1634 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch]; in __cfg_txpwr_lmt_by_alt()
1637 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = in __cfg_txpwr_lmt_by_alt()
1638 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch]; in __cfg_txpwr_lmt_by_alt()
1648 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt, in rtw_cfg_txpwr_lmt_by_alt()
1655 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data; in rtw_parse_tbl_txpwr_lmt()
1656 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size; in rtw_parse_tbl_txpwr_lmt()
1662 regd_cfg_flag |= BIT(p->regd); in rtw_parse_tbl_txpwr_lmt()
1663 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band, in rtw_parse_tbl_txpwr_lmt()
1664 p->bw, p->rs, p->ch, p->txpwr_lmt); in rtw_parse_tbl_txpwr_lmt()
1737 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data); in rtw_phy_cfg_rf()
1745 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_load_rfk_table()
1746 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; in rtw_load_rfk_table()
1748 if (!chip->rfk_init_tbl) in rtw_load_rfk_table()
1757 rtw_load_table(rtwdev, chip->rfk_init_tbl); in rtw_load_rfk_table()
1759 dpk_info->is_dpk_pwr_on = true; in rtw_load_rfk_table()
1765 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_load_tables()
1768 rtw_load_table(rtwdev, chip->mac_tbl); in rtw_phy_load_tables()
1769 rtw_load_table(rtwdev, chip->bb_tbl); in rtw_phy_load_tables()
1770 rtw_load_table(rtwdev, chip->agc_tbl); in rtw_phy_load_tables()
1771 if (rfe_def->agc_btg_tbl) in rtw_phy_load_tables()
1772 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); in rtw_phy_load_tables()
1775 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) { in rtw_phy_load_tables()
1778 tbl = chip->rf_tbl[rf_path]; in rtw_phy_load_tables()
1876 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_get_dis_dpd_by_rate_diff()
1879 if (!chip->en_dis_dpd) in rtw_phy_get_dis_dpd_by_rate_diff()
1884 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \ in rtw_phy_get_dis_dpd_by_rate_diff()
1885 dpd_diff = -6 * chip->txgi_factor; \ in rtw_phy_get_dis_dpd_by_rate_diff()
1910 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_get_2g_tx_power_index()
1914 u8 factor = chip->txgi_factor; in rtw_phy_get_2g_tx_power_index()
1917 tx_power = pwr_idx_2g->cck_base[group]; in rtw_phy_get_2g_tx_power_index()
1919 tx_power = pwr_idx_2g->bw40_base[group]; in rtw_phy_get_2g_tx_power_index()
1922 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor; in rtw_phy_get_2g_tx_power_index()
1938 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor; in rtw_phy_get_2g_tx_power_index()
1940 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor; in rtw_phy_get_2g_tx_power_index()
1945 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor; in rtw_phy_get_2g_tx_power_index()
1957 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_get_5g_tx_power_index()
1962 u8 factor = chip->txgi_factor; in rtw_phy_get_5g_tx_power_index()
1964 tx_power = pwr_idx_5g->bw40_base[group]; in rtw_phy_get_5g_tx_power_index()
1973 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor; in rtw_phy_get_5g_tx_power_index()
1982 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor; in rtw_phy_get_5g_tx_power_index()
1984 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor; in rtw_phy_get_5g_tx_power_index()
1989 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor; in rtw_phy_get_5g_tx_power_index()
1992 /* the base idx of bw80 is the average of bw40+/bw40- */ in rtw_phy_get_5g_tx_power_index()
1993 lower = pwr_idx_5g->bw40_base[group]; in rtw_phy_get_5g_tx_power_index()
1994 upper = pwr_idx_5g->bw40_base[group + 1]; in rtw_phy_get_5g_tx_power_index()
1997 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor; in rtw_phy_get_5g_tx_power_index()
1999 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor; in rtw_phy_get_5g_tx_power_index()
2029 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_get_tx_power_limit()
2030 u8 *cch_by_bw = hal->cch_by_bw; in rtw_phy_get_tx_power_limit()
2031 s8 power_limit = (s8)rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_limit()
2060 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] : in rtw_phy_get_tx_power_limit()
2061 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx]; in rtw_phy_get_tx_power_limit()
2071 return (s8)rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_limit()
2092 return (s8)rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_sar()
2098 struct rtw_hal *hal = &rtwdev->hal; in rtw_get_tx_power_params()
2099 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_get_tx_power_params()
2102 u8 *base = &pwr_param->pwr_base; in rtw_get_tx_power_params()
2103 s8 *offset = &pwr_param->pwr_offset; in rtw_get_tx_power_params()
2104 s8 *limit = &pwr_param->pwr_limit; in rtw_get_tx_power_params()
2105 s8 *remnant = &pwr_param->pwr_remnant; in rtw_get_tx_power_params()
2106 s8 *sar = &pwr_param->pwr_sar; in rtw_get_tx_power_params() local
2108 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path]; in rtw_get_tx_power_params()
2115 &pwr_idx->pwr_idx_2g, in rtw_get_tx_power_params()
2117 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate]; in rtw_get_tx_power_params()
2121 &pwr_idx->pwr_idx_5g, in rtw_get_tx_power_params()
2123 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate]; in rtw_get_tx_power_params()
2128 *remnant = (rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck : in rtw_get_tx_power_params()
2129 dm_info->txagc_remnant_ofdm); in rtw_get_tx_power_params()
2130 *sar = rtw_phy_get_tx_power_sar(rtwdev, hal->sar_band, path, rate); in rtw_get_tx_power_params()
2149 if (rtwdev->chip->en_dis_dpd) in rtw_phy_get_tx_power_index()
2154 if (tx_power > rtwdev->chip->max_power_index) in rtw_phy_get_tx_power_index()
2155 tx_power = rtwdev->chip->max_power_index; in rtw_phy_get_tx_power_index()
2164 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_index_by_rs()
2178 bw = hal->current_band_width; in rtw_phy_set_tx_power_index_by_rs()
2183 hal->tx_pwr_tbl[path][rate] = pwr_idx; in rtw_phy_set_tx_power_index_by_rs()
2189 * power index into a four-byte power index register, and calls set_tx_agc to
2195 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_level_by_path()
2199 if (hal->current_band_type == RTW_BAND_2G) in rtw_phy_set_tx_power_level_by_path()
2210 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_set_tx_power_level()
2211 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_set_tx_power_level()
2214 mutex_lock(&hal->tx_power_mutex); in rtw_phy_set_tx_power_level()
2216 for (path = 0; path < hal->rf_path_num; path++) in rtw_phy_set_tx_power_level()
2219 chip->ops->set_tx_power_index(rtwdev); in rtw_phy_set_tx_power_level()
2220 mutex_unlock(&hal->tx_power_mutex); in rtw_phy_set_tx_power_level()
2233 base_idx = rates[size - 3]; in rtw_phy_tx_power_by_rate_config_by_path()
2235 base_idx = rates[size - 1]; in rtw_phy_tx_power_by_rate_config_by_path()
2236 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx]; in rtw_phy_tx_power_by_rate_config_by_path()
2237 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx]; in rtw_phy_tx_power_by_rate_config_by_path()
2238 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g; in rtw_phy_tx_power_by_rate_config_by_path()
2239 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g; in rtw_phy_tx_power_by_rate_config_by_path()
2242 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g; in rtw_phy_tx_power_by_rate_config_by_path()
2243 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g; in rtw_phy_tx_power_by_rate_config_by_path()
2280 base = hal->tx_pwr_by_rate_base_2g[0][rs]; in __rtw_phy_tx_power_limit_config()
2281 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base; in __rtw_phy_tx_power_limit_config()
2285 base = hal->tx_pwr_by_rate_base_5g[0][rs]; in __rtw_phy_tx_power_limit_config()
2286 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base; in __rtw_phy_tx_power_limit_config()
2295 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1; in rtw_phy_tx_power_limit_config()
2306 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_init_tx_power_limit()
2307 s8 max_power_index = (s8)rtwdev->chip->max_power_index; in rtw_phy_init_tx_power_limit()
2312 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index; in rtw_phy_init_tx_power_limit()
2316 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index; in rtw_phy_init_tx_power_limit()
2321 struct rtw_hal *hal = &rtwdev->hal; in rtw_phy_init_tx_power()
2327 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0; in rtw_phy_init_tx_power()
2328 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0; in rtw_phy_init_tx_power()
2343 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; in rtw_phy_config_swing_table()
2344 u8 channel = rtwdev->hal.current_channel; in rtw_phy_config_swing_table()
2347 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) { in rtw_phy_config_swing_table()
2348 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p; in rtw_phy_config_swing_table()
2349 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n; in rtw_phy_config_swing_table()
2350 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p; in rtw_phy_config_swing_table()
2351 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n; in rtw_phy_config_swing_table()
2353 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; in rtw_phy_config_swing_table()
2354 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; in rtw_phy_config_swing_table()
2355 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; in rtw_phy_config_swing_table()
2356 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; in rtw_phy_config_swing_table()
2359 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2360 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2361 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2362 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1]; in rtw_phy_config_swing_table()
2364 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2365 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2366 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2367 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2]; in rtw_phy_config_swing_table()
2369 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2370 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2371 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2372 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3]; in rtw_phy_config_swing_table()
2374 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; in rtw_phy_config_swing_table()
2375 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; in rtw_phy_config_swing_table()
2376 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; in rtw_phy_config_swing_table()
2377 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; in rtw_phy_config_swing_table()
2384 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_avg()
2386 ewma_thermal_add(&dm_info->avg_thermal[path], thermal); in rtw_phy_pwrtrack_avg()
2387 dm_info->thermal_avg[path] = in rtw_phy_pwrtrack_avg()
2388 ewma_thermal_read(&dm_info->avg_thermal[path]); in rtw_phy_pwrtrack_avg()
2395 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_thermal_changed()
2396 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]); in rtw_phy_pwrtrack_thermal_changed()
2407 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_get_delta()
2410 therm_avg = dm_info->thermal_avg[path]; in rtw_phy_pwrtrack_get_delta()
2411 therm_efuse = rtwdev->efuse.thermal_meter[path]; in rtw_phy_pwrtrack_get_delta()
2412 therm_delta = abs(therm_avg - therm_efuse); in rtw_phy_pwrtrack_get_delta()
2414 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw_phy_pwrtrack_get_delta()
2422 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_get_pwridx()
2436 delta_swing_table_idx_pos = swing_table->p[tbl_path]; in rtw_phy_pwrtrack_get_pwridx()
2437 delta_swing_table_idx_neg = swing_table->n[tbl_path]; in rtw_phy_pwrtrack_get_pwridx()
2444 if (dm_info->thermal_avg[therm_path] > in rtw_phy_pwrtrack_get_pwridx()
2445 rtwdev->efuse.thermal_meter[therm_path]) in rtw_phy_pwrtrack_get_pwridx()
2448 return -delta_swing_table_idx_neg[delta]; in rtw_phy_pwrtrack_get_pwridx()
2454 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_need_lck()
2457 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck); in rtw_phy_pwrtrack_need_lck()
2458 if (delta_lck >= rtwdev->chip->lck_threshold) { in rtw_phy_pwrtrack_need_lck()
2459 dm_info->thermal_meter_lck = dm_info->thermal_avg[0]; in rtw_phy_pwrtrack_need_lck()
2468 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw_phy_pwrtrack_need_iqk()
2471 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k); in rtw_phy_pwrtrack_need_iqk()
2472 if (delta_iqk >= rtwdev->chip->iqk_threshold) { in rtw_phy_pwrtrack_need_iqk()
2473 dm_info->thermal_meter_k = dm_info->thermal_avg[0]; in rtw_phy_pwrtrack_need_iqk()
2483 struct rtw_path_div *path_div = &rtwdev->dm_path_div; in rtw_phy_set_tx_path_by_reg()
2485 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_set_tx_path_by_reg()
2487 if (tx_path_sel_1ss == path_div->current_tx_path) in rtw_phy_set_tx_path_by_reg()
2490 path_div->current_tx_path = tx_path_sel_1ss; in rtw_phy_set_tx_path_by_reg()
2493 chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx, in rtw_phy_set_tx_path_by_reg()
2499 struct rtw_path_div *path_div = &rtwdev->dm_path_div; in rtw_phy_tx_path_div_select()
2500 enum rtw_bb_path path = path_div->current_tx_path; in rtw_phy_tx_path_div_select()
2503 if (path_div->path_a_cnt) in rtw_phy_tx_path_div_select()
2504 rssi_a = path_div->path_a_sum / path_div->path_a_cnt; in rtw_phy_tx_path_div_select()
2507 if (path_div->path_b_cnt) in rtw_phy_tx_path_div_select()
2508 rssi_b = path_div->path_b_sum / path_div->path_b_cnt; in rtw_phy_tx_path_div_select()
2515 path_div->path_a_cnt = 0; in rtw_phy_tx_path_div_select()
2516 path_div->path_a_sum = 0; in rtw_phy_tx_path_div_select()
2517 path_div->path_b_cnt = 0; in rtw_phy_tx_path_div_select()
2518 path_div->path_b_sum = 0; in rtw_phy_tx_path_div_select()
2524 if (rtwdev->hal.antenna_rx != BB_PATH_AB) { in rtw_phy_tx_path_diversity_2ss()
2527 rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx); in rtw_phy_tx_path_diversity_2ss()
2530 if (rtwdev->sta_cnt == 0) { in rtw_phy_tx_path_diversity_2ss()
2540 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_tx_path_diversity()
2542 if (!chip->path_div_supported) in rtw_phy_tx_path_diversity()