Lines Matching refs:PWR_CMD_WRITE
46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
50 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
64 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
76 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
87 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
90 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
102 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
108 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
116 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
120 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
123 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
126 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
136 PWR_CMD_WRITE, BIT(5), BIT(5)}, \
140 PWR_CMD_WRITE, BIT(0), 0},
148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
152 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
161 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
164 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
175 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
178 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
184 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
187 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
208 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
211 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
222 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
225 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
231 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
234 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
237 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
252 PWR_CMD_WRITE, 0xFF, 0x20}, \
255 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
258 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
274 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
298 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
304 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
318 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
321 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
324 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
330 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
336 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
339 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
342 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
345 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
348 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},