Lines Matching refs:rtl_set_bbreg
121 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl8723be_phy_bb_config()
272 rtl_set_bbreg(hw, addr, MASKDWORD, data); in _rtl8723be_config_bb_reg()
1229 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl8723be_phy_set_bw_mode_callback()
1230 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl8723be_phy_set_bw_mode_callback()
1234 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl8723be_phy_set_bw_mode_callback()
1235 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl8723be_phy_set_bw_mode_callback()
1237 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, in rtl8723be_phy_set_bw_mode_callback()
1239 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl8723be_phy_set_bw_mode_callback()
1242 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl8723be_phy_set_bw_mode_callback()
1457 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1459 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1469 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_a_iqk()
1470 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_iqk()
1472 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_iqk()
1473 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1474 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1475 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1477 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); in _rtl8723be_phy_path_a_iqk()
1478 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); in _rtl8723be_phy_path_a_iqk()
1479 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_iqk()
1480 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_iqk()
1482 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl8723be_phy_path_a_iqk()
1484 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_iqk()
1487 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_iqk()
1488 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_iqk()
1493 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1530 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1533 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1542 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1545 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_a_rx_iqk()
1546 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_rx_iqk()
1549 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1550 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1551 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1552 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1554 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); in _rtl8723be_phy_path_a_rx_iqk()
1555 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1556 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1557 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1560 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl8723be_phy_path_a_rx_iqk()
1563 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1566 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_rx_iqk()
1567 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_rx_iqk()
1572 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1601 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); in _rtl8723be_phy_path_a_rx_iqk()
1605 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1617 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_rx_iqk()
1620 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1621 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1622 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1623 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1625 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1626 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); in _rtl8723be_phy_path_a_rx_iqk()
1627 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1628 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1631 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); in _rtl8723be_phy_path_a_rx_iqk()
1634 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1637 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_rx_iqk()
1638 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_rx_iqk()
1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1650 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1677 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_iqk()
1679 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); in _rtl8723be_phy_path_b_iqk()
1687 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_b_iqk()
1688 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_iqk()
1690 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_iqk()
1691 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1692 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1693 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1695 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); in _rtl8723be_phy_path_b_iqk()
1696 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_iqk()
1697 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_iqk()
1698 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_iqk()
1701 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl8723be_phy_path_b_iqk()
1704 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_iqk()
1707 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_iqk()
1708 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_iqk()
1713 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_iqk()
1750 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1752 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); in _rtl8723be_phy_path_b_rx_iqk()
1766 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_b_rx_iqk()
1767 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_rx_iqk()
1770 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1771 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1772 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1773 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1775 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); in _rtl8723be_phy_path_b_rx_iqk()
1776 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1777 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1778 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1781 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl8723be_phy_path_b_rx_iqk()
1783 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_rx_iqk()
1786 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_rx_iqk()
1787 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_rx_iqk()
1792 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1820 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp); in _rtl8723be_phy_path_b_rx_iqk()
1825 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1837 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_rx_iqk()
1840 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1841 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1842 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1843 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1845 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1846 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); in _rtl8723be_phy_path_b_rx_iqk()
1847 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1848 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1851 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); in _rtl8723be_phy_path_b_rx_iqk()
1853 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_rx_iqk()
1856 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_rx_iqk()
1857 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_rx_iqk()
1862 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1906 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1907 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), in _rtl8723be_phy_path_b_fill_iqk_matrix()
1913 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl8723be_phy_path_b_fill_iqk_matrix()
1915 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl8723be_phy_path_b_fill_iqk_matrix()
1917 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), in _rtl8723be_phy_path_b_fill_iqk_matrix()
1922 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1924 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl8723be_phy_path_b_fill_iqk_matrix()
2058 rtl_set_bbreg(hw, 0xa04, 0x0f000000, 0xf); in _rtl8723be_phy_iq_calibrate()
2059 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl8723be_phy_iq_calibrate()
2060 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl8723be_phy_iq_calibrate()
2061 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl8723be_phy_iq_calibrate()
2136 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl8723be_phy_iq_calibrate()
2147 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); in _rtl8723be_phy_iq_calibrate()
2150 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl8723be_phy_iq_calibrate()
2151 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_reg_c50); in _rtl8723be_phy_iq_calibrate()
2153 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, 0x50); in _rtl8723be_phy_iq_calibrate()
2154 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_reg_c58); in _rtl8723be_phy_iq_calibrate()
2156 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl8723be_phy_iq_calibrate()
2157 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl8723be_phy_iq_calibrate()
2244 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1); in _rtl8723be_phy_set_rfpath_switch()
2246 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2); in _rtl8723be_phy_set_rfpath_switch()
2386 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); in rtl8723be_phy_iq_calibrate()
2474 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); in rtl8723be_phy_set_io()
2479 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); in rtl8723be_phy_set_io()