Lines Matching +full:0 +full:x80800000
91 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl8723be_phy_mac_config()
106 regval | BIT(13) | BIT(0) | BIT(1)); in rtl8723be_phy_bb_config()
112 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl8723be_phy_bb_config()
113 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl8723be_phy_bb_config()
115 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723be_phy_bb_config()
120 crystalcap = crystalcap & 0x3F; in rtl8723be_phy_bb_config()
121 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl8723be_phy_bb_config()
140 u32 intf = (rtlhal->interface == INTF_USB ? BIT(1) : BIT(0)); in _rtl8723be_check_positive()
142 u8 board_type = ((rtlhal->board_type & BIT(4)) >> 4) << 0 | /* _GLNA */ in _rtl8723be_check_positive()
150 0 << 20 | /* interface 2/2 */ in _rtl8723be_check_positive()
151 0x04 << 16 | /* platform */ in _rtl8723be_check_positive()
156 u32 driver2 = rtlhal->type_glna << 0 | in _rtl8723be_check_positive()
162 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n", in _rtl8723be_check_positive()
165 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n", in _rtl8723be_check_positive()
169 "(Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf); in _rtl8723be_check_positive()
171 "(Board, Package) = (0x%X, 0x%X)\n", in _rtl8723be_check_positive()
177 if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != in _rtl8723be_check_positive()
178 (driver1 & 0x0000F000))) in _rtl8723be_check_positive()
180 if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != in _rtl8723be_check_positive()
181 (driver1 & 0x0F000000))) in _rtl8723be_check_positive()
187 cond1 &= 0x00FF0FFF; in _rtl8723be_check_positive()
188 driver1 &= 0x00FF0FFF; in _rtl8723be_check_positive()
191 u32 mask = 0; in _rtl8723be_check_positive()
193 if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ in _rtl8723be_check_positive()
196 if ((cond1 & BIT(0)) != 0) /*GLNA*/ in _rtl8723be_check_positive()
197 mask |= 0x000000FF; in _rtl8723be_check_positive()
198 if ((cond1 & BIT(1)) != 0) /*GPA*/ in _rtl8723be_check_positive()
199 mask |= 0x0000FF00; in _rtl8723be_check_positive()
200 if ((cond1 & BIT(2)) != 0) /*ALNA*/ in _rtl8723be_check_positive()
201 mask |= 0x00FF0000; in _rtl8723be_check_positive()
202 if ((cond1 & BIT(3)) != 0) /*APA*/ in _rtl8723be_check_positive()
203 mask |= 0xFF000000; in _rtl8723be_check_positive()
218 if (addr == 0xfe || addr == 0xffe) { in _rtl8723be_config_rf_reg()
231 u32 content = 0x1000; /*RF Content: radio_a_txt*/ in _rtl8723be_config_rf_radio_a()
232 u32 maskforphyset = (u32)(content & 0xE000); in _rtl8723be_config_rf_radio_a()
247 for (path = 0; path < TX_PWR_BY_RATE_NUM_RF; ++path) in _rtl8723be_phy_init_tx_power_by_rate()
248 for (txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum) in _rtl8723be_phy_init_tx_power_by_rate()
249 for (section = 0; in _rtl8723be_phy_init_tx_power_by_rate()
253 [band][path][txnum][section] = 0; in _rtl8723be_phy_init_tx_power_by_rate()
259 if (addr == 0xfe) { in _rtl8723be_config_bb_reg()
261 } else if (addr == 0xfd) { in _rtl8723be_config_bb_reg()
263 } else if (addr == 0xfc) { in _rtl8723be_config_bb_reg()
265 } else if (addr == 0xfb) { in _rtl8723be_config_bb_reg()
267 } else if (addr == 0xfa) { in _rtl8723be_config_bb_reg()
269 } else if (addr == 0xf9) { in _rtl8723be_config_bb_reg()
295 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value; in _rtl8723be_phy_set_txpower_by_rate_base()
326 u8 value = 0; in _rtl8723be_phy_get_txpower_by_rate_base()
331 return 0; in _rtl8723be_phy_get_txpower_by_rate_base()
337 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0]; in _rtl8723be_phy_get_txpower_by_rate_base()
367 u16 rawvalue = 0; in _rtl8723be_phy_store_txpower_by_rate_base()
368 u8 base = 0, path = 0; in _rtl8723be_phy_store_txpower_by_rate_base()
373 [BAND_ON_2_4G][path][RF_1TX][3] >> 24) & 0xFF; in _rtl8723be_phy_store_txpower_by_rate_base()
374 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); in _rtl8723be_phy_store_txpower_by_rate_base()
379 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) & 0xFF; in _rtl8723be_phy_store_txpower_by_rate_base()
380 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); in _rtl8723be_phy_store_txpower_by_rate_base()
387 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF; in _rtl8723be_phy_store_txpower_by_rate_base()
388 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); in _rtl8723be_phy_store_txpower_by_rate_base()
394 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF; in _rtl8723be_phy_store_txpower_by_rate_base()
395 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); in _rtl8723be_phy_store_txpower_by_rate_base()
401 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF; in _rtl8723be_phy_store_txpower_by_rate_base()
402 base = (rawvalue >> 4) * 10 + (rawvalue & 0xF); in _rtl8723be_phy_store_txpower_by_rate_base()
412 s8 i = 0; in _phy_convert_txpower_dbm_to_relative_value()
413 u8 temp_value = 0; in _phy_convert_txpower_dbm_to_relative_value()
414 u32 temp_data = 0; in _phy_convert_txpower_dbm_to_relative_value()
416 for (i = 3; i >= 0; --i) { in _phy_convert_txpower_dbm_to_relative_value()
419 temp_value = (u8)(*data >> (i * 8)) & 0xF; in _phy_convert_txpower_dbm_to_relative_value()
420 temp_value += ((u8)((*data >> (i*8 + 4)) & 0xF)) * 10; in _phy_convert_txpower_dbm_to_relative_value()
427 temp_value = (u8)(*data >> (i * 8)) & 0xFF; in _phy_convert_txpower_dbm_to_relative_value()
440 u8 base = 0, rfpath = RF90_PATH_A; in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
454 &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_1TX][0], in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
455 0, 3, base); in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
458 0, 3, base); in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
464 0, 3, base); in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
467 0, 3, base); in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
474 0, 3, base); in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
478 0, 3, base); in _rtl8723be_phy_convert_txpower_dbm_to_relative_value()
499 rtl_write_dword(rtlpriv, 0x948, 0x0); in _rtl8723be_phy_bb8723b_config_parafile()
501 if (rtlpriv->btcoexist.btc_info.single_ant_path == 0) in _rtl8723be_phy_bb8723b_config_parafile()
502 rtl_write_dword(rtlpriv, 0x948, 0x280); in _rtl8723be_phy_bb8723b_config_parafile()
504 rtl_write_dword(rtlpriv, 0x948, 0x0); in _rtl8723be_phy_bb8723b_config_parafile()
515 rtlphy->pwrgroup_cnt = 0; in _rtl8723be_phy_bb8723b_config_parafile()
532 0x200)); in _rtl8723be_phy_bb8723b_config_parafile()
544 int i = 0; in rtl8723be_phy_config_with_headerfile()
618 u8 index = 0; in _rtl8723be_get_rate_section_index()
622 index = 0; in _rtl8723be_get_rate_section_index()
646 index = 0; in _rtl8723be_get_rate_section_index()
667 regaddr &= 0xFFF; in _rtl8723be_get_rate_section_index()
668 if (regaddr >= 0xC20 && regaddr <= 0xC4C) in _rtl8723be_get_rate_section_index()
669 index = (u8)((regaddr - 0xC20) / 4); in _rtl8723be_get_rate_section_index()
670 else if (regaddr >= 0xE20 && regaddr <= 0xE4C) in _rtl8723be_get_rate_section_index()
671 index = (u8)((regaddr - 0xE20) / 4); in _rtl8723be_get_rate_section_index()
712 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; in _rtl8723be_phy_config_bb_with_pgheaderfile()
718 for (i = 0; i < phy_regarray_pg_len; i = i + 6) { in _rtl8723be_phy_config_bb_with_pgheaderfile()
726 if (v1 < 0xcdcdcdcd) { in _rtl8723be_phy_config_bb_with_pgheaderfile()
727 if (phy_regarray_table_pg[i] == 0xfe || in _rtl8723be_phy_config_bb_with_pgheaderfile()
728 phy_regarray_table_pg[i] == 0xffe) in _rtl8723be_phy_config_bb_with_pgheaderfile()
759 _rtl8723be_config_rf_radio_a(hw, 0x52, 0x7E4BD); in rtl8723be_phy_config_rf_with_headerfile()
777 rtlphy->default_initialgain[0] = in rtl8723be_phy_get_hw_reg_originalvalue()
787 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl8723be_phy_get_hw_reg_originalvalue()
788 rtlphy->default_initialgain[0], in rtl8723be_phy_get_hw_reg_originalvalue()
799 "Default framesync (0x%x) = 0x%x\n", in rtl8723be_phy_get_hw_reg_originalvalue()
806 u8 rate_section = 0; in _rtl8723be_phy_get_ratesection_intxpower_byrate()
829 rate_section = 0; in _rtl8723be_phy_get_ratesection_intxpower_byrate()
881 u8 shift = 0, rate_section, tx_num; in _rtl8723be_get_txpower_by_rate()
882 s8 tx_pwr_diff = 0; in _rtl8723be_get_txpower_by_rate()
902 shift = 0; in _rtl8723be_get_txpower_by_rate()
937 [rate_section] >> shift) & 0xff; in _rtl8723be_get_txpower_by_rate()
948 u8 txpower = 0; in _rtl8723be_get_txpower_index()
949 u8 power_diff_byrate = 0; in _rtl8723be_get_txpower_index()
952 index = 0; in _rtl8723be_get_txpower_index()
966 txpower += rtlefuse->txpwr_legacyhtdiff[0][TX_1S]; in _rtl8723be_get_txpower_index()
970 txpower += rtlefuse->txpwr_ht20diff[0][TX_1S]; in _rtl8723be_get_txpower_index()
972 txpower += rtlefuse->txpwr_ht20diff[0][TX_2S]; in _rtl8723be_get_txpower_index()
975 txpower += rtlefuse->txpwr_ht40diff[0][TX_1S]; in _rtl8723be_get_txpower_index()
977 txpower += rtlefuse->txpwr_ht40diff[0][TX_2S]; in _rtl8723be_get_txpower_index()
1135 for (i = 0; i < ARRAY_SIZE(cck_rates); i++) { in rtl8723be_phy_set_txpower_level()
1143 for (i = 0; i < ARRAY_SIZE(ofdm_rates); i++) { in rtl8723be_phy_set_txpower_level()
1151 for (i = 0; i < ARRAY_SIZE(ht_rates_1t); i++) { in rtl8723be_phy_set_txpower_level()
1217 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | in rtl8723be_phy_set_bw_mode_callback()
1229 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl8723be_phy_set_bw_mode_callback()
1230 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl8723be_phy_set_bw_mode_callback()
1234 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl8723be_phy_set_bw_mode_callback()
1235 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl8723be_phy_set_bw_mode_callback()
1239 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl8723be_phy_set_bw_mode_callback()
1240 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ in rtl8723be_phy_set_bw_mode_callback()
1242 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl8723be_phy_set_bw_mode_callback()
1282 u32 delay = 0; in rtl8723be_phy_sw_chnl_callback()
1296 if (delay > 0) in rtl8723be_phy_sw_chnl_callback()
1315 return 0; in rtl8723be_phy_sw_chnl()
1317 return 0; in rtl8723be_phy_sw_chnl()
1321 rtlphy->sw_chnl_stage = 0; in rtl8723be_phy_sw_chnl()
1322 rtlphy->sw_chnl_step = 0; in rtl8723be_phy_sw_chnl()
1353 precommoncmdcnt = 0; in _rtl8723be_phy_sw_chnl_step_by_step()
1357 0, 0, 0); in _rtl8723be_phy_sw_chnl_step_by_step()
1359 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl8723be_phy_sw_chnl_step_by_step()
1361 postcommoncmdcnt = 0; in _rtl8723be_phy_sw_chnl_step_by_step()
1365 0, 0, 0); in _rtl8723be_phy_sw_chnl_step_by_step()
1367 rfdependcmdcnt = 0; in _rtl8723be_phy_sw_chnl_step_by_step()
1379 CMDID_END, 0, 0, 0); in _rtl8723be_phy_sw_chnl_step_by_step()
1383 case 0: in _rtl8723be_phy_sw_chnl_step_by_step()
1403 (*step) = 0; in _rtl8723be_phy_sw_chnl_step_by_step()
1425 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl8723be_phy_sw_chnl_step_by_step()
1428 0xfffffc00) | currentcmd->para2); in _rtl8723be_phy_sw_chnl_step_by_step()
1454 u8 result = 0x00; in _rtl8723be_phy_path_a_iqk()
1457 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1459 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1461 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl8723be_phy_path_a_iqk()
1462 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x20000); in _rtl8723be_phy_path_a_iqk()
1463 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0003f); in _rtl8723be_phy_path_a_iqk()
1464 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xc7f87); in _rtl8723be_phy_path_a_iqk()
1469 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_a_iqk()
1470 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_iqk()
1472 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_iqk()
1473 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1474 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1475 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_iqk()
1477 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); in _rtl8723be_phy_path_a_iqk()
1478 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); in _rtl8723be_phy_path_a_iqk()
1479 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_iqk()
1480 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_iqk()
1482 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl8723be_phy_path_a_iqk()
1484 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_iqk()
1487 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_iqk()
1488 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_iqk()
1493 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_iqk()
1496 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl8723be_phy_path_a_iqk()
1497 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl8723be_phy_path_a_iqk()
1498 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl8723be_phy_path_a_iqk()
1501 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl8723be_phy_path_a_iqk()
1502 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl8723be_phy_path_a_iqk()
1503 result |= 0x01; in _rtl8723be_phy_path_a_iqk()
1508 tmp = (reg_e9c & 0x03FF0000) >> 16; in _rtl8723be_phy_path_a_iqk()
1509 if ((tmp & 0x200) > 0) in _rtl8723be_phy_path_a_iqk()
1510 tmp = 0x400 - tmp; in _rtl8723be_phy_path_a_iqk()
1513 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) && in _rtl8723be_phy_path_a_iqk()
1514 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) && in _rtl8723be_phy_path_a_iqk()
1515 (tmp < 0xf)) in _rtl8723be_phy_path_a_iqk()
1516 result |= 0x01; in _rtl8723be_phy_path_a_iqk()
1527 u8 result = 0x00; in _rtl8723be_phy_path_a_rx_iqk()
1530 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1533 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1537 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1); in _rtl8723be_phy_path_a_rx_iqk()
1538 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl8723be_phy_path_a_rx_iqk()
1539 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); in _rtl8723be_phy_path_a_rx_iqk()
1541 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7fb7); in _rtl8723be_phy_path_a_rx_iqk()
1542 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1545 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_a_rx_iqk()
1546 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_rx_iqk()
1549 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1550 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1551 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1552 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1554 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); in _rtl8723be_phy_path_a_rx_iqk()
1555 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1556 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1557 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1560 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl8723be_phy_path_a_rx_iqk()
1563 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1566 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_rx_iqk()
1567 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_rx_iqk()
1572 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1580 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl8723be_phy_path_a_rx_iqk()
1581 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl8723be_phy_path_a_rx_iqk()
1582 result |= 0x01; in _rtl8723be_phy_path_a_rx_iqk()
1587 tmp = (reg_e9c & 0x03FF0000) >> 16; in _rtl8723be_phy_path_a_rx_iqk()
1588 if ((tmp & 0x200) > 0) in _rtl8723be_phy_path_a_rx_iqk()
1589 tmp = 0x400 - tmp; in _rtl8723be_phy_path_a_rx_iqk()
1592 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) && in _rtl8723be_phy_path_a_rx_iqk()
1593 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) && in _rtl8723be_phy_path_a_rx_iqk()
1594 (tmp < 0xf)) in _rtl8723be_phy_path_a_rx_iqk()
1595 result |= 0x01; in _rtl8723be_phy_path_a_rx_iqk()
1599 u32tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | in _rtl8723be_phy_path_a_rx_iqk()
1600 ((reg_e9c & 0x3FF0000) >> 16); in _rtl8723be_phy_path_a_rx_iqk()
1605 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1606 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1); in _rtl8723be_phy_path_a_rx_iqk()
1607 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl8723be_phy_path_a_rx_iqk()
1608 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); in _rtl8723be_phy_path_a_rx_iqk()
1610 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77); in _rtl8723be_phy_path_a_rx_iqk()
1613 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0xf80); in _rtl8723be_phy_path_a_rx_iqk()
1614 rtl_set_rfreg(hw, RF90_PATH_A, 0x55, RFREG_OFFSET_MASK, 0x4021f); in _rtl8723be_phy_path_a_rx_iqk()
1617 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_a_rx_iqk()
1620 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1621 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1622 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1623 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_a_rx_iqk()
1625 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1626 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); in _rtl8723be_phy_path_a_rx_iqk()
1627 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_a_rx_iqk()
1628 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_a_rx_iqk()
1631 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); in _rtl8723be_phy_path_a_rx_iqk()
1634 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_a_rx_iqk()
1637 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_a_rx_iqk()
1638 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_a_rx_iqk()
1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1650 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_a_rx_iqk()
1651 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x780); in _rtl8723be_phy_path_a_rx_iqk()
1654 tmp = (reg_eac & 0x03FF0000) >> 16; in _rtl8723be_phy_path_a_rx_iqk()
1655 if ((tmp & 0x200) > 0) in _rtl8723be_phy_path_a_rx_iqk()
1656 tmp = 0x400 - tmp; in _rtl8723be_phy_path_a_rx_iqk()
1659 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl8723be_phy_path_a_rx_iqk()
1660 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl8723be_phy_path_a_rx_iqk()
1661 result |= 0x02; in _rtl8723be_phy_path_a_rx_iqk()
1663 (((reg_ea4 & 0x03FF0000) >> 16) < 0x110) && in _rtl8723be_phy_path_a_rx_iqk()
1664 (((reg_ea4 & 0x03FF0000) >> 16) > 0xf0) && in _rtl8723be_phy_path_a_rx_iqk()
1665 (tmp < 0xf)) in _rtl8723be_phy_path_a_rx_iqk()
1666 result |= 0x02; in _rtl8723be_phy_path_a_rx_iqk()
1674 u8 result = 0x00; in _rtl8723be_phy_path_b_iqk()
1677 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_iqk()
1679 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); in _rtl8723be_phy_path_b_iqk()
1682 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020); in _rtl8723be_phy_path_b_iqk()
1683 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x40fc1); in _rtl8723be_phy_path_b_iqk()
1687 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_b_iqk()
1688 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_iqk()
1690 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_iqk()
1691 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1692 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1693 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_iqk()
1695 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea); in _rtl8723be_phy_path_b_iqk()
1696 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_iqk()
1697 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_iqk()
1698 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_iqk()
1701 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl8723be_phy_path_b_iqk()
1704 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_iqk()
1707 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_iqk()
1708 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_iqk()
1713 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_iqk()
1721 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl8723be_phy_path_b_iqk()
1722 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl8723be_phy_path_b_iqk()
1723 result |= 0x01; in _rtl8723be_phy_path_b_iqk()
1728 tmp = (reg_e9c & 0x03FF0000) >> 16; in _rtl8723be_phy_path_b_iqk()
1729 if ((tmp & 0x200) > 0) in _rtl8723be_phy_path_b_iqk()
1730 tmp = 0x400 - tmp; in _rtl8723be_phy_path_b_iqk()
1733 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) && in _rtl8723be_phy_path_b_iqk()
1734 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) && in _rtl8723be_phy_path_b_iqk()
1735 (tmp < 0xf)) in _rtl8723be_phy_path_b_iqk()
1736 result |= 0x01; in _rtl8723be_phy_path_b_iqk()
1747 u8 result = 0x00; in _rtl8723be_phy_path_b_rx_iqk()
1750 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1752 rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280); in _rtl8723be_phy_path_b_rx_iqk()
1756 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl8723be_phy_path_b_rx_iqk()
1757 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl8723be_phy_path_b_rx_iqk()
1758 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); in _rtl8723be_phy_path_b_rx_iqk()
1759 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ff7); in _rtl8723be_phy_path_b_rx_iqk()
1762 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020); in _rtl8723be_phy_path_b_rx_iqk()
1763 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fed); in _rtl8723be_phy_path_b_rx_iqk()
1766 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl8723be_phy_path_b_rx_iqk()
1767 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_rx_iqk()
1770 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1771 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1772 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1773 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1775 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0); in _rtl8723be_phy_path_b_rx_iqk()
1776 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1777 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1778 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1781 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl8723be_phy_path_b_rx_iqk()
1783 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_rx_iqk()
1786 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_rx_iqk()
1787 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_rx_iqk()
1792 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1799 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl8723be_phy_path_b_rx_iqk()
1800 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl8723be_phy_path_b_rx_iqk()
1801 result |= 0x01; in _rtl8723be_phy_path_b_rx_iqk()
1806 tmp = (reg_e9c & 0x03FF0000) >> 16; in _rtl8723be_phy_path_b_rx_iqk()
1807 if ((tmp & 0x200) > 0) in _rtl8723be_phy_path_b_rx_iqk()
1808 tmp = 0x400 - tmp; in _rtl8723be_phy_path_b_rx_iqk()
1811 (((reg_e94 & 0x03FF0000) >> 16) < 0x110) && in _rtl8723be_phy_path_b_rx_iqk()
1812 (((reg_e94 & 0x03FF0000) >> 16) > 0xf0) && in _rtl8723be_phy_path_b_rx_iqk()
1813 (tmp < 0xf)) in _rtl8723be_phy_path_b_rx_iqk()
1814 result |= 0x01; in _rtl8723be_phy_path_b_rx_iqk()
1818 u32tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | in _rtl8723be_phy_path_b_rx_iqk()
1819 ((reg_e9c & 0x3FF0000) >> 16); in _rtl8723be_phy_path_b_rx_iqk()
1825 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1826 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x1); in _rtl8723be_phy_path_b_rx_iqk()
1827 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl8723be_phy_path_b_rx_iqk()
1828 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0001f); in _rtl8723be_phy_path_b_rx_iqk()
1829 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7d77); in _rtl8723be_phy_path_b_rx_iqk()
1830 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, 0x80000, 0x0); in _rtl8723be_phy_path_b_rx_iqk()
1833 rtl_set_rfreg(hw, RF90_PATH_A, 0xed, RFREG_OFFSET_MASK, 0x00020); in _rtl8723be_phy_path_b_rx_iqk()
1834 rtl_set_rfreg(hw, RF90_PATH_A, 0x43, RFREG_OFFSET_MASK, 0x60fbd); in _rtl8723be_phy_path_b_rx_iqk()
1837 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl8723be_phy_path_b_rx_iqk()
1840 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1841 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1842 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1843 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl8723be_phy_path_b_rx_iqk()
1845 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1846 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f); in _rtl8723be_phy_path_b_rx_iqk()
1847 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl8723be_phy_path_b_rx_iqk()
1848 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000); in _rtl8723be_phy_path_b_rx_iqk()
1851 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1); in _rtl8723be_phy_path_b_rx_iqk()
1853 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl8723be_phy_path_b_rx_iqk()
1856 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl8723be_phy_path_b_rx_iqk()
1857 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl8723be_phy_path_b_rx_iqk()
1862 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl8723be_phy_path_b_rx_iqk()
1868 tmp = (reg_eac & 0x03FF0000) >> 16; in _rtl8723be_phy_path_b_rx_iqk()
1869 if ((tmp & 0x200) > 0) in _rtl8723be_phy_path_b_rx_iqk()
1870 tmp = 0x400 - tmp; in _rtl8723be_phy_path_b_rx_iqk()
1874 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl8723be_phy_path_b_rx_iqk()
1875 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl8723be_phy_path_b_rx_iqk()
1876 result |= 0x02; in _rtl8723be_phy_path_b_rx_iqk()
1878 (((reg_ea4 & 0x03FF0000) >> 16) < 0x110) && in _rtl8723be_phy_path_b_rx_iqk()
1879 (((reg_ea4 & 0x03FF0000) >> 16) > 0xf0) && in _rtl8723be_phy_path_b_rx_iqk()
1880 (tmp < 0xf)) in _rtl8723be_phy_path_b_rx_iqk()
1881 result |= 0x02; in _rtl8723be_phy_path_b_rx_iqk()
1897 if (final_candidate == 0xFF) { in _rtl8723be_phy_path_b_fill_iqk_matrix()
1901 MASKDWORD) >> 22) & 0x3FF; in _rtl8723be_phy_path_b_fill_iqk_matrix()
1903 if ((x & 0x00000200) != 0) in _rtl8723be_phy_path_b_fill_iqk_matrix()
1904 x = x | 0xFFFFFC00; in _rtl8723be_phy_path_b_fill_iqk_matrix()
1906 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1908 ((x * oldval_1 >> 7) & 0x1)); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1910 if ((y & 0x00000200) != 0) in _rtl8723be_phy_path_b_fill_iqk_matrix()
1911 y = y | 0xFFFFFC00; in _rtl8723be_phy_path_b_fill_iqk_matrix()
1913 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl8723be_phy_path_b_fill_iqk_matrix()
1914 ((tx1_c & 0x3C0) >> 6)); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1915 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl8723be_phy_path_b_fill_iqk_matrix()
1916 (tx1_c & 0x3F)); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1918 ((y * oldval_1 >> 7) & 0x1)); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1922 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1923 reg = result[final_candidate][7] & 0x3F; in _rtl8723be_phy_path_b_fill_iqk_matrix()
1924 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl8723be_phy_path_b_fill_iqk_matrix()
1925 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl8723be_phy_path_b_fill_iqk_matrix()
1926 /* rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); */ in _rtl8723be_phy_path_b_fill_iqk_matrix()
1933 u32 i, j, diff, simularity_bitmap, bound = 0; in _rtl8723be_phy_simularity_compare()
1935 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ in _rtl8723be_phy_simularity_compare()
1937 s32 tmp1 = 0, tmp2 = 0; in _rtl8723be_phy_simularity_compare()
1941 simularity_bitmap = 0; in _rtl8723be_phy_simularity_compare()
1943 for (i = 0; i < bound; i++) { in _rtl8723be_phy_simularity_compare()
1945 if ((result[c1][i] & 0x00000200) != 0) in _rtl8723be_phy_simularity_compare()
1946 tmp1 = result[c1][i] | 0xFFFFFC00; in _rtl8723be_phy_simularity_compare()
1950 if ((result[c2][i] & 0x00000200) != 0) in _rtl8723be_phy_simularity_compare()
1951 tmp2 = result[c2][i] | 0xFFFFFC00; in _rtl8723be_phy_simularity_compare()
1963 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl8723be_phy_simularity_compare()
1965 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl8723be_phy_simularity_compare()
1974 if (simularity_bitmap == 0) { in _rtl8723be_phy_simularity_compare()
1975 for (i = 0; i < (bound / 4); i++) { in _rtl8723be_phy_simularity_compare()
1976 if (final_candidate[i] != 0xFF) { in _rtl8723be_phy_simularity_compare()
1985 if (!(simularity_bitmap & 0x03)) { /* path A TX OK */ in _rtl8723be_phy_simularity_compare()
1986 for (i = 0; i < 2; i++) in _rtl8723be_phy_simularity_compare()
1989 if (!(simularity_bitmap & 0x0c)) { /* path A RX OK */ in _rtl8723be_phy_simularity_compare()
1993 if (!(simularity_bitmap & 0x30)) { /* path B TX OK */ in _rtl8723be_phy_simularity_compare()
1997 if (!(simularity_bitmap & 0xc0)) { /* path B RX OK */ in _rtl8723be_phy_simularity_compare()
2013 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl8723be_phy_iq_calibrate()
2014 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl8723be_phy_iq_calibrate()
2015 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl8723be_phy_iq_calibrate()
2016 0xed8, 0xedc, 0xee0, 0xeec in _rtl8723be_phy_iq_calibrate()
2020 0x522, 0x550, 0x551, 0x040 in _rtl8723be_phy_iq_calibrate()
2024 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, in _rtl8723be_phy_iq_calibrate()
2025 0x870, 0x860, in _rtl8723be_phy_iq_calibrate()
2026 0x864, 0xa04 in _rtl8723be_phy_iq_calibrate()
2034 tmp_reg_c50 = rtl_get_bbreg(hw, 0xc50, MASKBYTE0); in _rtl8723be_phy_iq_calibrate()
2035 tmp_reg_c58 = rtl_get_bbreg(hw, 0xc58, MASKBYTE0); in _rtl8723be_phy_iq_calibrate()
2037 if (t == 0) { in _rtl8723be_phy_iq_calibrate()
2047 if (t == 0) { in _rtl8723be_phy_iq_calibrate()
2053 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); in _rtl8723be_phy_iq_calibrate()
2058 rtl_set_bbreg(hw, 0xa04, 0x0f000000, 0xf); in _rtl8723be_phy_iq_calibrate()
2059 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl8723be_phy_iq_calibrate()
2060 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl8723be_phy_iq_calibrate()
2061 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl8723be_phy_iq_calibrate()
2064 for (i = 0; i < retrycount; i++) { in _rtl8723be_phy_iq_calibrate()
2066 if (patha_ok == 0x01) { in _rtl8723be_phy_iq_calibrate()
2069 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2070 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2071 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2072 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2080 for (i = 0; i < retrycount; i++) { in _rtl8723be_phy_iq_calibrate()
2082 if (patha_ok == 0x03) { in _rtl8723be_phy_iq_calibrate()
2085 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2086 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2087 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl8723be_phy_iq_calibrate()
2088 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2095 if (0x00 == patha_ok) in _rtl8723be_phy_iq_calibrate()
2100 for (i = 0; i < retrycount; i++) { in _rtl8723be_phy_iq_calibrate()
2102 if (pathb_ok == 0x01) { in _rtl8723be_phy_iq_calibrate()
2105 result[t][4] = (rtl_get_bbreg(hw, 0xe94, in _rtl8723be_phy_iq_calibrate()
2107 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2108 result[t][5] = (rtl_get_bbreg(hw, 0xe9c, in _rtl8723be_phy_iq_calibrate()
2110 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2117 for (i = 0; i < retrycount; i++) { in _rtl8723be_phy_iq_calibrate()
2119 if (pathb_ok == 0x03) { in _rtl8723be_phy_iq_calibrate()
2122 result[t][6] = (rtl_get_bbreg(hw, 0xea4, in _rtl8723be_phy_iq_calibrate()
2124 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2125 result[t][7] = (rtl_get_bbreg(hw, 0xeac, in _rtl8723be_phy_iq_calibrate()
2127 0x3FF0000) >> 16; in _rtl8723be_phy_iq_calibrate()
2136 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl8723be_phy_iq_calibrate()
2138 if (t != 0) { in _rtl8723be_phy_iq_calibrate()
2147 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); in _rtl8723be_phy_iq_calibrate()
2148 /*rtl_set_rfreg(hw, RF90_PATH_B, 0xb0, 0xfffff, path_sel_rf);*/ in _rtl8723be_phy_iq_calibrate()
2150 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl8723be_phy_iq_calibrate()
2151 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_reg_c50); in _rtl8723be_phy_iq_calibrate()
2153 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, 0x50); in _rtl8723be_phy_iq_calibrate()
2154 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_reg_c58); in _rtl8723be_phy_iq_calibrate()
2156 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl8723be_phy_iq_calibrate()
2157 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl8723be_phy_iq_calibrate()
2182 return 0; in _get_right_chnl_place_for_iqk()
2188 u32 rf_a_mode = 0, rf_b_mode = 0; in _rtl8723be_phy_lc_calibrate()
2191 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl8723be_phy_lc_calibrate()
2193 if ((tmpreg & 0x70) != 0) in _rtl8723be_phy_lc_calibrate()
2194 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl8723be_phy_lc_calibrate()
2196 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl8723be_phy_lc_calibrate()
2198 if ((tmpreg & 0x70) != 0) { in _rtl8723be_phy_lc_calibrate()
2199 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl8723be_phy_lc_calibrate()
2202 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, in _rtl8723be_phy_lc_calibrate()
2205 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl8723be_phy_lc_calibrate()
2206 (rf_a_mode & 0x8FFFF) | 0x10000); in _rtl8723be_phy_lc_calibrate()
2209 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl8723be_phy_lc_calibrate()
2210 (rf_b_mode & 0x8FFFF) | 0x10000); in _rtl8723be_phy_lc_calibrate()
2212 rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl8723be_phy_lc_calibrate()
2214 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdfbe0); in _rtl8723be_phy_lc_calibrate()
2215 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, 0x8c0a); in _rtl8723be_phy_lc_calibrate()
2222 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdffe0); in _rtl8723be_phy_lc_calibrate()
2224 if ((tmpreg & 0x70) != 0) { in _rtl8723be_phy_lc_calibrate()
2225 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl8723be_phy_lc_calibrate()
2226 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl8723be_phy_lc_calibrate()
2229 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, in _rtl8723be_phy_lc_calibrate()
2232 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl8723be_phy_lc_calibrate()
2244 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1); in _rtl8723be_phy_set_rfpath_switch()
2246 rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2); in _rtl8723be_phy_set_rfpath_switch()
2260 long reg_tmp = 0; in rtl8723be_phy_iq_calibrate()
2273 u32 path_sel_bb = 0; /* path_sel_rf = 0 */ in rtl8723be_phy_iq_calibrate()
2288 path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD); in rtl8723be_phy_iq_calibrate()
2289 /* path_sel_rf = rtl_get_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff); */ in rtl8723be_phy_iq_calibrate()
2291 for (i = 0; i < 8; i++) { in rtl8723be_phy_iq_calibrate()
2292 result[0][i] = 0; in rtl8723be_phy_iq_calibrate()
2293 result[1][i] = 0; in rtl8723be_phy_iq_calibrate()
2294 result[2][i] = 0; in rtl8723be_phy_iq_calibrate()
2295 result[3][i] = 0; in rtl8723be_phy_iq_calibrate()
2297 final_candidate = 0xff; in rtl8723be_phy_iq_calibrate()
2303 for (i = 0; i < 3; i++) { in rtl8723be_phy_iq_calibrate()
2308 0, 1); in rtl8723be_phy_iq_calibrate()
2310 final_candidate = 0; in rtl8723be_phy_iq_calibrate()
2317 0, 2); in rtl8723be_phy_iq_calibrate()
2319 final_candidate = 0; in rtl8723be_phy_iq_calibrate()
2328 for (i = 0; i < 8; i++) in rtl8723be_phy_iq_calibrate()
2331 if (reg_tmp != 0) in rtl8723be_phy_iq_calibrate()
2334 final_candidate = 0xFF; in rtl8723be_phy_iq_calibrate()
2338 for (i = 0; i < 4; i++) { in rtl8723be_phy_iq_calibrate()
2339 reg_e94 = result[i][0]; in rtl8723be_phy_iq_calibrate()
2346 if (final_candidate != 0xff) { in rtl8723be_phy_iq_calibrate()
2347 reg_e94 = result[final_candidate][0]; in rtl8723be_phy_iq_calibrate()
2360 rtlphy->reg_e94 = 0x100; in rtl8723be_phy_iq_calibrate()
2361 rtlphy->reg_eb4 = 0x100; in rtl8723be_phy_iq_calibrate()
2362 rtlphy->reg_e9c = 0x0; in rtl8723be_phy_iq_calibrate()
2363 rtlphy->reg_ebc = 0x0; in rtl8723be_phy_iq_calibrate()
2365 if (reg_e94 != 0) in rtl8723be_phy_iq_calibrate()
2368 (reg_ea4 == 0)); in rtl8723be_phy_iq_calibrate()
2369 if (reg_eb4 != 0) in rtl8723be_phy_iq_calibrate()
2372 (reg_ec4 == 0)); in rtl8723be_phy_iq_calibrate()
2377 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl8723be_phy_iq_calibrate()
2378 rtlphy->iqk_matrix[idx].value[0][i] = in rtl8723be_phy_iq_calibrate()
2386 rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb); in rtl8723be_phy_iq_calibrate()
2387 /* rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, 0xfffff, path_sel_rf); */ in rtl8723be_phy_iq_calibrate()
2400 u32 timeout = 2000, timecount = 0; in rtl8723be_phy_lc_calibrate()
2474 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); in rtl8723be_phy_set_io()
2478 dm_digtable->cur_igvalue = 0x17; in rtl8723be_phy_set_io()
2479 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); in rtl8723be_phy_set_io()
2496 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl8723be_phy_set_rf_on()
2497 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl8723be_phy_set_rf_on()
2498 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl8723be_phy_set_rf_on()
2499 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl8723be_phy_set_rf_on()
2500 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl8723be_phy_set_rf_on()
2507 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl8723be_phy_set_rf_sleep()
2508 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl8723be_phy_set_rf_sleep()
2509 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl8723be_phy_set_rf_sleep()
2510 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl8723be_phy_set_rf_sleep()
2529 u32 initializecount = 0; in _rtl8723be_phy_set_rf_power_state()
2553 for (queue_id = 0, i = 0; in _rtl8723be_phy_set_rf_power_state()
2561 skb_queue_len(&ring->queue) == 0) { in _rtl8723be_phy_set_rf_power_state()
2602 for (queue_id = 0, i = 0; in _rtl8723be_phy_set_rf_power_state()
2605 if (skb_queue_len(&ring->queue) == 0) { in _rtl8723be_phy_set_rf_power_state()