Lines Matching refs:PWR_CMD_WRITE
46 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0},\
52 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
55 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
58 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0},\
61 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},\
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},\
75 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
84 PWR_BASEADDR_MAC, PWR_CMD_WRITE, \
90 PWR_CMD_WRITE, \
95 PWR_CMD_WRITE, BIT(3)|BIT(4), \
100 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
112 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0},\
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
131 PWR_CMD_WRITE, BIT(2), BIT(2)}, \
135 PWR_CMD_WRITE, BIT(0), BIT(0)}, \
148 PWR_CMD_WRITE, BIT(0), 0}, \
156 PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
160 PWR_CMD_WRITE, 0xFF, 0},
167 PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
170 PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
177 PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
185 PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
188 PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
208 PWR_CMD_WRITE, BIT(0), 0},\
214 PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
217 PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
220 PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
224 PWR_CMD_WRITE, BIT(5), BIT(5)},\
231 PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
234 PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
237 PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
244 PWR_CMD_WRITE, BIT(4), 0}, \
252 PWR_CMD_WRITE, BIT(6)|BIT(7), 0},\
256 PWR_CMD_WRITE, BIT(1), BIT(1)},\
260 PWR_CMD_WRITE, 0xFF, 0xFF},\
264 PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)},\
267 PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/