Lines Matching refs:rtl_write_dword
73 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); in rtl92se_set_hw_reg()
101 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]); in rtl92se_set_hw_reg()
285 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); in rtl92se_set_hw_reg()
695 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
696 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
699 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
700 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
701 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
702 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
703 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
704 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
705 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
706 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
707 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
761 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | in _rtl92se_macconfig_after_fwdownload()
765 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); in _rtl92se_macconfig_after_fwdownload()
811 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0); in _rtl92se_macconfig_after_fwdownload()
827 rtl_write_dword(rtlpriv, DARFRC, 0x04010000); in _rtl92se_macconfig_after_fwdownload()
828 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605); in _rtl92se_macconfig_after_fwdownload()
829 rtl_write_dword(rtlpriv, RARFRC, 0x04010000); in _rtl92se_macconfig_after_fwdownload()
830 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605); in _rtl92se_macconfig_after_fwdownload()
896 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr); in _rtl92se_hw_configure()
990 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); in rtl92se_hw_init()
994 rtl_write_dword(rtlpriv, CMDR, 0x37FC); in rtl92se_hw_init()
1061 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF); in rtl92se_hw_init()
1071 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT); in rtl92se_hw_init()
1075 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); in rtl92se_hw_init()
1077 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); in rtl92se_hw_init()
1079 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); in rtl92se_hw_init()
1097 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); in rtl92se_hw_init()
1179 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); in _rtl92se_set_media_status()
1180 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); in _rtl92se_set_media_status()
1212 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f); in rtl92se_set_qos()
1218 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322); in rtl92se_set_qos()
1221 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222); in rtl92se_set_qos()
1234 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); in rtl92se_enable_interrupt()
1236 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); in rtl92se_enable_interrupt()
1250 rtl_write_dword(rtlpriv, INTA_MASK, 0); in rtl92se_disable_interrupt()
1251 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0); in rtl92se_disable_interrupt()
1545 rtl_write_dword(rtlpriv, ISR, intvec->inta); in rtl92se_interrupt_recognized()
1548 rtl_write_dword(rtlpriv, ISR + 4, intvec->intb); in rtl92se_interrupt_recognized()
2088 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value); in rtl92se_update_hal_rate_table()
2251 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap); in rtl92se_update_hal_rate_mask()
2252 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); in rtl92se_update_hal_rate_mask()