Lines Matching +full:mlt +full:- +full:3
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
27 *((u32 *) (val)) = rtlpci->receive_config; in rtl92se_get_hw_reg()
31 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; in rtl92se_get_hw_reg()
35 *((bool *) (val)) = ppsc->fw_current_inpsmode; in rtl92se_get_hw_reg()
51 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; in rtl92se_get_hw_reg()
81 if (rtlhal->version == VERSION_8192S_ACUT) in rtl92se_set_hw_reg()
120 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
129 reg_tmp = (mac->cur_40_prime_sc) << 5; in rtl92se_set_hw_reg()
142 if (rtlpriv->sec.pairwise_enc_algorithm == in rtl92se_set_hw_reg()
153 mac->min_space_cfg = in rtl92se_set_hw_reg()
154 ((mac->min_space_cfg & 0xf8) | in rtl92se_set_hw_reg()
161 mac->min_space_cfg); in rtl92se_set_hw_reg()
164 mac->min_space_cfg); in rtl92se_set_hw_reg()
172 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; in rtl92se_set_hw_reg()
173 mac->min_space_cfg |= (density_to_set << 3); in rtl92se_set_hw_reg()
177 mac->min_space_cfg); in rtl92se_set_hw_reg()
180 mac->min_space_cfg); in rtl92se_set_hw_reg()
194 if (factor_toset <= 3) { in rtl92se_set_hw_reg()
228 if (rtlpci->acm_method != EACMWAY2_SW) in rtl92se_set_hw_reg()
229 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
237 mac->ac[0].aifs)); in rtl92se_set_hw_reg()
238 u8 acm = p_aci_aifsn->f.acm; in rtl92se_set_hw_reg()
241 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? in rtl92se_set_hw_reg()
286 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92se_set_hw_reg()
301 rtlefuse->efuse_usedbytes = *((u16 *) val); in rtl92se_set_hw_reg()
305 rtlefuse->efuse_usedpercentage = *val; in rtl92se_set_hw_reg()
322 ppsc->fw_current_inpsmode = *((bool *) val); in rtl92se_set_hw_reg()
355 rtlpriv->dm.current_mrc_switch = bmrc_toset; in rtl92se_set_hw_reg()
372 rtlpriv->dm.current_mrc_switch = bmrc_toset; in rtl92se_set_hw_reg()
385 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
388 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
390 &ppsc->fwctrl_psmode); in rtl92se_set_hw_reg()
392 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in rtl92se_set_hw_reg()
398 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in rtl92se_set_hw_reg()
400 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in rtl92se_set_hw_reg()
403 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92se_set_hw_reg()
422 rtlpriv->sec.pairwise_enc_algorithm, in rtl92se_enable_hw_security_config()
423 rtlpriv->sec.group_enc_algorithm); in rtl92se_enable_hw_security_config()
425 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { in rtl92se_enable_hw_security_config()
433 if (rtlpriv->sec.use_defaultkey) { in rtl92se_enable_hw_security_config()
438 rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", in rtl92se_enable_hw_security_config()
441 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); in rtl92se_enable_hw_security_config()
466 waitcount--; in _rtl92se_halset_sysclk()
539 if (rtlpci->first_init) { in _rtl92se_macconfig_before_fwdownload()
566 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */ in _rtl92se_macconfig_before_fwdownload()
580 tmpu1b &= ~(BIT(3)); in _rtl92se_macconfig_before_fwdownload()
687 if (ppsc->support_aspm && !ppsc->support_backdoor) in _rtl92se_macconfig_before_fwdownload()
695 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
696 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
699 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
700 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
701 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
702 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
703 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
704 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
705 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
706 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
707 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma); in _rtl92se_macconfig_before_fwdownload()
719 } while (pollingcnt--); in _rtl92se_macconfig_before_fwdownload()
732 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) || in _rtl92se_macconfig_before_fwdownload()
733 (ppsc->rfoff_reason == 0)) { in _rtl92se_macconfig_before_fwdownload()
734 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; in _rtl92se_macconfig_before_fwdownload()
752 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */ in _rtl92se_macconfig_after_fwdownload()
754 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */ in _rtl92se_macconfig_after_fwdownload()
765 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); in _rtl92se_macconfig_after_fwdownload()
767 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */ in _rtl92se_macconfig_after_fwdownload()
769 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */ in _rtl92se_macconfig_after_fwdownload()
782 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */ in _rtl92se_macconfig_after_fwdownload()
786 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */ in _rtl92se_macconfig_after_fwdownload()
791 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */ in _rtl92se_macconfig_after_fwdownload()
797 * Disable RRSR for CCK rate in A-Cut */ in _rtl92se_macconfig_after_fwdownload()
799 if (rtlhal->version == VERSION_8192S_ACUT) in _rtl92se_macconfig_after_fwdownload()
801 else if (rtlhal->version == VERSION_8192S_BCUT) in _rtl92se_macconfig_after_fwdownload()
806 /* A-Cut IC do not support CCK rate. We forbid ARFR to */ in _rtl92se_macconfig_after_fwdownload()
809 /*Disable RRSR for CCK rate in A-Cut */ in _rtl92se_macconfig_after_fwdownload()
810 if (rtlhal->version == VERSION_8192S_ACUT) in _rtl92se_macconfig_after_fwdownload()
817 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */ in _rtl92se_macconfig_after_fwdownload()
832 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */ in _rtl92se_macconfig_after_fwdownload()
836 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */ in _rtl92se_macconfig_after_fwdownload()
839 /* CF-END Threshold */ in _rtl92se_macconfig_after_fwdownload()
846 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */ in _rtl92se_macconfig_after_fwdownload()
847 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */ in _rtl92se_macconfig_after_fwdownload()
848 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */ in _rtl92se_macconfig_after_fwdownload()
849 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */ in _rtl92se_macconfig_after_fwdownload()
850 /* 13. Test mode and Debug Control Register (Offset: 0x0310 - 0x034F) */ in _rtl92se_macconfig_after_fwdownload()
864 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { in _rtl92se_macconfig_after_fwdownload()
872 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72); in _rtl92se_macconfig_after_fwdownload()
884 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92se_hw_configure()
900 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, in _rtl92se_hw_configure()
901 (u8 *)(&rtlpci->shortretry_limit)); in _rtl92se_hw_configure()
903 rtl_write_byte(rtlpriv, MLT, 0x8f); in _rtl92se_hw_configure()
906 switch (rtlphy->rf_type) { in _rtl92se_hw_configure()
909 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); in _rtl92se_hw_configure()
913 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); in _rtl92se_hw_configure()
916 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg); in _rtl92se_hw_configure()
923 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92se_hw_init()
937 rtlpci->being_init_adapter = true; in rtl92se_hw_init()
949 rtlpriv->intf_ops->disable_aspm(hw); in rtl92se_hw_init()
955 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv, in rtl92se_hw_init()
973 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR); in rtl92se_hw_init()
974 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK); in rtl92se_hw_init()
976 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */ in rtl92se_hw_init()
988 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR); in rtl92se_hw_init()
989 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); in rtl92se_hw_init()
990 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); in rtl92se_hw_init()
1004 /* Before initalizing RF. We can not use FW to do RF-R/W. */ in rtl92se_hw_init()
1006 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; in rtl92se_hw_init()
1008 /* Before RF-R/W we must execute the IO from Scott's suggestion. */ in rtl92se_hw_init()
1010 if (rtlhal->version == VERSION_8192S_ACUT) in rtl92se_hw_init()
1011 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07); in rtl92se_hw_init()
1024 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, in rtl92se_hw_init()
1028 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw, in rtl92se_hw_init()
1033 /*---- Set CCK and OFDM Block "ON"----*/ in rtl92se_hw_init()
1037 /*3 Set Hardware(Do nothing now) */ in rtl92se_hw_init()
1045 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); in rtl92se_hw_init()
1049 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); in rtl92se_hw_init()
1053 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3))); in rtl92se_hw_init()
1099 if (rtlphy->rf_type == RF_1T2R) { in rtl92se_hw_init()
1101 /* Turn on B-Path */ in rtl92se_hw_init()
1102 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set); in rtl92se_hw_init()
1105 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON); in rtl92se_hw_init()
1109 rtlpci->being_init_adapter = false; in rtl92se_hw_init()
1123 if (rtlpriv->psc.rfpwr_state != ERFON) in rtl92se_set_check_bssid()
1126 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92se_set_check_bssid()
1130 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92se_set_check_bssid()
1133 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92se_set_check_bssid()
1174 rtlpriv->mac80211.link_state < MAC80211_LINKED) in _rtl92se_set_media_status()
1192 return -EOPNOTSUPP; in rtl92se_set_network_type()
1194 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { in rtl92se_set_network_type()
1234 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); in rtl92se_enable_interrupt()
1235 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */ in rtl92se_enable_interrupt()
1236 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); in rtl92se_enable_interrupt()
1237 rtlpci->irq_enabled = true; in rtl92se_enable_interrupt()
1247 if (!rtlpriv || !rtlpriv->max_fw_size) in rtl92se_disable_interrupt()
1252 rtlpci->irq_enabled = false; in rtl92se_disable_interrupt()
1276 waitcnt--; in _rtl92s_set_sysclk()
1305 if (rtlhal->driver_is_goingto_unload) in _rtl92s_phy_set_rfhalt()
1326 if (rtlhal->driver_is_goingto_unload) { in _rtl92s_phy_set_rfhalt()
1347 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS && in _rtl92s_phy_set_rfhalt()
1348 !rtlhal->driver_is_goingto_unload) { in _rtl92s_phy_set_rfhalt()
1374 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; in _rtl92se_gen_refreshledstate()
1376 if (rtlpci->up_first_time) in _rtl92se_gen_refreshledstate()
1379 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS) in _rtl92se_gen_refreshledstate()
1392 rtlpriv->psc.pwrdomain_protect = true; in _rtl92se_power_domain_init()
1398 rtlpriv->psc.pwrdomain_protect = false; in _rtl92se_power_domain_init()
1406 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */ in _rtl92se_power_domain_init()
1410 * disable BIT 3/7 of reg3. */ in _rtl92se_power_domain_init()
1411 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW)) in _rtl92se_power_domain_init()
1427 tmpu1b &= ~(BIT(3)); in _rtl92se_power_domain_init()
1491 rtlpriv->psc.pwrdomain_protect = false; in _rtl92se_power_domain_init()
1500 rtlpriv->psc.pwrdomain_protect = false; in _rtl92se_power_domain_init()
1512 rtlpriv->intf_ops->enable_aspm(hw); in rtl92se_card_disable()
1514 if (rtlpci->driver_is_goingto_unload || in rtl92se_card_disable()
1515 ppsc->rfoff_reason > RF_CHANGE_BY_PS) in rtl92se_card_disable()
1516 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); in rtl92se_card_disable()
1523 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) { in rtl92se_card_disable()
1524 if (rtlpriv->psc.pwrdomain_protect) in rtl92se_card_disable()
1530 mac->link_state = MAC80211_NOLINK; in rtl92se_card_disable()
1544 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92se_interrupt_recognized()
1545 rtl_write_dword(rtlpriv, ISR, intvec->inta); in rtl92se_interrupt_recognized()
1547 intvec->intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1]; in rtl92se_interrupt_recognized()
1548 rtl_write_dword(rtlpriv, ISR + 4, intvec->intb); in rtl92se_interrupt_recognized()
1561 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval); in rtl92se_set_beacon_related_registers()
1578 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval); in rtl92se_set_beacon_related_registers()
1585 u16 bcn_interval = mac->beacon_interval; in rtl92se_set_beacon_interval()
1603 rtlpci->irq_mask[0] |= add_msr; in rtl92se_update_interrupt_mask()
1606 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92se_update_interrupt_mask()
1618 rtlhal->ic_class = IC_INFERIORITY_A; in _rtl8192se_get_ic_inferiority()
1621 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) && in _rtl8192se_get_ic_inferiority()
1622 !rtlefuse->autoload_failflag) { in _rtl8192se_get_ic_inferiority()
1626 rtlhal->ic_class = IC_INFERIORITY_B; in _rtl8192se_get_ic_inferiority()
1634 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92se_read_adapter_info()
1635 struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev; in _rtl92se_read_adapter_info()
1642 switch (rtlefuse->epromtype) { in _rtl92se_read_adapter_info()
1656 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], in _rtl92se_read_adapter_info()
1666 rtlefuse->autoload_failflag = true; in _rtl92se_read_adapter_info()
1669 rtlefuse->autoload_failflag = false; in _rtl92se_read_adapter_info()
1672 if (rtlefuse->autoload_failflag) in _rtl92se_read_adapter_info()
1678 /* VID, DID SE 0xA-D */ in _rtl92se_read_adapter_info()
1679 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; in _rtl92se_read_adapter_info()
1680 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; in _rtl92se_read_adapter_info()
1681 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; in _rtl92se_read_adapter_info()
1682 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; in _rtl92se_read_adapter_info()
1683 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; in _rtl92se_read_adapter_info()
1688 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); in _rtl92se_read_adapter_info()
1690 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); in _rtl92se_read_adapter_info()
1692 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); in _rtl92se_read_adapter_info()
1694 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); in _rtl92se_read_adapter_info()
1698 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; in _rtl92se_read_adapter_info()
1702 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); in _rtl92se_read_adapter_info()
1704 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); in _rtl92se_read_adapter_info()
1710 for (i = 0; i < 3; i++) { in _rtl92se_read_adapter_info()
1712 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = in _rtl92se_read_adapter_info()
1713 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i]; in _rtl92se_read_adapter_info()
1716 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = in _rtl92se_read_adapter_info()
1717 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i]; in _rtl92se_read_adapter_info()
1720 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i] in _rtl92se_read_adapter_info()
1722 rf_path * 3 + i]; in _rtl92se_read_adapter_info()
1727 for (i = 0; i < 3; i++) in _rtl92se_read_adapter_info()
1731 rtlefuse->eeprom_chnlarea_txpwr_cck in _rtl92se_read_adapter_info()
1734 for (i = 0; i < 3; i++) in _rtl92se_read_adapter_info()
1738 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s in _rtl92se_read_adapter_info()
1741 for (i = 0; i < 3; i++) in _rtl92se_read_adapter_info()
1745 rtlefuse->eprom_chnl_txpwr_ht40_2sdf in _rtl92se_read_adapter_info()
1752 /* channel 1~3 use the same Tx Power Level. */ in _rtl92se_read_adapter_info()
1753 if (i < 3) in _rtl92se_read_adapter_info()
1755 /* Channel 4-8 */ in _rtl92se_read_adapter_info()
1758 /* Channel 9-14 */ in _rtl92se_read_adapter_info()
1762 /* Record A & B CCK /OFDM - 1T/2T Channel area in _rtl92se_read_adapter_info()
1764 rtlefuse->txpwrlevel_cck[rf_path][i] = in _rtl92se_read_adapter_info()
1765 rtlefuse->eeprom_chnlarea_txpwr_cck in _rtl92se_read_adapter_info()
1767 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = in _rtl92se_read_adapter_info()
1768 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s in _rtl92se_read_adapter_info()
1770 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = in _rtl92se_read_adapter_info()
1771 rtlefuse->eprom_chnl_txpwr_ht40_2sdf in _rtl92se_read_adapter_info()
1777 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", in _rtl92se_read_adapter_info()
1779 rtlefuse->txpwrlevel_cck[rf_path][i], in _rtl92se_read_adapter_info()
1780 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], in _rtl92se_read_adapter_info()
1781 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); in _rtl92se_read_adapter_info()
1786 for (i = 0; i < 3; i++) { in _rtl92se_read_adapter_info()
1788 rtlefuse->eeprom_pwrgroup[rf_path][i] = in _rtl92se_read_adapter_info()
1789 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i]; in _rtl92se_read_adapter_info()
1796 /* Chanel 1-3 */ in _rtl92se_read_adapter_info()
1797 if (i < 3) in _rtl92se_read_adapter_info()
1799 /* Channel 4-8 */ in _rtl92se_read_adapter_info()
1802 /* Channel 9-13 */ in _rtl92se_read_adapter_info()
1806 rtlefuse->pwrgroup_ht20[rf_path][i] = in _rtl92se_read_adapter_info()
1807 (rtlefuse->eeprom_pwrgroup[rf_path][index] & in _rtl92se_read_adapter_info()
1809 rtlefuse->pwrgroup_ht40[rf_path][i] = in _rtl92se_read_adapter_info()
1810 ((rtlefuse->eeprom_pwrgroup[rf_path][index] & in _rtl92se_read_adapter_info()
1814 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1816 rtlefuse->pwrgroup_ht20[rf_path][i]); in _rtl92se_read_adapter_info()
1818 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1820 rtlefuse->pwrgroup_ht40[rf_path][i]); in _rtl92se_read_adapter_info()
1826 /* channel 1-3 */ in _rtl92se_read_adapter_info()
1827 if (i < 3) in _rtl92se_read_adapter_info()
1829 /* Channel 4-8 */ in _rtl92se_read_adapter_info()
1832 /* Channel 9-14 */ in _rtl92se_read_adapter_info()
1837 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); in _rtl92se_read_adapter_info()
1838 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = in _rtl92se_read_adapter_info()
1841 /* Read OFDM<->HT tx power diff */ in _rtl92se_read_adapter_info()
1842 /* Channel 1-3 */ in _rtl92se_read_adapter_info()
1843 if (i < 3) in _rtl92se_read_adapter_info()
1845 /* Channel 4-8 */ in _rtl92se_read_adapter_info()
1848 /* Channel 9-14 */ in _rtl92se_read_adapter_info()
1853 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = in _rtl92se_read_adapter_info()
1855 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = in _rtl92se_read_adapter_info()
1859 rtlefuse->txpwr_safetyflag = (tempval & 0x01); in _rtl92se_read_adapter_info()
1862 rtlefuse->eeprom_regulatory = 0; in _rtl92se_read_adapter_info()
1863 if (rtlefuse->eeprom_version >= 2) { in _rtl92se_read_adapter_info()
1865 if (rtlefuse->eeprom_version >= 4) in _rtl92se_read_adapter_info()
1866 rtlefuse->eeprom_regulatory = in _rtl92se_read_adapter_info()
1869 rtlefuse->eeprom_regulatory = in _rtl92se_read_adapter_info()
1873 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); in _rtl92se_read_adapter_info()
1877 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1878 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); in _rtl92se_read_adapter_info()
1881 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1882 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); in _rtl92se_read_adapter_info()
1885 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1886 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); in _rtl92se_read_adapter_info()
1889 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", in _rtl92se_read_adapter_info()
1890 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); in _rtl92se_read_adapter_info()
1893 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag); in _rtl92se_read_adapter_info()
1895 /* Read RF-indication and Tx Power gain in _rtl92se_read_adapter_info()
1898 rtlefuse->eeprom_txpowerdiff = tempval; in _rtl92se_read_adapter_info()
1899 rtlefuse->legacy_ht_txpowerdiff = in _rtl92se_read_adapter_info()
1900 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0]; in _rtl92se_read_adapter_info()
1903 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff); in _rtl92se_read_adapter_info()
1907 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8); in _rtl92se_read_adapter_info()
1909 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff); in _rtl92se_read_adapter_info()
1912 rtlefuse->eeprom_tssi[RF90_PATH_A], in _rtl92se_read_adapter_info()
1913 rtlefuse->eeprom_tssi[RF90_PATH_B]); in _rtl92se_read_adapter_info()
1918 rtlefuse->eeprom_thermalmeter = tempval; in _rtl92se_read_adapter_info()
1920 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); in _rtl92se_read_adapter_info()
1922 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */ in _rtl92se_read_adapter_info()
1923 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f); in _rtl92se_read_adapter_info()
1924 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100; in _rtl92se_read_adapter_info()
1928 rtlefuse->eeprom_crystalcap = tempval; in _rtl92se_read_adapter_info()
1930 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap; in _rtl92se_read_adapter_info()
1934 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN]; in _rtl92se_read_adapter_info()
1935 rtlefuse->txpwr_fromeprom = true; in _rtl92se_read_adapter_info()
1937 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan); in _rtl92se_read_adapter_info()
1943 rtlphy->rf_type = RF_2T2R; in _rtl92se_read_adapter_info()
1945 rtlphy->rf_type = RF_1T2R; in _rtl92se_read_adapter_info()
1947 rtlphy->rf_type = RF_1T2R; in _rtl92se_read_adapter_info()
1948 else if (tempval == 3) in _rtl92se_read_adapter_info()
1949 rtlphy->rf_type = RF_1T1R; in _rtl92se_read_adapter_info()
1952 rtlefuse->b1x1_recvcombine = false; in _rtl92se_read_adapter_info()
1953 if (rtlphy->rf_type == RF_1T2R) { in _rtl92se_read_adapter_info()
1956 rtlefuse->b1x1_recvcombine = true; in _rtl92se_read_adapter_info()
1961 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine; in _rtl92se_read_adapter_info()
1962 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID]; in _rtl92se_read_adapter_info()
1965 rtlefuse->eeprom_oemid); in _rtl92se_read_adapter_info()
1968 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; in _rtl92se_read_adapter_info()
1981 rtlefuse->epromtype = EEPROM_93C46; in rtl92se_read_eeprom_info()
1984 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; in rtl92se_read_eeprom_info()
1989 rtlefuse->autoload_failflag = false; in rtl92se_read_eeprom_info()
1993 rtlefuse->autoload_failflag = true; in rtl92se_read_eeprom_info()
2001 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92se_update_hal_rate_table()
2006 u8 nmode = mac->ht_enable; in rtl92se_update_hal_rate_table()
2010 u8 curtxbw_40mhz = mac->bw_40; in rtl92se_update_hal_rate_table()
2011 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? in rtl92se_update_hal_rate_table()
2013 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? in rtl92se_update_hal_rate_table()
2015 enum wireless_mode wirelessmode = mac->mode; in rtl92se_update_hal_rate_table()
2017 if (rtlhal->current_bandtype == BAND_ON_5G) in rtl92se_update_hal_rate_table()
2018 ratr_value = sta->deflink.supp_rates[1] << 4; in rtl92se_update_hal_rate_table()
2020 ratr_value = sta->deflink.supp_rates[0]; in rtl92se_update_hal_rate_table()
2021 if (mac->opmode == NL80211_IFTYPE_ADHOC) in rtl92se_update_hal_rate_table()
2023 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | in rtl92se_update_hal_rate_table()
2024 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92se_update_hal_rate_table()
2057 if (rtlphy->rf_type == RF_1T2R) in rtl92se_update_hal_rate_table()
2065 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) in rtl92se_update_hal_rate_table()
2067 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) in rtl92se_update_hal_rate_table()
2077 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { in rtl92se_update_hal_rate_table()
2103 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92se_update_hal_rate_mask()
2109 u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; in rtl92se_update_hal_rate_mask()
2110 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? in rtl92se_update_hal_rate_mask()
2112 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? in rtl92se_update_hal_rate_mask()
2124 sta_entry = (struct rtl_sta_info *) sta->drv_priv; in rtl92se_update_hal_rate_mask()
2125 wirelessmode = sta_entry->wireless_mode; in rtl92se_update_hal_rate_mask()
2126 if (mac->opmode == NL80211_IFTYPE_STATION) in rtl92se_update_hal_rate_mask()
2127 curtxbw_40mhz = mac->bw_40; in rtl92se_update_hal_rate_mask()
2128 else if (mac->opmode == NL80211_IFTYPE_AP || in rtl92se_update_hal_rate_mask()
2129 mac->opmode == NL80211_IFTYPE_ADHOC) in rtl92se_update_hal_rate_mask()
2130 macid = sta->aid + 1; in rtl92se_update_hal_rate_mask()
2132 if (rtlhal->current_bandtype == BAND_ON_5G) in rtl92se_update_hal_rate_mask()
2133 ratr_bitmap = sta->deflink.supp_rates[1] << 4; in rtl92se_update_hal_rate_mask()
2135 ratr_bitmap = sta->deflink.supp_rates[0]; in rtl92se_update_hal_rate_mask()
2136 if (mac->opmode == NL80211_IFTYPE_ADHOC) in rtl92se_update_hal_rate_mask()
2138 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | in rtl92se_update_hal_rate_mask()
2139 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92se_update_hal_rate_mask()
2178 if (rtlphy->rf_type == RF_1T2R || in rtl92se_update_hal_rate_mask()
2179 rtlphy->rf_type == RF_1T1R) { in rtl92se_update_hal_rate_mask()
2182 } else if (rssi_level == 3) { in rtl92se_update_hal_rate_mask()
2195 } else if (rssi_level == 3) { in rtl92se_update_hal_rate_mask()
2220 if (rtlphy->rf_type == RF_1T2R) in rtl92se_update_hal_rate_mask()
2226 sta_entry->ratr_index = ratr_index; in rtl92se_update_hal_rate_mask()
2228 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) in rtl92se_update_hal_rate_mask()
2230 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) in rtl92se_update_hal_rate_mask()
2237 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { in rtl92se_update_hal_rate_mask()
2255 sta_entry->ratr_index = ratr_index; in rtl92se_update_hal_rate_mask()
2263 if (rtlpriv->dm.useramask) in rtl92se_update_hal_rate_tbl()
2275 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, in rtl92se_update_channel_access_setting()
2276 &mac->slot_time); in rtl92se_update_channel_access_setting()
2278 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); in rtl92se_update_channel_access_setting()
2296 if (rtlpci->up_first_time || rtlpci->being_init_adapter) in rtl92se_gpio_radio_on_off_checking()
2299 if (ppsc->swrf_processing) in rtl92se_gpio_radio_on_off_checking()
2302 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92se_gpio_radio_on_off_checking()
2303 if (ppsc->rfchange_inprogress) { in rtl92se_gpio_radio_on_off_checking()
2304 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92se_gpio_radio_on_off_checking()
2307 ppsc->rfchange_inprogress = true; in rtl92se_gpio_radio_on_off_checking()
2308 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92se_gpio_radio_on_off_checking()
2311 /* cur_rfstate = ppsc->rfpwr_state;*/ in rtl92se_gpio_radio_on_off_checking()
2324 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) { in rtl92se_gpio_radio_on_off_checking()
2326 "RFKILL-HW Radio ON, RF ON\n"); in rtl92se_gpio_radio_on_off_checking()
2329 ppsc->hwradiooff = false; in rtl92se_gpio_radio_on_off_checking()
2331 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) { in rtl92se_gpio_radio_on_off_checking()
2333 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n"); in rtl92se_gpio_radio_on_off_checking()
2336 ppsc->hwradiooff = true; in rtl92se_gpio_radio_on_off_checking()
2341 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92se_gpio_radio_on_off_checking()
2342 ppsc->rfchange_inprogress = false; in rtl92se_gpio_radio_on_off_checking()
2343 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92se_gpio_radio_on_off_checking()
2353 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC && in rtl92se_gpio_radio_on_off_checking()
2359 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); in rtl92se_gpio_radio_on_off_checking()
2360 ppsc->rfchange_inprogress = false; in rtl92se_gpio_radio_on_off_checking()
2361 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); in rtl92se_gpio_radio_on_off_checking()
2365 return !ppsc->hwradiooff; in rtl92se_gpio_radio_on_off_checking()
2404 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92se_set_key()
2406 rtlpriv->sec.key_len[idx] = 0; in rtl92se_set_key()
2431 if (is_wepkey || rtlpriv->sec.use_defaultkey) { in rtl92se_set_key()
2439 if (mac->opmode == NL80211_IFTYPE_AP) { in rtl92se_set_key()
2455 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92se_set_key()
2459 if (mac->opmode == NL80211_IFTYPE_AP) in rtl92se_set_key()
2472 rtlpriv->sec.key_buf[key_index]); in rtl92se_set_key()
2477 if (mac->opmode == NL80211_IFTYPE_ADHOC) { in rtl92se_set_key()
2479 rtlefuse->dev_addr, in rtl92se_set_key()
2483 rtlpriv->sec.key_buf[entry_id]); in rtl92se_set_key()
2489 rtlpriv->sec.key_buf[entry_id]); in rtl92se_set_key()
2500 rtlpci->up_first_time = true; in rtl92se_suspend()
2508 pci_read_config_dword(rtlpci->pdev, 0x40, &val); in rtl92se_resume()
2510 pci_write_config_dword(rtlpci->pdev, 0x40, in rtl92se_resume()