Lines Matching refs:PWR_CMD_WRITE
47 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
50 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
53 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
59 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
62 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
73 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
76 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
79 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
90 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
94 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
97 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
100 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
111 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
117 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
125 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20}, \
128 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
131 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
135 PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
138 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
141 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
152 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, BIT(0), 0}, \
158 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
161 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
164 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
172 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
175 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
183 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
191 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
194 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
209 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
215 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
218 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03}, \
221 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
224 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00}, \
227 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
235 PWR_BASEADDR_SDIO , PWR_CMD_WRITE, 0xFF, 0x84}, \
238 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
241 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
247 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
253 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
256 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
259 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
262 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
265 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},