Lines Matching refs:PWR_BASEADDR_MAC
47 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
50 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
53 PWR_BASEADDR_MAC , PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
56 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), BIT(1)}, \
59 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
62 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
65 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(0), 0},
73 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
76 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0}, \
79 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
82 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(1), 0},
90 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))},\
93 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
97 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
117 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
125 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x20}, \
128 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
131 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
134 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
138 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), BIT(2)}, \
158 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), BIT(0)}, \
161 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0}, \
164 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
172 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
175 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), BIT(7)},
183 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(7), 0},
191 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
194 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
197 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
200 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
203 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
206 PWR_BASEADDR_MAC , PWR_CMD_POLLING, 0xFF, 0}, \
209 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(0), 0}, \
212 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
215 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
218 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x03}, \
221 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), 0}, \
224 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x00}, \
227 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(5), BIT(5)},
238 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
241 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0x84}, \
244 PWR_BASEADDR_MAC , PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
247 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(4), 0}, \
250 PWR_BASEADDR_MAC , PWR_CMD_POLLING, BIT(7), 0}, \
253 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1), BIT(1)}, \
256 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF}, \
259 PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},\
262 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0}, \
265 PWR_BASEADDR_MAC , PWR_CMD_WRITE, 0xFF, 0xFF},