Lines Matching refs:rtl_set_rfreg
280 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); in _rtl92ee_config_rf_reg()
292 rtl_set_rfreg(hw, rfpath, regaddr, in _rtl92ee_config_rf_reg()
311 rtl_set_rfreg(hw, rfpath, regaddr, in _rtl92ee_config_rf_reg()
314 rtl_set_rfreg(hw, rfpath, 0x18, in _rtl92ee_config_rf_reg()
1884 rtl_set_rfreg(hw, (enum radio_path)rfpath, in _rtl92ee_phy_sw_chnl_step_by_step()
1935 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_iqk()
1976 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_iqk()
2022 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2023 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2024 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2025 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_a_rx_iqk()
2028 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2029 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2068 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2079 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2081 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2082 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2083 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_a_rx_iqk()
2086 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2087 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2118 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2138 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2139 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2140 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2141 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_b_rx_iqk()
2144 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2145 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2183 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2193 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2195 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2196 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2197 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_b_rx_iqk()
2200 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2201 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2232 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2395 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000); in _rtl92ee_phy_path_a_standby()
2683 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2687 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2692 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl92ee_phy_lc_calibrate()
2698 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl92ee_phy_lc_calibrate()
2701 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
3027 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92ee_phy_set_rf_sleep()