Lines Matching refs:rtl_set_bbreg
158 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92ee_phy_rf_serial_read()
160 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92ee_phy_rf_serial_read()
197 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92ee_phy_rf_serial_write()
234 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl92ee_phy_bb_config()
362 rtl_set_bbreg(hw, addr, MASKDWORD , data); in _rtl92ee_config_bb_reg()
725 rtl_set_bbreg(hw, array[i], MASKDWORD, in phy_config_bb_with_hdr_file()
753 rtl_set_bbreg(hw, in phy_config_bb_with_hdr_file()
1274 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, in _rtl92ee_set_txpower_index()
1278 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1, in _rtl92ee_set_txpower_index()
1282 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2, in _rtl92ee_set_txpower_index()
1286 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3, in _rtl92ee_set_txpower_index()
1290 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0, in _rtl92ee_set_txpower_index()
1294 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1, in _rtl92ee_set_txpower_index()
1298 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2, in _rtl92ee_set_txpower_index()
1302 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3, in _rtl92ee_set_txpower_index()
1306 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0, in _rtl92ee_set_txpower_index()
1310 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1, in _rtl92ee_set_txpower_index()
1314 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2, in _rtl92ee_set_txpower_index()
1318 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3, in _rtl92ee_set_txpower_index()
1322 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0, in _rtl92ee_set_txpower_index()
1326 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1, in _rtl92ee_set_txpower_index()
1330 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2, in _rtl92ee_set_txpower_index()
1334 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3, in _rtl92ee_set_txpower_index()
1338 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0, in _rtl92ee_set_txpower_index()
1342 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1, in _rtl92ee_set_txpower_index()
1346 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2, in _rtl92ee_set_txpower_index()
1350 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3, in _rtl92ee_set_txpower_index()
1354 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0, in _rtl92ee_set_txpower_index()
1358 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1, in _rtl92ee_set_txpower_index()
1362 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2, in _rtl92ee_set_txpower_index()
1366 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3, in _rtl92ee_set_txpower_index()
1370 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0, in _rtl92ee_set_txpower_index()
1374 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1, in _rtl92ee_set_txpower_index()
1378 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2, in _rtl92ee_set_txpower_index()
1382 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3, in _rtl92ee_set_txpower_index()
1393 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1, in _rtl92ee_set_txpower_index()
1397 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2, in _rtl92ee_set_txpower_index()
1401 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3, in _rtl92ee_set_txpower_index()
1405 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, in _rtl92ee_set_txpower_index()
1409 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0, in _rtl92ee_set_txpower_index()
1413 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1, in _rtl92ee_set_txpower_index()
1417 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2, in _rtl92ee_set_txpower_index()
1421 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3, in _rtl92ee_set_txpower_index()
1425 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0, in _rtl92ee_set_txpower_index()
1429 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1, in _rtl92ee_set_txpower_index()
1433 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2, in _rtl92ee_set_txpower_index()
1437 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3, in _rtl92ee_set_txpower_index()
1441 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0, in _rtl92ee_set_txpower_index()
1445 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1, in _rtl92ee_set_txpower_index()
1449 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2, in _rtl92ee_set_txpower_index()
1453 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3, in _rtl92ee_set_txpower_index()
1457 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0, in _rtl92ee_set_txpower_index()
1461 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1, in _rtl92ee_set_txpower_index()
1465 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2, in _rtl92ee_set_txpower_index()
1469 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3, in _rtl92ee_set_txpower_index()
1473 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0, in _rtl92ee_set_txpower_index()
1477 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1, in _rtl92ee_set_txpower_index()
1481 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2, in _rtl92ee_set_txpower_index()
1485 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3, in _rtl92ee_set_txpower_index()
1489 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0, in _rtl92ee_set_txpower_index()
1493 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1, in _rtl92ee_set_txpower_index()
1497 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2, in _rtl92ee_set_txpower_index()
1501 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3, in _rtl92ee_set_txpower_index()
1689 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1690 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1691 rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT, in rtl92ee_phy_set_bw_mode_callback()
1695 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1696 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1697 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, in rtl92ee_phy_set_bw_mode_callback()
1699 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, in rtl92ee_phy_set_bw_mode_callback()
1702 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92ee_phy_set_bw_mode_callback()
1934 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_iqk()
1936 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_iqk()
1938 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_iqk()
1939 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1940 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1941 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1943 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); in _rtl92ee_phy_path_a_iqk()
1944 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_a_iqk()
1947 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_a_iqk()
1950 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92ee_phy_path_a_iqk()
1951 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_iqk()
1975 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1977 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1979 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1980 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1982 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1983 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1984 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_iqk()
1985 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1987 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); in _rtl92ee_phy_path_b_iqk()
1988 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_b_iqk()
1991 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_b_iqk()
1994 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_iqk()
1995 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_iqk()
2020 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2032 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2035 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_a_rx_iqk()
2036 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2039 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2040 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2041 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2042 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2044 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2045 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2048 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_a_rx_iqk()
2051 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2052 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2067 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2074 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_a_rx_iqk()
2077 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2090 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2093 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2096 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2097 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2098 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2099 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2101 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2102 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2105 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_a_rx_iqk()
2107 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2108 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2117 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2136 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2147 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2150 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_b_rx_iqk()
2151 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2154 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2155 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2156 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2157 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2159 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2160 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2163 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_b_rx_iqk()
2166 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2167 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2182 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2189 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_b_rx_iqk()
2192 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2204 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2207 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2210 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2211 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2212 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2213 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2215 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2216 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2219 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_b_rx_iqk()
2221 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2222 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2231 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2261 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2262 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), in _rtl92ee_phy_path_a_fill_iqk_matrix()
2268 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2270 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2272 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), in _rtl92ee_phy_path_a_fill_iqk_matrix()
2279 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2282 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2285 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2306 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2307 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), in _rtl92ee_phy_path_b_fill_iqk_matrix()
2313 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2315 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2317 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), in _rtl92ee_phy_path_b_fill_iqk_matrix()
2324 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2327 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2330 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2363 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); in _rtl92ee_phy_reload_adda_registers()
2383 rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616); in _rtl92ee_phy_path_adda_on()
2389 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff); in _rtl92ee_phy_mac_setting_calibration()
2394 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92ee_phy_path_a_standby()
2396 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_standby()
2514 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92ee_phy_iq_calibrate()
2515 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92ee_phy_iq_calibrate()
2516 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92ee_phy_iq_calibrate()
2517 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); in _rtl92ee_phy_iq_calibrate()
2519 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2520 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); in _rtl92ee_phy_iq_calibrate()
2521 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2522 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2528 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2529 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2530 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2582 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2583 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2584 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2633 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl92ee_phy_iq_calibrate()
2650 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2651 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50); in _rtl92ee_phy_iq_calibrate()
2653 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2654 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58); in _rtl92ee_phy_iq_calibrate()
2658 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2659 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2722 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92ee_phy_set_rfpath_switch()
2726 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2729 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2732 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl92ee_phy_set_rfpath_switch()
2733 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl92ee_phy_set_rfpath_switch()
2740 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2742 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2745 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl92ee_phy_set_rfpath_switch()
2747 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2749 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2752 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); in _rtl92ee_phy_set_rfpath_switch()