151 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
155 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
163 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,  in _rtl92ee_phy_rf_serial_read()
166 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,  in _rtl92ee_phy_rf_serial_read()
169 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,  in _rtl92ee_phy_rf_serial_read()
172 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,  in _rtl92ee_phy_rf_serial_read()
636 	rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,  in _rtl92ee_phy_bb8192ee_config_parafile()
1008 		(u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1010 		(u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1012 		(u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1014 		(u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1023 	rtlphy->framesync = (u8)rtl_get_bbreg(hw,  in rtl92ee_phy_get_hw_reg_originalvalue()
1025 	rtlphy->framesync_c34 = rtl_get_bbreg(hw,  in rtl92ee_phy_get_hw_reg_originalvalue()
1955 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1956 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1957 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1999 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2000 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2001 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2057 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2058 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2059 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2112 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2113 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2172 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2173 	reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2174 	reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2226 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2227 	reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2228 	reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2255 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,  in _rtl92ee_phy_path_a_fill_iqk_matrix()
2300 		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,  in _rtl92ee_phy_path_b_fill_iqk_matrix()
2341 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in _rtl92ee_phy_save_adda_registers()
2481 	u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0);  in _rtl92ee_phy_iq_calibrate()
2482 	u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0);  in _rtl92ee_phy_iq_calibrate()
2538 			result[t][0] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2542 			result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A,  in _rtl92ee_phy_iq_calibrate()
2558 			result[t][2] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2562 			result[t][3] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2591 				result[t][4] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2595 				result[t][5] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2611 				result[t][6] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2615 				result[t][7] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()