165 	else if (rfpath == RF90_PATH_B)  in _rtl92ee_phy_rf_serial_read()
342 	_rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B,  in _rtl92ee_config_rf_radio_b()
470 	for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {  in _rtl92ee_phy_store_txpower_by_rate_base()
479 		} else if (path == RF90_PATH_B) {  in _rtl92ee_phy_store_txpower_by_rate_base()
540 	for (rf = RF90_PATH_A; rf <= RF90_PATH_B; ++rf) {  in phy_convert_txpwr_dbm_to_rel_val()
553 		} else if (rf == RF90_PATH_B) {  in phy_convert_txpwr_dbm_to_rel_val()
949 	case RF90_PATH_B:  in rtl92ee_phy_config_rf_with_headerfile()
1039 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in phy_init_bb_rf_register_def()
1042 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1045 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1049 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in phy_init_bb_rf_register_def()
1053 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in phy_init_bb_rf_register_def()
1056 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in phy_init_bb_rf_register_def()
1059 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;  in phy_init_bb_rf_register_def()
1099 		else if (path == RF90_PATH_B)  in _rtl92ee_phy_get_ratesection_intxpower_byrate()
1390 	} else if (rfpath == RF90_PATH_B) {  in _rtl92ee_set_txpower_index()
1976 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);  in _rtl92ee_phy_path_b_iqk()
2138 	rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);  in _rtl92ee_phy_path_b_rx_iqk()
2139 	rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);  in _rtl92ee_phy_path_b_rx_iqk()
2140 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);  in _rtl92ee_phy_path_b_rx_iqk()
2141 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);  in _rtl92ee_phy_path_b_rx_iqk()
2144 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);  in _rtl92ee_phy_path_b_rx_iqk()
2145 	rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);  in _rtl92ee_phy_path_b_rx_iqk()
2183 		rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);  in _rtl92ee_phy_path_b_rx_iqk()
2193 	rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);  in _rtl92ee_phy_path_b_rx_iqk()
2195 	rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);  in _rtl92ee_phy_path_b_rx_iqk()
2196 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);  in _rtl92ee_phy_path_b_rx_iqk()
2197 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);  in _rtl92ee_phy_path_b_rx_iqk()
2200 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);  in _rtl92ee_phy_path_b_rx_iqk()
2201 	rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);  in _rtl92ee_phy_path_b_rx_iqk()
2232 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);  in _rtl92ee_phy_path_b_rx_iqk()
2680 			rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,  in _rtl92ee_phy_lc_calibrate()
2687 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,  in _rtl92ee_phy_lc_calibrate()
2701 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,  in _rtl92ee_phy_lc_calibrate()