Lines Matching +full:0 +full:xfa000000
52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92ee_phy_query_bb_reg()
142 u8 rfpi_enable = 0; in _rtl92ee_phy_rf_serial_read()
145 offset &= 0xff; in _rtl92ee_phy_rf_serial_read()
149 return 0xFFFFFFFF; in _rtl92ee_phy_rf_serial_read()
175 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92ee_phy_rf_serial_read()
194 offset &= 0xff; in _rtl92ee_phy_rf_serial_write()
196 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92ee_phy_rf_serial_write()
199 "RFW-%d Addr[0x%x]=0x%x\n", rfpath, in _rtl92ee_phy_rf_serial_write()
219 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92ee_phy_bb_config()
226 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92ee_phy_bb_config()
228 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl92ee_phy_bb_config()
229 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl92ee_phy_bb_config()
233 crystal_cap = rtlpriv->efuse.eeprom_crystalcap & 0x3F; in rtl92ee_phy_bb_config()
234 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl92ee_phy_bb_config()
251 u32 _platform = 0x08;/*SupportPlatform */ in _check_condition()
254 if (condition == 0xCDCDCDCD) in _check_condition()
257 cond = condition & 0xFF; in _check_condition()
258 if ((_board != cond) && (cond != 0xFF)) in _check_condition()
261 cond = condition & 0xFF00; in _check_condition()
263 if ((_interface & cond) == 0 && cond != 0x07) in _check_condition()
266 cond = condition & 0xFF0000; in _check_condition()
268 if ((_platform & cond) == 0 && cond != 0x0F) in _check_condition()
277 if (addr == 0xfe || addr == 0xffe) { in _rtl92ee_config_rf_reg()
283 if (addr == 0xb6) { in _rtl92ee_config_rf_reg()
285 u8 count = 0; in _rtl92ee_config_rf_reg()
302 if (addr == 0xb2) { in _rtl92ee_config_rf_reg()
304 u8 count = 0; in _rtl92ee_config_rf_reg()
314 rtl_set_rfreg(hw, rfpath, 0x18, in _rtl92ee_config_rf_reg()
315 RFREG_OFFSET_MASK, 0x0fc07); in _rtl92ee_config_rf_reg()
329 u32 content = 0x1000; /*RF Content: radio_a_txt*/ in _rtl92ee_config_rf_radio_a()
330 u32 maskforphyset = (u32)(content & 0xE000); in _rtl92ee_config_rf_radio_a()
339 u32 content = 0x1001; /*RF Content: radio_b_txt*/ in _rtl92ee_config_rf_radio_b()
340 u32 maskforphyset = (u32)(content & 0xE000); in _rtl92ee_config_rf_radio_b()
349 if (addr == 0xfe) in _rtl92ee_config_bb_reg()
351 else if (addr == 0xfd) in _rtl92ee_config_bb_reg()
353 else if (addr == 0xfc) in _rtl92ee_config_bb_reg()
355 else if (addr == 0xfb) in _rtl92ee_config_bb_reg()
357 else if (addr == 0xfa) in _rtl92ee_config_bb_reg()
359 else if (addr == 0xf9) in _rtl92ee_config_bb_reg()
372 u8 band = BAND_ON_2_4G, rf = 0, txnum = 0, sec = 0; in _rtl92ee_phy_init_tx_power_by_rate()
379 [band][rf][txnum][sec] = 0; in _rtl92ee_phy_init_tx_power_by_rate()
399 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value; in _rtl92ee_phy_set_txpower_by_rate_base()
428 u8 value = 0; in _rtl92ee_phy_get_txpower_by_rate_base()
433 return 0; in _rtl92ee_phy_get_txpower_by_rate_base()
439 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0]; in _rtl92ee_phy_get_txpower_by_rate_base()
467 u16 raw = 0; in _rtl92ee_phy_store_txpower_by_rate_base()
468 u8 base = 0, path = 0; in _rtl92ee_phy_store_txpower_by_rate_base()
474 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
475 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
481 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) & in _rtl92ee_phy_store_txpower_by_rate_base()
482 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
483 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
489 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
490 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
495 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
496 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
502 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
503 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
513 s8 i = 0; in _phy_convert_txpower_dbm_to_relative_value()
514 u8 tmp = 0; in _phy_convert_txpower_dbm_to_relative_value()
515 u32 temp_data = 0; in _phy_convert_txpower_dbm_to_relative_value()
517 for (i = 3; i >= 0; --i) { in _phy_convert_txpower_dbm_to_relative_value()
520 tmp = (u8)(*data >> (i * 8)) & 0xF; in _phy_convert_txpower_dbm_to_relative_value()
521 tmp += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10; in _phy_convert_txpower_dbm_to_relative_value()
526 tmp = (u8)(*data >> (i * 8)) & 0xFF; in _phy_convert_txpower_dbm_to_relative_value()
538 u8 base = 0, rf = 0, band = BAND_ON_2_4G; in phy_convert_txpwr_dbm_to_rel_val()
560 0, 0, base); in phy_convert_txpwr_dbm_to_rel_val()
569 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0], in phy_convert_txpwr_dbm_to_rel_val()
570 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
573 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
580 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
583 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
590 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
594 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
622 rtlphy->pwrgroup_cnt = 0; in _rtl92ee_phy_bb8192ee_config_parafile()
638 0x200)); in _rtl92ee_phy_bb8192ee_config_parafile()
655 for (i = 0; i < arraylength; i = i + 2) in _rtl92ee_phy_config_mac_with_headerfile()
665 } while (0)
674 u32 v1 = 0, v2 = 0; in phy_config_bb_with_hdr_file()
680 for (i = 0; i < len; i = i + 2) { in phy_config_bb_with_hdr_file()
683 if (v1 < 0xcdcdcdcd) { in phy_config_bb_with_hdr_file()
693 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
694 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
695 v2 != 0xCDCD && i < len - 2) { in phy_config_bb_with_hdr_file()
704 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
705 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
706 v2 != 0xCDCD && i < len - 2) { in phy_config_bb_with_hdr_file()
712 while (v2 != 0xDEAD && i < len - 2) in phy_config_bb_with_hdr_file()
721 for (i = 0; i < len; i = i + 2) { in phy_config_bb_with_hdr_file()
724 if (v1 < 0xCDCDCDCD) { in phy_config_bb_with_hdr_file()
737 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
738 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
739 v2 != 0xCDCD && in phy_config_bb_with_hdr_file()
749 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
750 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
751 v2 != 0xCDCD && in phy_config_bb_with_hdr_file()
761 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
768 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", in phy_config_bb_with_hdr_file()
778 u8 index = 0; in _rtl92ee_get_rate_section_index()
783 index = 0; in _rtl92ee_get_rate_section_index()
813 regaddr &= 0xFFF; in _rtl92ee_get_rate_section_index()
814 if (regaddr >= 0xC20 && regaddr <= 0xC4C) in _rtl92ee_get_rate_section_index()
815 index = (u8)((regaddr - 0xC20) / 4); in _rtl92ee_get_rate_section_index()
816 else if (regaddr >= 0xE20 && regaddr <= 0xE4C) in _rtl92ee_get_rate_section_index()
817 index = (u8)((regaddr - 0xE20) / 4); in _rtl92ee_get_rate_section_index()
858 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; in phy_config_bb_with_pghdrfile()
864 for (i = 0; i < phy_regarray_pg_len; i = i + 6) { in phy_config_bb_with_pghdrfile()
872 if (v1 < 0xcdcdcdcd) { in phy_config_bb_with_pghdrfile()
890 } while (0)
899 u32 v1 = 0, v2 = 0; in rtl92ee_phy_config_rf_with_headerfile()
908 for (i = 0; i < len; i = i + 2) { in rtl92ee_phy_config_rf_with_headerfile()
911 if (v1 < 0xcdcdcdcd) { in rtl92ee_phy_config_rf_with_headerfile()
922 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
923 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
924 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
933 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
934 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
935 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
942 while (v2 != 0xDEAD && i < len - 2) in rtl92ee_phy_config_rf_with_headerfile()
955 for (i = 0; i < len; i = i + 2) { in rtl92ee_phy_config_rf_with_headerfile()
958 if (v1 < 0xcdcdcdcd) { in rtl92ee_phy_config_rf_with_headerfile()
969 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
970 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
971 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
980 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
981 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
982 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
989 while (v2 != 0xDEAD && i < len - 2) in rtl92ee_phy_config_rf_with_headerfile()
1007 rtlphy->default_initialgain[0] = in rtl92ee_phy_get_hw_reg_originalvalue()
1017 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl92ee_phy_get_hw_reg_originalvalue()
1018 rtlphy->default_initialgain[0], in rtl92ee_phy_get_hw_reg_originalvalue()
1029 "Default framesync (0x%x) = 0x%x\n", in rtl92ee_phy_get_hw_reg_originalvalue()
1089 u8 rate_section = 0; in _rtl92ee_phy_get_ratesection_intxpower_byrate()
1109 rate_section = 0; in _rtl92ee_phy_get_ratesection_intxpower_byrate()
1154 u8 shift = 0, sec, tx_num; in _rtl92ee_get_txpower_by_rate()
1155 s8 diff = 0; in _rtl92ee_get_txpower_by_rate()
1175 shift = 0; in _rtl92ee_get_txpower_by_rate()
1210 shift) & 0xff; in _rtl92ee_get_txpower_by_rate()
1222 u8 tx_power = 0; in _rtl92ee_get_txpower_index()
1223 u8 diff = 0; in _rtl92ee_get_txpower_index()
1226 index = 0; in _rtl92ee_get_txpower_index()
1521 for (i = 0; i < size; i++) { in phy_set_txpower_index_by_rate_array()
1677 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | in rtl92ee_phy_set_bw_mode_callback()
1689 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1690 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1692 (BIT(31) | BIT(30)), 0); in rtl92ee_phy_set_bw_mode_callback()
1695 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1696 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1699 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, in rtl92ee_phy_set_bw_mode_callback()
1702 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92ee_phy_set_bw_mode_callback()
1754 if (delay > 0) in rtl92ee_phy_sw_chnl_callback()
1773 return 0; in rtl92ee_phy_sw_chnl()
1775 return 0; in rtl92ee_phy_sw_chnl()
1779 rtlphy->sw_chnl_stage = 0; in rtl92ee_phy_sw_chnl()
1780 rtlphy->sw_chnl_step = 0; in rtl92ee_phy_sw_chnl()
1811 precommoncmdcnt = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1814 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1816 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1818 postcommoncmdcnt = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1821 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1823 rfdependcmdcnt = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1835 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1839 case 0: in _rtl92ee_phy_sw_chnl_step_by_step()
1858 (*step) = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1879 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92ee_phy_sw_chnl_step_by_step()
1882 0xfffff00) | currentcmd->para2); in _rtl92ee_phy_sw_chnl_step_by_step()
1886 0x3ff, in _rtl92ee_phy_sw_chnl_step_by_step()
1931 u8 result = 0x00; in _rtl92ee_phy_path_a_iqk()
1933 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_a_iqk()
1934 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_iqk()
1935 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_iqk()
1936 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_iqk()
1938 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_iqk()
1939 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1940 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1941 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1943 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); in _rtl92ee_phy_path_a_iqk()
1944 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_a_iqk()
1947 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_a_iqk()
1950 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92ee_phy_path_a_iqk()
1951 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_iqk()
1955 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1956 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1957 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1960 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_a_iqk()
1961 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92ee_phy_path_a_iqk()
1962 result |= 0x01; in _rtl92ee_phy_path_a_iqk()
1972 u8 result = 0x00; in _rtl92ee_phy_path_b_iqk()
1974 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_b_iqk()
1975 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1976 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_iqk()
1977 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1979 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1980 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1982 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1983 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1984 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_iqk()
1985 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1987 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); in _rtl92ee_phy_path_b_iqk()
1988 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_b_iqk()
1991 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_b_iqk()
1994 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_iqk()
1995 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_iqk()
1999 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2000 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2001 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2004 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_b_iqk()
2005 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92ee_phy_path_b_iqk()
2006 result |= 0x01; in _rtl92ee_phy_path_b_iqk()
2016 u8 result = 0x00; in _rtl92ee_phy_path_a_rx_iqk()
2020 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2022 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2023 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2024 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2025 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_a_rx_iqk()
2027 /*PA/PAD control by 0x56, and set = 0x0*/ in _rtl92ee_phy_path_a_rx_iqk()
2028 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2029 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2032 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2035 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_a_rx_iqk()
2036 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2039 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2040 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2041 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2042 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2044 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2045 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2048 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_a_rx_iqk()
2051 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2052 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2062 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_a_rx_iqk()
2063 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) { in _rtl92ee_phy_path_a_rx_iqk()
2064 result |= 0x01; in _rtl92ee_phy_path_a_rx_iqk()
2066 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_a_rx_iqk()
2067 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2068 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2072 u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000) | in _rtl92ee_phy_path_a_rx_iqk()
2073 ((reg_e9c & 0x3FF0000) >> 16); in _rtl92ee_phy_path_a_rx_iqk()
2077 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2079 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2081 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2082 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2083 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_a_rx_iqk()
2085 /*PA/PAD control by 0x56, and set = 0x0*/ in _rtl92ee_phy_path_a_rx_iqk()
2086 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2087 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2090 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2093 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2096 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2097 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2098 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2099 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2101 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2102 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2105 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_a_rx_iqk()
2107 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2108 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2115 /*PA/PAD controlled by 0x0*/ in _rtl92ee_phy_path_a_rx_iqk()
2117 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2118 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2121 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92ee_phy_path_a_rx_iqk()
2122 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl92ee_phy_path_a_rx_iqk()
2123 result |= 0x02; in _rtl92ee_phy_path_a_rx_iqk()
2132 u8 result = 0x00; in _rtl92ee_phy_path_b_rx_iqk()
2136 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2138 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2139 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2140 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2141 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_b_rx_iqk()
2144 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2145 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2147 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2150 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_b_rx_iqk()
2151 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2154 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2155 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2156 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2157 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2159 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2160 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2163 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_b_rx_iqk()
2166 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2167 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2177 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_b_rx_iqk()
2178 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) { in _rtl92ee_phy_path_b_rx_iqk()
2179 result |= 0x01; in _rtl92ee_phy_path_b_rx_iqk()
2181 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_b_rx_iqk()
2182 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2183 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2187 u32temp = 0x80007C00 | (reg_eb4 & 0x3FF0000) | in _rtl92ee_phy_path_b_rx_iqk()
2188 ((reg_ebc & 0x3FF0000) >> 16); in _rtl92ee_phy_path_b_rx_iqk()
2192 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2193 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2195 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2196 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2197 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_b_rx_iqk()
2200 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2201 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2204 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2207 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2210 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2211 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2212 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2213 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2215 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2216 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2219 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_b_rx_iqk()
2221 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2222 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2229 /*PA/PAD controlled by 0x0*/ in _rtl92ee_phy_path_b_rx_iqk()
2231 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2232 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2235 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92ee_phy_path_b_rx_iqk()
2236 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92ee_phy_path_b_rx_iqk()
2237 result |= 0x02; in _rtl92ee_phy_path_b_rx_iqk()
2252 if (final_candidate == 0xFF) { in _rtl92ee_phy_path_a_fill_iqk_matrix()
2256 MASKDWORD) >> 22) & 0x3FF; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2257 x = result[final_candidate][0]; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2258 if ((x & 0x00000200) != 0) in _rtl92ee_phy_path_a_fill_iqk_matrix()
2259 x = x | 0xFFFFFC00; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2261 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2263 ((x * oldval_0 >> 7) & 0x1)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2265 if ((y & 0x00000200) != 0) in _rtl92ee_phy_path_a_fill_iqk_matrix()
2266 y = y | 0xFFFFFC00; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2268 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2269 ((tx0_c & 0x3C0) >> 6)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2270 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2271 (tx0_c & 0x3F)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2273 ((y * oldval_0 >> 7) & 0x1)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2279 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2281 reg = result[final_candidate][3] & 0x3F; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2282 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2284 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2285 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2297 if (final_candidate == 0xFF) { in _rtl92ee_phy_path_b_fill_iqk_matrix()
2301 MASKDWORD) >> 22) & 0x3FF; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2303 if ((x & 0x00000200) != 0) in _rtl92ee_phy_path_b_fill_iqk_matrix()
2304 x = x | 0xFFFFFC00; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2306 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2308 ((x * oldval_1 >> 7) & 0x1)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2310 if ((y & 0x00000200) != 0) in _rtl92ee_phy_path_b_fill_iqk_matrix()
2311 y = y | 0xFFFFFC00; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2313 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2314 ((tx1_c & 0x3C0) >> 6)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2315 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2316 (tx1_c & 0x3F)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2318 ((y * oldval_1 >> 7) & 0x1)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2324 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2326 reg = result[final_candidate][7] & 0x3F; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2327 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2329 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2330 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2340 for (i = 0; i < registernum; i++) in _rtl92ee_phy_save_adda_registers()
2350 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92ee_phy_save_mac_registers()
2362 for (i = 0; i < regiesternum; i++) in _rtl92ee_phy_reload_adda_registers()
2372 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92ee_phy_reload_mac_registers()
2382 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in _rtl92ee_phy_path_adda_on()
2383 rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616); in _rtl92ee_phy_path_adda_on()
2389 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff); in _rtl92ee_phy_mac_setting_calibration()
2394 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92ee_phy_path_a_standby()
2395 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000); in _rtl92ee_phy_path_a_standby()
2396 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_standby()
2404 u8 final_candidate[2] = { 0xFF, 0xFF }; in _rtl92ee_phy_simularity_compare()
2410 simularity_bitmap = 0; in _rtl92ee_phy_simularity_compare()
2412 for (i = 0; i < bound; i++) { in _rtl92ee_phy_simularity_compare()
2414 if ((result[c1][i] & 0x00000200) != 0) in _rtl92ee_phy_simularity_compare()
2415 tmp1 = result[c1][i] | 0xFFFFFC00; in _rtl92ee_phy_simularity_compare()
2419 if ((result[c2][i] & 0x00000200) != 0) in _rtl92ee_phy_simularity_compare()
2420 tmp2 = result[c2][i] | 0xFFFFFC00; in _rtl92ee_phy_simularity_compare()
2432 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92ee_phy_simularity_compare()
2434 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92ee_phy_simularity_compare()
2444 if (simularity_bitmap == 0) { in _rtl92ee_phy_simularity_compare()
2445 for (i = 0; i < (bound / 4); i++) { in _rtl92ee_phy_simularity_compare()
2446 if (final_candidate[i] != 0xFF) { in _rtl92ee_phy_simularity_compare()
2455 if (!(simularity_bitmap & 0x03)) {/*path A TX OK*/ in _rtl92ee_phy_simularity_compare()
2456 for (i = 0; i < 2; i++) in _rtl92ee_phy_simularity_compare()
2459 if (!(simularity_bitmap & 0x0c)) {/*path A RX OK*/ in _rtl92ee_phy_simularity_compare()
2463 if (!(simularity_bitmap & 0x30)) {/*path B TX OK*/ in _rtl92ee_phy_simularity_compare()
2467 if (!(simularity_bitmap & 0xc0)) {/*path B RX OK*/ in _rtl92ee_phy_simularity_compare()
2481 u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0); in _rtl92ee_phy_iq_calibrate()
2482 u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0); in _rtl92ee_phy_iq_calibrate()
2484 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl92ee_phy_iq_calibrate()
2485 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92ee_phy_iq_calibrate()
2486 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92ee_phy_iq_calibrate()
2487 0xed8, 0xedc, 0xee0, 0xeec in _rtl92ee_phy_iq_calibrate()
2490 0x522, 0x550, 0x551, 0x040 in _rtl92ee_phy_iq_calibrate()
2494 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, in _rtl92ee_phy_iq_calibrate()
2495 0x870, 0x860, in _rtl92ee_phy_iq_calibrate()
2496 0x864, 0x800 in _rtl92ee_phy_iq_calibrate()
2500 if (t == 0) { in _rtl92ee_phy_iq_calibrate()
2514 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92ee_phy_iq_calibrate()
2515 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92ee_phy_iq_calibrate()
2516 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92ee_phy_iq_calibrate()
2517 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); in _rtl92ee_phy_iq_calibrate()
2519 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2520 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); in _rtl92ee_phy_iq_calibrate()
2521 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2522 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2528 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2529 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2530 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2532 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2535 if (patha_ok == 0x01) { in _rtl92ee_phy_iq_calibrate()
2538 result[t][0] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2540 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2543 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2548 "Path A Tx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2552 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2555 if (patha_ok == 0x03) { in _rtl92ee_phy_iq_calibrate()
2560 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2564 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2569 "Path A Rx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2573 if (0x00 == patha_ok) in _rtl92ee_phy_iq_calibrate()
2575 "Path A IQK failed!!, ret = 0\n"); in _rtl92ee_phy_iq_calibrate()
2582 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2583 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2584 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2586 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2588 if (pathb_ok == 0x01) { in _rtl92ee_phy_iq_calibrate()
2593 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2597 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2602 "Path B Tx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2606 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2608 if (pathb_ok == 0x03) { in _rtl92ee_phy_iq_calibrate()
2613 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2617 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2622 "Path B Rx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2626 if (0x00 == pathb_ok) in _rtl92ee_phy_iq_calibrate()
2628 "Path B IQK failed!!, ret = 0\n"); in _rtl92ee_phy_iq_calibrate()
2633 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl92ee_phy_iq_calibrate()
2635 if (t != 0) { in _rtl92ee_phy_iq_calibrate()
2650 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2651 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50); in _rtl92ee_phy_iq_calibrate()
2653 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2654 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58); in _rtl92ee_phy_iq_calibrate()
2657 /* load 0xe30 IQC default value */ in _rtl92ee_phy_iq_calibrate()
2658 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2659 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2666 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; in _rtl92ee_phy_lc_calibrate()
2669 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl92ee_phy_lc_calibrate()
2671 if ((tmpreg & 0x70) != 0) in _rtl92ee_phy_lc_calibrate()
2672 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl92ee_phy_lc_calibrate()
2674 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92ee_phy_lc_calibrate()
2676 if ((tmpreg & 0x70) != 0) { in _rtl92ee_phy_lc_calibrate()
2677 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl92ee_phy_lc_calibrate()
2680 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, in _rtl92ee_phy_lc_calibrate()
2683 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2684 (rf_a_mode & 0x8FFFF) | 0x10000); in _rtl92ee_phy_lc_calibrate()
2687 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2688 (rf_b_mode & 0x8FFFF) | 0x10000); in _rtl92ee_phy_lc_calibrate()
2690 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl92ee_phy_lc_calibrate()
2692 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl92ee_phy_lc_calibrate()
2696 if ((tmpreg & 0x70) != 0) { in _rtl92ee_phy_lc_calibrate()
2697 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl92ee_phy_lc_calibrate()
2698 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl92ee_phy_lc_calibrate()
2701 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2704 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92ee_phy_lc_calibrate()
2722 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92ee_phy_set_rfpath_switch()
2727 BIT(5) | BIT(6), 0x1); in _rtl92ee_phy_set_rfpath_switch()
2730 BIT(5) | BIT(6), 0x2); in _rtl92ee_phy_set_rfpath_switch()
2732 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl92ee_phy_set_rfpath_switch()
2733 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl92ee_phy_set_rfpath_switch()
2741 BIT(14) | BIT(13) | BIT(12), 0); in _rtl92ee_phy_set_rfpath_switch()
2743 BIT(5) | BIT(4) | BIT(3), 0); in _rtl92ee_phy_set_rfpath_switch()
2745 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl92ee_phy_set_rfpath_switch()
2779 return 0; in rtl92ee_get_rightchnlplace_for_iqk()
2811 for (i = 0; i < 8; i++) { in rtl92ee_phy_iq_calibrate()
2812 result[0][i] = 0; in rtl92ee_phy_iq_calibrate()
2813 result[1][i] = 0; in rtl92ee_phy_iq_calibrate()
2814 result[2][i] = 0; in rtl92ee_phy_iq_calibrate()
2816 if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) in rtl92ee_phy_iq_calibrate()
2817 result[3][i] = 0x100; in rtl92ee_phy_iq_calibrate()
2819 result[3][i] = 0; in rtl92ee_phy_iq_calibrate()
2821 final_candidate = 0xff; in rtl92ee_phy_iq_calibrate()
2827 for (i = 0; i < 3; i++) { in rtl92ee_phy_iq_calibrate()
2832 0, 1); in rtl92ee_phy_iq_calibrate()
2834 final_candidate = 0; in rtl92ee_phy_iq_calibrate()
2842 0, 2); in rtl92ee_phy_iq_calibrate()
2844 final_candidate = 0; in rtl92ee_phy_iq_calibrate()
2857 reg_e94 = result[3][0]; in rtl92ee_phy_iq_calibrate()
2864 if (final_candidate != 0xff) { in rtl92ee_phy_iq_calibrate()
2865 reg_e94 = result[final_candidate][0]; in rtl92ee_phy_iq_calibrate()
2878 rtlphy->reg_e94 = 0x100; in rtl92ee_phy_iq_calibrate()
2879 rtlphy->reg_eb4 = 0x100; in rtl92ee_phy_iq_calibrate()
2880 rtlphy->reg_e9c = 0x0; in rtl92ee_phy_iq_calibrate()
2881 rtlphy->reg_ebc = 0x0; in rtl92ee_phy_iq_calibrate()
2884 if (reg_e94 != 0) in rtl92ee_phy_iq_calibrate()
2887 (reg_ea4 == 0)); in rtl92ee_phy_iq_calibrate()
2891 (reg_ec4 == 0)); in rtl92ee_phy_iq_calibrate()
2895 /* To Fix BSOD when final_candidate is 0xff */ in rtl92ee_phy_iq_calibrate()
2897 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl92ee_phy_iq_calibrate()
2898 rtlphy->iqk_matrix[idx].value[0][i] = in rtl92ee_phy_iq_calibrate()
2912 u32 timeout = 2000, timecount = 0; in rtl92ee_phy_lc_calibrate()
2995 rtl92ee_dm_write_dig(hw, 0x17); in rtl92ee_phy_set_io()
2997 rtl92ee_dm_write_cck_cca_thres(hw, 0x40); in rtl92ee_phy_set_io()
3014 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl92ee_phy_set_rf_on()
3015 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ee_phy_set_rf_on()
3016 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ in rtl92ee_phy_set_rf_on()
3017 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92ee_phy_set_rf_on()
3018 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ee_phy_set_rf_on()
3019 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl92ee_phy_set_rf_on()
3026 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92ee_phy_set_rf_sleep()
3027 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92ee_phy_set_rf_sleep()
3029 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92ee_phy_set_rf_sleep()
3030 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92ee_phy_set_rf_sleep()
3049 u32 initializecount = 0; in _rtl92ee_phy_set_rf_power_state()
3072 for (queue_id = 0, i = 0; in _rtl92ee_phy_set_rf_power_state()
3076 skb_queue_len(&ring->queue) == 0) { in _rtl92ee_phy_set_rf_power_state()
3116 for (queue_id = 0, i = 0; in _rtl92ee_phy_set_rf_power_state()
3119 if (skb_queue_len(&ring->queue) == 0) { in _rtl92ee_phy_set_rf_power_state()