Lines Matching refs:rtl_set_bbreg
295 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, in _rtl92du_phy_config_bb()
305 rtl_set_bbreg(hw, agctab_array_table[i], in _rtl92du_phy_config_bb()
431 rtl_set_bbreg(hw, REG_AFE_XTAL_CTRL, 0xf0, in rtl92du_phy_bb_config()
433 rtl_set_bbreg(hw, REG_AFE_PLL_CTRL, 0xf0000000, in rtl92du_phy_bb_config()
557 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92du_phy_set_bw_mode()
559 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | BIT(11), 3); in rtl92du_phy_set_bw_mode()
563 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92du_phy_set_bw_mode()
568 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, in rtl92du_phy_set_bw_mode()
570 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92du_phy_set_bw_mode()
572 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, in rtl92du_phy_set_bw_mode()
574 rtl_set_bbreg(hw, 0x818, BIT(26) | BIT(27), in rtl92du_phy_set_bw_mode()
593 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92du_phy_stop_trx_before_changeband()
594 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92du_phy_stop_trx_before_changeband()
670 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92du_phy_reload_imr_setting()
674 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92du_phy_reload_imr_setting()
677 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92du_phy_reload_imr_setting()
688 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92du_phy_reload_imr_setting()
704 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92du_phy_reload_imr_setting()
714 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92du_phy_reload_imr_setting()
970 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1f); in _rtl92du_phy_patha_iqk()
971 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1f); in _rtl92du_phy_patha_iqk()
973 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c22); in _rtl92du_phy_patha_iqk()
974 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c22); in _rtl92du_phy_patha_iqk()
976 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140102); in _rtl92du_phy_patha_iqk()
977 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, in _rtl92du_phy_patha_iqk()
981 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x10008c22); in _rtl92du_phy_patha_iqk()
982 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x10008c22); in _rtl92du_phy_patha_iqk()
983 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140102); in _rtl92du_phy_patha_iqk()
984 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160206); in _rtl92du_phy_patha_iqk()
989 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92du_phy_patha_iqk()
993 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92du_phy_patha_iqk()
994 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92du_phy_patha_iqk()
1049 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); in _rtl92du_phy_patha_iqk_5g_normal()
1050 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); in _rtl92du_phy_patha_iqk_5g_normal()
1051 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140307); in _rtl92du_phy_patha_iqk_5g_normal()
1052 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160960); in _rtl92du_phy_patha_iqk_5g_normal()
1055 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); in _rtl92du_phy_patha_iqk_5g_normal()
1056 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); in _rtl92du_phy_patha_iqk_5g_normal()
1057 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); in _rtl92du_phy_patha_iqk_5g_normal()
1058 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68110000); in _rtl92du_phy_patha_iqk_5g_normal()
1063 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92du_phy_patha_iqk_5g_normal()
1066 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92du_phy_patha_iqk_5g_normal()
1067 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92du_phy_patha_iqk_5g_normal()
1073 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92du_phy_patha_iqk_5g_normal()
1074 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92du_phy_patha_iqk_5g_normal()
1123 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92du_phy_patha_iqk_5g_normal()
1125 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, in _rtl92du_phy_patha_iqk_5g_normal()
1129 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); in _rtl92du_phy_patha_iqk_5g_normal()
1132 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in _rtl92du_phy_patha_iqk_5g_normal()
1133 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); in _rtl92du_phy_patha_iqk_5g_normal()
1151 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000002); in _rtl92du_phy_pathb_iqk()
1152 rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000000); in _rtl92du_phy_pathb_iqk()
1199 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); in _rtl92du_phy_pathb_iqk_5g_normal()
1200 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); in _rtl92du_phy_pathb_iqk_5g_normal()
1201 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); in _rtl92du_phy_pathb_iqk_5g_normal()
1202 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68110000); in _rtl92du_phy_pathb_iqk_5g_normal()
1205 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); in _rtl92du_phy_pathb_iqk_5g_normal()
1206 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); in _rtl92du_phy_pathb_iqk_5g_normal()
1207 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140307); in _rtl92du_phy_pathb_iqk_5g_normal()
1208 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160960); in _rtl92du_phy_pathb_iqk_5g_normal()
1212 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92du_phy_pathb_iqk_5g_normal()
1215 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92du_phy_pathb_iqk_5g_normal()
1216 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92du_phy_pathb_iqk_5g_normal()
1222 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92du_phy_pathb_iqk_5g_normal()
1223 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92du_phy_pathb_iqk_5g_normal()
1270 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92du_phy_pathb_iqk_5g_normal()
1272 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, in _rtl92du_phy_pathb_iqk_5g_normal()
1276 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); in _rtl92du_phy_pathb_iqk_5g_normal()
1279 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in _rtl92du_phy_pathb_iqk_5g_normal()
1280 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); in _rtl92du_phy_pathb_iqk_5g_normal()
1303 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, 0x50); in _rtl92du_phy_reload_adda_registers()
1305 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); in _rtl92du_phy_reload_adda_registers()
1327 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x0); in _rtl92du_phy_patha_standby()
1328 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92du_phy_patha_standby()
1329 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); in _rtl92du_phy_patha_standby()
1340 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, MASKDWORD, mode); in _rtl92du_phy_pimode_switch()
1341 rtl_set_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, MASKDWORD, mode); in _rtl92du_phy_pimode_switch()
1389 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); in _rtl92du_phy_iq_calibrate()
1400 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92du_phy_iq_calibrate()
1401 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92du_phy_iq_calibrate()
1402 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92du_phy_iq_calibrate()
1403 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92du_phy_iq_calibrate()
1405 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, in _rtl92du_phy_iq_calibrate()
1407 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, in _rtl92du_phy_iq_calibrate()
1416 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); in _rtl92du_phy_iq_calibrate()
1418 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); in _rtl92du_phy_iq_calibrate()
1422 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); in _rtl92du_phy_iq_calibrate()
1423 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92du_phy_iq_calibrate()
1424 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92du_phy_iq_calibrate()
1492 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); in _rtl92du_phy_iq_calibrate()
1518 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92du_phy_iq_calibrate()
1519 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92du_phy_iq_calibrate()
1598 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92du_phy_iq_calibrate_5g_normal()
1599 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92du_phy_iq_calibrate_5g_normal()
1600 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92du_phy_iq_calibrate_5g_normal()
1601 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92du_phy_iq_calibrate_5g_normal()
1604 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0); in _rtl92du_phy_iq_calibrate_5g_normal()
1605 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); in _rtl92du_phy_iq_calibrate_5g_normal()
1608 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0); in _rtl92du_phy_iq_calibrate_5g_normal()
1609 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); in _rtl92du_phy_iq_calibrate_5g_normal()
1614 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); in _rtl92du_phy_iq_calibrate_5g_normal()
1615 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x10007c00); in _rtl92du_phy_iq_calibrate_5g_normal()
1616 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92du_phy_iq_calibrate_5g_normal()
1638 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); in _rtl92du_phy_iq_calibrate_5g_normal()
1643 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); in _rtl92du_phy_iq_calibrate_5g_normal()
1680 rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0); in _rtl92du_phy_iq_calibrate_5g_normal()
1692 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x010170b8); in _rtl92du_phy_iq_calibrate_5g_normal()
1694 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x010170b8); in _rtl92du_phy_iq_calibrate_5g_normal()
1803 rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF0000, val_x); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1804 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1816 rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF, val_y); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1817 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 0); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1828 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1830 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1832 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1837 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1838 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1839 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); in _rtl92du_phy_patha_fill_iqk_matrix_5g_normal()
1877 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92du_phy_patha_fill_iqk_matrix()
1878 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), in _rtl92du_phy_patha_fill_iqk_matrix()
1895 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, (tx0_c & 0x3C0) >> 6); in _rtl92du_phy_patha_fill_iqk_matrix()
1896 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, tx0_c & 0x3F); in _rtl92du_phy_patha_fill_iqk_matrix()
1898 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), in _rtl92du_phy_patha_fill_iqk_matrix()
1911 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92du_phy_patha_fill_iqk_matrix()
1913 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92du_phy_patha_fill_iqk_matrix()
1915 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); in _rtl92du_phy_patha_fill_iqk_matrix()
1937 rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF0000, val_x); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1938 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 0); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1950 rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF, val_y); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1951 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 0); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1962 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1964 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1966 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1971 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1972 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
1973 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); in _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal()
2008 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92du_phy_pathb_fill_iqk_matrix()
2009 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), in _rtl92du_phy_pathb_fill_iqk_matrix()
2023 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, (tx1_c & 0x3C0) >> 6); in _rtl92du_phy_pathb_fill_iqk_matrix()
2024 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, tx1_c & 0x3F); in _rtl92du_phy_pathb_fill_iqk_matrix()
2025 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), in _rtl92du_phy_pathb_fill_iqk_matrix()
2032 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92du_phy_pathb_fill_iqk_matrix()
2034 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92du_phy_pathb_fill_iqk_matrix()
2036 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92du_phy_pathb_fill_iqk_matrix()
2312 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92du_phy_lc_calibrate_sw()
2355 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92du_phy_lc_calibrate_sw()
2761 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92du_update_bbrf_configuration()
2762 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92du_update_bbrf_configuration()
2764 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92du_update_bbrf_configuration()
2765 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92du_update_bbrf_configuration()
2769 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92du_update_bbrf_configuration()
2772 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92du_update_bbrf_configuration()
2775 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92du_update_bbrf_configuration()
2778 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92du_update_bbrf_configuration()
2779 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92du_update_bbrf_configuration()
2781 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92du_update_bbrf_configuration()
2786 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92du_update_bbrf_configuration()
2791 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92du_update_bbrf_configuration()
2793 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); in rtl92du_update_bbrf_configuration()
2794 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); in rtl92du_update_bbrf_configuration()
2796 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92du_update_bbrf_configuration()
2805 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92du_update_bbrf_configuration()
2810 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in rtl92du_update_bbrf_configuration()
2815 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92du_update_bbrf_configuration()
2818 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); in rtl92du_update_bbrf_configuration()
2819 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017038); in rtl92du_update_bbrf_configuration()
2820 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); in rtl92du_update_bbrf_configuration()
2821 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); in rtl92du_update_bbrf_configuration()
2826 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92du_update_bbrf_configuration()
2827 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92du_update_bbrf_configuration()
2829 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92du_update_bbrf_configuration()
2830 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92du_update_bbrf_configuration()
2834 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92du_update_bbrf_configuration()
2837 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92du_update_bbrf_configuration()
2840 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92du_update_bbrf_configuration()
2844 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92du_update_bbrf_configuration()
2847 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92du_update_bbrf_configuration()
2852 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, in rtl92du_update_bbrf_configuration()
2855 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, in rtl92du_update_bbrf_configuration()
2859 rtl_set_bbreg(hw, 0xB30, BIT(27), 0); in rtl92du_update_bbrf_configuration()
2862 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92du_update_bbrf_configuration()
2865 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92du_update_bbrf_configuration()
2867 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), in rtl92du_update_bbrf_configuration()
2870 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); in rtl92du_update_bbrf_configuration()
2871 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); in rtl92du_update_bbrf_configuration()
2873 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92du_update_bbrf_configuration()
2878 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92du_update_bbrf_configuration()
2880 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), in rtl92du_update_bbrf_configuration()
2882 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92du_update_bbrf_configuration()
2887 rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); in rtl92du_update_bbrf_configuration()
2888 rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017098); in rtl92du_update_bbrf_configuration()
2889 rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); in rtl92du_update_bbrf_configuration()
2890 rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); in rtl92du_update_bbrf_configuration()
2895 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92du_update_bbrf_configuration()
2896 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92du_update_bbrf_configuration()
2897 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); in rtl92du_update_bbrf_configuration()
2898 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | in rtl92du_update_bbrf_configuration()
2900 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); in rtl92du_update_bbrf_configuration()
2901 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, 0x00); in rtl92du_update_bbrf_configuration()
2902 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92du_update_bbrf_configuration()
2947 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92du_update_bbrf_configuration()
2948 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92du_update_bbrf_configuration()
2952 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | in rtl92du_update_bbrf_configuration()
2956 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, in rtl92du_update_bbrf_configuration()
2961 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x0); in rtl92du_update_bbrf_configuration()
2965 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92du_update_bbrf_configuration()
2966 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92du_update_bbrf_configuration()
2968 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92du_update_bbrf_configuration()
2970 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x1); in rtl92du_update_bbrf_configuration()