112 		rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);  in rtl92du_set_hw_reg()
155 		rtl_write_dword(rtlpriv, REG_TSFTR,  in rtl92du_set_hw_reg()
157 		rtl_write_dword(rtlpriv, REG_TSFTR + 4,  in rtl92du_set_hw_reg()
229 	rtl_write_dword(rtlpriv, REG_RQPN, value32);  in _rtl92du_init_queue_reserved_page()
418 	rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);  in _rtl92du_init_wmac_setting()
421 	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);  in _rtl92du_init_wmac_setting()
422 	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);  in _rtl92du_init_wmac_setting()
436 	rtl_write_dword(rtlpriv, REG_RRSR, val32);  in _rtl92du_init_adaptive_ctrl()
462 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);  in _rtl92du_init_edca()
465 	rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);  in _rtl92du_init_edca()
466 	rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);  in _rtl92du_init_edca()
467 	rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);  in _rtl92du_init_edca()
468 	rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);  in _rtl92du_init_edca()
532 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66525541);  in _rtl92du_init_ampdu_aggregation()
534 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x44444441);  in _rtl92du_init_ampdu_aggregation()
536 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x88728841);  in _rtl92du_init_ampdu_aggregation()
697 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);  in rtl92du_hw_init()
698 	rtl_write_dword(rtlpriv, REG_HIMR, 0xffffffff);  in rtl92du_hw_init()
709 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);  in rtl92du_hw_init()
710 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x10080404);  in rtl92du_hw_init()
711 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);  in rtl92du_hw_init()
712 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x08070605);  in rtl92du_hw_init()
732 	rtl_write_dword(rtlpriv, REG_TXDMA_OFFSET_CHK, val32);  in rtl92du_hw_init()
741 		rtl_write_dword(rtlpriv, REG_ARFR0 + i * 4, 0x1f8ffff0);  in rtl92du_hw_init()
745 			rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03066666);  in rtl92du_hw_init()
830 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0xffff);  in rtl92du_hw_init()
862 		rtl_write_dword(rtlpriv, RFPGA1_TXINFO,  in rtl92du_hw_init()
865 		rtl_write_dword(rtlpriv, RFPGA0_TXGAINSTAGE,  in rtl92du_hw_init()
868 		rtl_write_dword(rtlpriv, ROFDM0_XBTXAFE, 0xa0e40000);  in rtl92du_hw_init()
873 	rtl_write_dword(rtlpriv, REG_FWHW_TXQ_CTRL, val32);  in rtl92du_hw_init()
1067 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, val32);  in _rtl92du_poweroff_adapter()
1153 		rtl_write_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER, val32);  in rtl92du_card_disable()