Lines Matching refs:rtl_set_bbreg
293 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
304 rtl_set_bbreg(hw, agctab_array_table[i], in _rtl92d_phy_config_bb_with_headerfile()
320 rtl_set_bbreg(hw, agctab_array_table[i], in _rtl92d_phy_config_bb_with_headerfile()
335 rtl_set_bbreg(hw, in _rtl92d_phy_config_bb_with_headerfile()
558 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
559 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
561 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | in rtl92d_phy_set_bw_mode()
565 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
566 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
571 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, in rtl92d_phy_set_bw_mode()
575 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92d_phy_set_bw_mode()
577 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | in rtl92d_phy_set_bw_mode()
579 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92d_phy_set_bw_mode()
596 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
597 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
598 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92d_phy_stop_trx_before_changeband()
599 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92d_phy_stop_trx_before_changeband()
631 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92d_phy_switch_wirelessband()
632 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92d_phy_switch_wirelessband()
667 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
668 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
671 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92d_phy_reload_imr_setting()
674 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92d_phy_reload_imr_setting()
683 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
684 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); in _rtl92d_phy_reload_imr_setting()
696 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
697 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92d_phy_reload_imr_setting()
706 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92d_phy_reload_imr_setting()
708 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); in _rtl92d_phy_reload_imr_setting()
900 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
901 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
903 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
904 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
906 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
907 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
910 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
911 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
912 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
913 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
917 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
920 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
921 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
970 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
971 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
972 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
973 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
976 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
977 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
978 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
979 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
983 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
985 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
986 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
991 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
992 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1027 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1029 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1044 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1045 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1087 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1088 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1089 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1090 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1093 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1094 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1095 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1096 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1100 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1103 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1104 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1110 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1111 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1145 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1147 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1162 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); in _rtl92d_phy_reload_adda_registers()
1182 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1183 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1184 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1195 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1196 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1251 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate()
1252 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1253 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1254 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1255 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate()
1257 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1259 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1266 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1268 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1271 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1272 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1273 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1338 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1358 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1359 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1425 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate_5g_normal()
1426 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1427 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1428 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1429 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate_5g_normal()
1432 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1434 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1437 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1438 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1439 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
1494 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
1602 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92d_phy_patha_fill_iqk_matrix()
1603 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), in _rtl92d_phy_patha_fill_iqk_matrix()
1616 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92d_phy_patha_fill_iqk_matrix()
1618 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_patha_fill_iqk_matrix()
1621 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), in _rtl92d_phy_patha_fill_iqk_matrix()
1631 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
1633 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
1635 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
1660 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92d_phy_pathb_fill_iqk_matrix()
1661 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), in _rtl92d_phy_pathb_fill_iqk_matrix()
1671 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92d_phy_pathb_fill_iqk_matrix()
1673 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_pathb_fill_iqk_matrix()
1675 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), in _rtl92d_phy_pathb_fill_iqk_matrix()
1680 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
1682 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
1684 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
1943 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92d_phy_lc_calibrate_sw()
2023 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2522 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
2523 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
2525 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
2526 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
2529 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92d_update_bbrf_configuration()
2531 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92d_update_bbrf_configuration()
2533 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92d_update_bbrf_configuration()
2535 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
2537 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
2540 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
2545 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
2550 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
2552 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
2561 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
2566 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
2571 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()
2577 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
2578 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
2580 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
2581 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
2584 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92d_update_bbrf_configuration()
2586 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92d_update_bbrf_configuration()
2588 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92d_update_bbrf_configuration()
2591 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
2594 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
2597 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
2600 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
2603 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
2606 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
2608 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), in rtl92d_update_bbrf_configuration()
2611 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
2616 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
2618 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
2620 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()
2627 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
2628 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
2629 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
2630 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | in rtl92d_update_bbrf_configuration()
2632 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
2633 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
2634 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92d_update_bbrf_configuration()
2657 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92d_update_bbrf_configuration()
2658 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92d_update_bbrf_configuration()
2662 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | in rtl92d_update_bbrf_configuration()
2679 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92d_update_bbrf_configuration()
2680 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92d_update_bbrf_configuration()
2682 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92d_update_bbrf_configuration()