495 					RFREG_OFFSET_MASK,  in rtl92d_phy_config_rf_with_headerfile()
502 					RFREG_OFFSET_MASK,  in rtl92d_phy_config_rf_with_headerfile()
660 	u32 rfmask = RFREG_OFFSET_MASK;  in _rtl92d_phy_reload_imr_setting()
703 					      RFREG_OFFSET_MASK,  in _rtl92d_phy_reload_imr_setting()
762 					      RFREG_OFFSET_MASK, 0xE439D);  in _rtl92d_phy_switch_rf_setting()
770 					      RFREG_OFFSET_MASK, u4tmp2);  in _rtl92d_phy_switch_rf_setting()
774 					      RFREG_OFFSET_MASK,  in _rtl92d_phy_switch_rf_setting()
784 					      RFREG_OFFSET_MASK));  in _rtl92d_phy_switch_rf_setting()
814 						RFREG_OFFSET_MASK,  in _rtl92d_phy_switch_rf_setting()
855 					RFREG_OFFSET_MASK,  in _rtl92d_phy_switch_rf_setting()
861 					      RFREG_OFFSET_MASK,  in _rtl92d_phy_switch_rf_setting()
871 					      RFREG_OFFSET_MASK));  in _rtl92d_phy_switch_rf_setting()
878 			      RFREG_OFFSET_MASK,  in _rtl92d_phy_switch_rf_setting()
1950 			      RFREG_OFFSET_MASK, 0x010000);  in _rtl92d_phy_lc_calibrate_sw()
1960 				  RFREG_OFFSET_MASK);  in _rtl92d_phy_lc_calibrate_sw()
1965 					      RF_SYN_G6, RFREG_OFFSET_MASK);  in _rtl92d_phy_lc_calibrate_sw()
1969 		rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);  in _rtl92d_phy_lc_calibrate_sw()
1989 				RFREG_OFFSET_MASK, 0x0);  in _rtl92d_phy_lc_calibrate_sw()
1991 					  0x4F, RFREG_OFFSET_MASK);  in _rtl92d_phy_lc_calibrate_sw()
2177 					      RFREG_OFFSET_MASK,  in _rtl92d_phy_sw_chnl_step_by_step()
2307 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);  in _rtl92d_phy_set_rfsleep()
2315 	u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);  in _rtl92d_phy_set_rfsleep()
2318 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);  in _rtl92d_phy_set_rfsleep()
2320 		u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);  in _rtl92d_phy_set_rfsleep()
2687 						RF_CHNLBW, RFREG_OFFSET_MASK);  in rtl92d_update_bbrf_configuration()
2689 			RFREG_OFFSET_MASK);  in rtl92d_update_bbrf_configuration()