Lines Matching +full:0 +full:x80800000
29 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
41 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
62 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
70 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
75 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
78 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
80 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
88 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
89 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
93 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
94 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
95 0x32c9a
99 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
100 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
172 u8 dbi_direct = 0; in rtl92d_phy_query_bb_reg()
188 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92d_phy_query_bb_reg()
198 u8 dbi_direct = 0; in rtl92d_phy_set_bb_reg()
240 for (i = 0; i < arraylength; i = i + 2) in rtl92d_phy_mac_config()
244 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ in rtl92d_phy_mac_config()
247 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); in rtl92d_phy_mac_config()
250 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); in rtl92d_phy_mac_config()
262 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; in _rtl92d_phy_config_bb_with_headerfile()
267 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
291 for (i = 0; i < phy_reg_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
297 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", in _rtl92d_phy_config_bb_with_headerfile()
302 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
303 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
311 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
319 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
327 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
334 for (i = 0; i < agctab_5garraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
343 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
366 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { in _rtl92d_phy_config_bb_with_pgheaderfile()
401 rtlphy->pwrgroup_cnt = 0; in _rtl92d_phy_bb_config()
416 RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl92d_phy_bb_config()
431 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92d_phy_bb_config()
432 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); in rtl92d_phy_bb_config()
433 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); in rtl92d_phy_bb_config()
434 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ in rtl92d_phy_bb_config()
440 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92d_phy_bb_config()
468 if (rtlpriv->efuse.internal_pa_5g[0]) { in rtl92d_phy_config_rf_with_headerfile()
483 * mac1 start on 5G, mac 0 has to set phy0&phy1 in rtl92d_phy_config_rf_with_headerfile()
493 for (i = 0; i < radioa_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
500 for (i = 0; i < radiob_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
521 unsigned long flag = 0; in rtl92d_phy_set_bw_mode()
547 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | in rtl92d_phy_set_bw_mode()
558 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
559 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
565 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
566 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
575 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92d_phy_set_bw_mode()
578 BIT(11), 0); in rtl92d_phy_set_bw_mode()
579 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92d_phy_set_bw_mode()
596 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
597 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
598 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92d_phy_stop_trx_before_changeband()
599 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92d_phy_stop_trx_before_changeband()
631 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92d_phy_switch_wirelessband()
632 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92d_phy_switch_wirelessband()
637 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_switch_wirelessband()
640 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
643 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
646 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
649 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
662 unsigned long flag = 0; in _rtl92d_phy_reload_imr_setting()
667 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
668 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
669 /* fc area 0xd2c */ in _rtl92d_phy_reload_imr_setting()
676 /* leave 0 for channel1-14. */ in _rtl92d_phy_reload_imr_setting()
679 for (i = 0; i < imr_num; i++) in _rtl92d_phy_reload_imr_setting()
682 rf_imr_param_normal[0][group][i]); in _rtl92d_phy_reload_imr_setting()
683 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
696 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
698 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
700 for (i = 0; i < imr_num; i++) { in _rtl92d_phy_reload_imr_setting()
704 rf_imr_param_normal[0][0][i]); in _rtl92d_phy_reload_imr_setting()
707 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
722 u8 index = 0, i = 0, rfpath = RF90_PATH_A; in _rtl92d_phy_switch_rf_setting()
724 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; in _rtl92d_phy_switch_rf_setting()
732 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
733 for (i = 0; i < RF_CHNL_NUM_5G; i++) { in _rtl92d_phy_switch_rf_setting()
735 index = 0; in _rtl92d_phy_switch_rf_setting()
737 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { in _rtl92d_phy_switch_rf_setting()
758 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { in _rtl92d_phy_switch_rf_setting()
759 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { in _rtl92d_phy_switch_rf_setting()
762 RFREG_OFFSET_MASK, 0xE439D); in _rtl92d_phy_switch_rf_setting()
765 0x7FF) | (u4tmp << 11); in _rtl92d_phy_switch_rf_setting()
778 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
791 value = 0x07; in _rtl92d_phy_switch_rf_setting()
793 value = 0x02; in _rtl92d_phy_switch_rf_setting()
795 index = 0; in _rtl92d_phy_switch_rf_setting()
809 for (i = 0; in _rtl92d_phy_switch_rf_setting()
817 "offset 0x%x value 0x%x path %d index %d\n", in _rtl92d_phy_switch_rf_setting()
823 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in _rtl92d_phy_switch_rf_setting()
831 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
834 index = 0; in _rtl92d_phy_switch_rf_setting()
841 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_switch_rf_setting()
851 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { in _rtl92d_phy_switch_rf_setting()
865 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
874 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_switch_rf_setting()
894 u8 result = 0; in _rtl92d_phy_patha_iqk()
899 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_patha_iqk()
900 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
901 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
903 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
904 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
906 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
907 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
910 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
911 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
912 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
913 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
917 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
920 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
921 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
928 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk()
929 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk()
930 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk()
931 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk()
932 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk()
933 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk()
934 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk()
935 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk()
936 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_patha_iqk()
937 (((rege9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_patha_iqk()
938 result |= 0x01; in _rtl92d_phy_patha_iqk()
942 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_patha_iqk()
943 (((regeac & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_patha_iqk()
944 result |= 0x02; in _rtl92d_phy_patha_iqk()
958 u8 result = 0; in _rtl92d_phy_patha_iqk_5g_normal()
970 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
971 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
972 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
973 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
976 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
977 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
978 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
979 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
983 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
985 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
986 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
987 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_patha_iqk_5g_normal()
991 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
992 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
999 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1000 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk_5g_normal()
1001 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1002 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk_5g_normal()
1003 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1004 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk_5g_normal()
1005 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1006 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk_5g_normal()
1008 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { in _rtl92d_phy_patha_iqk_5g_normal()
1009 result |= 0x01; in _rtl92d_phy_patha_iqk_5g_normal()
1018 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_patha_iqk_5g_normal()
1019 result |= 0x02; in _rtl92d_phy_patha_iqk_5g_normal()
1028 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_patha_iqk_5g_normal()
1039 u8 result = 0; in _rtl92d_phy_pathb_iqk()
1044 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1045 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1051 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1052 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk()
1053 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1054 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk()
1055 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1056 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk()
1057 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1058 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk()
1059 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1060 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk()
1061 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_pathb_iqk()
1062 (((regebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_pathb_iqk()
1063 result |= 0x01; in _rtl92d_phy_pathb_iqk()
1066 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_pathb_iqk()
1067 (((regecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_pathb_iqk()
1068 result |= 0x02; in _rtl92d_phy_pathb_iqk()
1080 u8 result = 0; in _rtl92d_phy_pathb_iqk_5g_normal()
1087 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1088 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1089 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1090 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1093 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1094 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1095 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1096 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1100 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1103 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1104 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1106 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_pathb_iqk_5g_normal()
1110 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1111 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1119 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1120 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk_5g_normal()
1121 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1122 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk_5g_normal()
1123 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1124 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk_5g_normal()
1125 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1126 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk_5g_normal()
1127 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1128 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk_5g_normal()
1130 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) in _rtl92d_phy_pathb_iqk_5g_normal()
1131 result |= 0x01; in _rtl92d_phy_pathb_iqk_5g_normal()
1135 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_pathb_iqk_5g_normal()
1136 result |= 0x02; in _rtl92d_phy_pathb_iqk_5g_normal()
1146 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_pathb_iqk_5g_normal()
1161 for (i = 0; i < regnum; i++) in _rtl92d_phy_reload_adda_registers()
1172 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92d_phy_reload_mac_registers()
1182 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1183 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1184 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1194 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl92d_phy_pimode_switch()
1195 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1196 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1207 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate()
1208 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate()
1209 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate()
1210 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate()
1213 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate()
1226 if (t == 0) { in _rtl92d_phy_iq_calibrate()
1228 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate()
1243 if (t == 0) in _rtl92d_phy_iq_calibrate()
1251 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate()
1252 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1253 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1254 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1255 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate()
1258 0x00010000); in _rtl92d_phy_iq_calibrate()
1260 0x00010000); in _rtl92d_phy_iq_calibrate()
1266 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1268 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1271 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1272 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1273 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1274 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1276 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1279 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1280 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1281 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1282 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1283 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1284 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1285 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1286 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1288 } else if (i == (retrycount - 1) && patha_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1293 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1294 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1295 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1296 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1299 if (0x00 == patha_ok) in _rtl92d_phy_iq_calibrate()
1305 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1307 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1310 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1311 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1312 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1313 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1314 result[t][6] = (rtl_get_bbreg(hw, 0xec4, in _rtl92d_phy_iq_calibrate()
1315 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1316 result[t][7] = (rtl_get_bbreg(hw, 0xecc, in _rtl92d_phy_iq_calibrate()
1317 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1319 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1323 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1324 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1325 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1326 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1329 if (0x00 == pathb_ok) in _rtl92d_phy_iq_calibrate()
1338 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1339 if (t != 0) { in _rtl92d_phy_iq_calibrate()
1357 /* load 0xe30 IQC default value */ in _rtl92d_phy_iq_calibrate()
1358 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1359 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1372 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate_5g_normal()
1373 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate_5g_normal()
1374 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate_5g_normal()
1375 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate_5g_normal()
1378 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate_5g_normal()
1395 if (t == 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
1397 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate_5g_normal()
1419 if (t == 0) in _rtl92d_phy_iq_calibrate_5g_normal()
1425 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate_5g_normal()
1426 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1427 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1428 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1429 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate_5g_normal()
1432 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1434 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1437 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1438 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1439 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
1441 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
1443 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1444 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1445 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1446 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1447 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1448 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1449 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1450 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1451 } else if (patha_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
1455 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1456 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1457 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1458 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1467 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
1470 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1471 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1472 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1473 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1474 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1475 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1476 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1477 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1478 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
1481 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1482 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1483 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1484 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1494 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
1495 if (t != 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
1524 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ in _rtl92d_phy_simularity_compare()
1532 sim_bitmap = 0; in _rtl92d_phy_simularity_compare()
1533 for (i = 0; i < bound; i++) { in _rtl92d_phy_simularity_compare()
1538 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92d_phy_simularity_compare()
1540 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92d_phy_simularity_compare()
1549 if (sim_bitmap == 0) { in _rtl92d_phy_simularity_compare()
1550 for (i = 0; i < (bound / 4); i++) { in _rtl92d_phy_simularity_compare()
1551 if (final_candidate[i] != 0xFF) { in _rtl92d_phy_simularity_compare()
1560 if (!(sim_bitmap & 0x0F)) { /* path A OK */ in _rtl92d_phy_simularity_compare()
1561 for (i = 0; i < 4; i++) in _rtl92d_phy_simularity_compare()
1563 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ in _rtl92d_phy_simularity_compare()
1564 for (i = 0; i < 2; i++) in _rtl92d_phy_simularity_compare()
1567 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ in _rtl92d_phy_simularity_compare()
1570 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ in _rtl92d_phy_simularity_compare()
1590 if (final_candidate == 0xFF) { in _rtl92d_phy_patha_fill_iqk_matrix()
1594 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ in _rtl92d_phy_patha_fill_iqk_matrix()
1595 val_x = result[final_candidate][0]; in _rtl92d_phy_patha_fill_iqk_matrix()
1596 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
1597 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
1600 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
1602 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92d_phy_patha_fill_iqk_matrix()
1604 ((val_x * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
1606 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
1607 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
1614 "Y = 0x%lx, tx0_c = 0x%lx\n", in _rtl92d_phy_patha_fill_iqk_matrix()
1616 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92d_phy_patha_fill_iqk_matrix()
1617 ((tx0_c & 0x3C0) >> 6)); in _rtl92d_phy_patha_fill_iqk_matrix()
1618 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_patha_fill_iqk_matrix()
1619 (tx0_c & 0x3F)); in _rtl92d_phy_patha_fill_iqk_matrix()
1622 ((val_y * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
1623 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
1631 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
1632 reg = result[final_candidate][3] & 0x3F; in _rtl92d_phy_patha_fill_iqk_matrix()
1633 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
1634 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92d_phy_patha_fill_iqk_matrix()
1635 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
1649 if (final_candidate == 0xFF) { in _rtl92d_phy_pathb_fill_iqk_matrix()
1653 MASKDWORD) >> 22) & 0x3FF; in _rtl92d_phy_pathb_fill_iqk_matrix()
1655 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
1656 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
1658 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
1660 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92d_phy_pathb_fill_iqk_matrix()
1662 ((val_x * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
1664 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
1665 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
1669 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
1671 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92d_phy_pathb_fill_iqk_matrix()
1672 ((tx1_c & 0x3C0) >> 6)); in _rtl92d_phy_pathb_fill_iqk_matrix()
1673 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_pathb_fill_iqk_matrix()
1674 (tx1_c & 0x3F)); in _rtl92d_phy_pathb_fill_iqk_matrix()
1676 ((val_y * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
1680 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
1681 reg = result[final_candidate][7] & 0x3F; in _rtl92d_phy_pathb_fill_iqk_matrix()
1682 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
1683 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92d_phy_pathb_fill_iqk_matrix()
1684 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
1697 long regebc, regec4, regecc, regtmp = 0; in rtl92d_phy_iq_calibrate()
1699 unsigned long flag = 0; in rtl92d_phy_iq_calibrate()
1703 for (i = 0; i < 8; i++) { in rtl92d_phy_iq_calibrate()
1704 result[0][i] = 0; in rtl92d_phy_iq_calibrate()
1705 result[1][i] = 0; in rtl92d_phy_iq_calibrate()
1706 result[2][i] = 0; in rtl92d_phy_iq_calibrate()
1707 result[3][i] = 0; in rtl92d_phy_iq_calibrate()
1709 final_candidate = 0xff; in rtl92d_phy_iq_calibrate()
1718 for (i = 0; i < 3; i++) { in rtl92d_phy_iq_calibrate()
1729 0, 1); in rtl92d_phy_iq_calibrate()
1731 final_candidate = 0; in rtl92d_phy_iq_calibrate()
1737 0, 2); in rtl92d_phy_iq_calibrate()
1739 final_candidate = 0; in rtl92d_phy_iq_calibrate()
1747 for (i = 0; i < 8; i++) in rtl92d_phy_iq_calibrate()
1750 if (regtmp != 0) in rtl92d_phy_iq_calibrate()
1753 final_candidate = 0xFF; in rtl92d_phy_iq_calibrate()
1758 for (i = 0; i < 4; i++) { in rtl92d_phy_iq_calibrate()
1759 rege94 = result[i][0]; in rtl92d_phy_iq_calibrate()
1772 if (final_candidate != 0xff) { in rtl92d_phy_iq_calibrate()
1773 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; in rtl92d_phy_iq_calibrate()
1789 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ in rtl92d_phy_iq_calibrate()
1790 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ in rtl92d_phy_iq_calibrate()
1792 if ((rege94 != 0) /*&&(regea4 != 0) */) in rtl92d_phy_iq_calibrate()
1794 final_candidate, (regea4 == 0)); in rtl92d_phy_iq_calibrate()
1796 if ((regeb4 != 0) /*&&(regec4 != 0) */) in rtl92d_phy_iq_calibrate()
1798 final_candidate, (regec4 == 0)); in rtl92d_phy_iq_calibrate()
1800 if (final_candidate != 0xFF) { in rtl92d_phy_iq_calibrate()
1804 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl92d_phy_iq_calibrate()
1806 value[0][i] = result[final_candidate][i]; in rtl92d_phy_iq_calibrate()
1828 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && in rtl92d_phy_reload_iqk_setting()
1838 indexforchannel == 0) || indexforchannel > 0) { in rtl92d_phy_reload_iqk_setting()
1842 if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) in rtl92d_phy_reload_iqk_setting()
1844 rtlphy->iqk_matrix[indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
1845 rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); in rtl92d_phy_reload_iqk_setting()
1848 indexforchannel].value[0][4] != 0) in rtl92d_phy_reload_iqk_setting()
1849 /*&&(regec4 != 0) */) in rtl92d_phy_reload_iqk_setting()
1853 indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
1855 indexforchannel].value[0][6] in rtl92d_phy_reload_iqk_setting()
1856 == 0)); in rtl92d_phy_reload_iqk_setting()
1872 u32 u4tmp = 0, u4regvalue = 0; in _rtl92d_phy_reload_lck_setting()
1882 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
1893 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
1901 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
1903 rtlpriv->rtlhal.interfaceindex == 0) { in _rtl92d_phy_reload_lck_setting()
1911 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
1913 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_reload_lck_setting()
1914 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); in _rtl92d_phy_reload_lck_setting()
1932 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; in _rtl92d_phy_lc_calibrate_sw()
1933 u16 timeout = 800, timecount = 0; in _rtl92d_phy_lc_calibrate_sw()
1936 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl92d_phy_lc_calibrate_sw()
1939 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
1940 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl92d_phy_lc_calibrate_sw()
1942 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_lc_calibrate_sw()
1943 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92d_phy_lc_calibrate_sw()
1944 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
1946 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
1950 RFREG_OFFSET_MASK, 0x010000); in _rtl92d_phy_lc_calibrate_sw()
1954 BIT(17), 0x0); in _rtl92d_phy_lc_calibrate_sw()
1957 0x08000, 0x01); in _rtl92d_phy_lc_calibrate_sw()
1970 if (index == 0 && rtlhal->interfaceindex == 0) { in _rtl92d_phy_lc_calibrate_sw()
1977 memset(curvecount_val, 0, sizeof(curvecount_val)); in _rtl92d_phy_lc_calibrate_sw()
1980 0x08000, 0x0); in _rtl92d_phy_lc_calibrate_sw()
1981 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); in _rtl92d_phy_lc_calibrate_sw()
1983 for (i = 0; i < CV_CURVE_CNT; i++) { in _rtl92d_phy_lc_calibrate_sw()
1984 u32 readval = 0, readval2 = 0; in _rtl92d_phy_lc_calibrate_sw()
1985 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, in _rtl92d_phy_lc_calibrate_sw()
1986 0x7f, i); in _rtl92d_phy_lc_calibrate_sw()
1988 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, in _rtl92d_phy_lc_calibrate_sw()
1989 RFREG_OFFSET_MASK, 0x0); in _rtl92d_phy_lc_calibrate_sw()
1991 0x4F, RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
1992 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; in _rtl92d_phy_lc_calibrate_sw()
1993 /* reg 0x4f [4:0] */ in _rtl92d_phy_lc_calibrate_sw()
1994 /* reg 0x50 [19:10] */ in _rtl92d_phy_lc_calibrate_sw()
1996 0x50, 0xffc00); in _rtl92d_phy_lc_calibrate_sw()
1997 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | in _rtl92d_phy_lc_calibrate_sw()
2000 if (index == 0 && rtlhal->interfaceindex == 0) in _rtl92d_phy_lc_calibrate_sw()
2010 BIT(17), 0x1); in _rtl92d_phy_lc_calibrate_sw()
2014 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
2015 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
2016 rtl_write_byte(rtlpriv, offset, 0x50); in _rtl92d_phy_lc_calibrate_sw()
2019 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
2020 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl92d_phy_lc_calibrate_sw()
2022 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2023 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2040 u32 timeout = 2000, timecount = 0; in rtl92d_phy_lc_calibrate()
2100 precommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2103 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2105 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2106 postcommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2108 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2109 rfdependcmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2112 RF_CHNLBW, channel, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2115 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2119 case 0: in _rtl92d_phy_sw_chnl_step_by_step()
2134 (*step) = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2155 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92d_phy_sw_chnl_step_by_step()
2158 0xffffff00) | currentcmd->para2); in _rtl92d_phy_sw_chnl_step_by_step()
2204 u32 timeout = 1000, timecount = 0; in rtl92d_phy_sw_chnl()
2209 return 0; in rtl92d_phy_sw_chnl()
2211 return 0; in rtl92d_phy_sw_chnl()
2216 return 0; in rtl92d_phy_sw_chnl()
2226 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2228 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2236 return 0; in rtl92d_phy_sw_chnl()
2242 return 0; in rtl92d_phy_sw_chnl()
2250 if (channel == 0) in rtl92d_phy_sw_chnl()
2252 rtlphy->sw_chnl_stage = 0; in rtl92d_phy_sw_chnl()
2253 rtlphy->sw_chnl_step = 0; in rtl92d_phy_sw_chnl()
2263 if (delay > 0) in rtl92d_phy_sw_chnl()
2281 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ in _rtl92d_phy_set_rfon()
2282 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ in _rtl92d_phy_set_rfon()
2284 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92d_phy_set_rfon()
2285 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ in _rtl92d_phy_set_rfon()
2286 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2288 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ in _rtl92d_phy_set_rfon()
2289 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfon()
2290 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ in _rtl92d_phy_set_rfon()
2291 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ in _rtl92d_phy_set_rfon()
2292 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfon()
2293 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2294 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ in _rtl92d_phy_set_rfon()
2295 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfon()
2304 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ in _rtl92d_phy_set_rfsleep()
2305 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_set_rfsleep()
2306 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ in _rtl92d_phy_set_rfsleep()
2307 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
2308 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ in _rtl92d_phy_set_rfsleep()
2309 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
2310 /* d. APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
2311 * APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
2312 * RF path 0 offset 0x00 = 0x00 in _rtl92d_phy_set_rfsleep()
2313 * APSD_CTRL 0x600[7:0] = 0x40 in _rtl92d_phy_set_rfsleep()
2315 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
2316 while (u4btmp != 0 && delay > 0) { in _rtl92d_phy_set_rfsleep()
2317 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl92d_phy_set_rfsleep()
2318 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
2319 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
2320 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
2323 if (delay == 0) { in _rtl92d_phy_set_rfsleep()
2325 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfsleep()
2327 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
2328 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfsleep()
2329 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfsleep()
2334 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ in _rtl92d_phy_set_rfsleep()
2335 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
2336 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ in _rtl92d_phy_set_rfsleep()
2338 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92d_phy_set_rfsleep()
2339 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ in _rtl92d_phy_set_rfsleep()
2362 u32 initializecount = 0; in rtl92d_phy_set_rf_power_state()
2408 for (queue_id = 0, i = 0; in rtl92d_phy_set_rf_power_state()
2411 if (skb_queue_len(&ring->queue) == 0 || in rtl92d_phy_set_rf_power_state()
2417 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", in rtl92d_phy_set_rf_power_state()
2466 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); in rtl92d_phy_set_poweron()
2468 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_set_poweron()
2484 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_set_poweron()
2493 for (i = 0; i < 200; i++) { in rtl92d_phy_set_poweron()
2494 if ((value8 & BIT(7)) == 0) { in rtl92d_phy_set_poweron()
2519 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ in rtl92d_update_bbrf_configuration()
2521 /* r_select_5G for path_A/B,0x878 */ in rtl92d_update_bbrf_configuration()
2522 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
2523 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
2525 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
2526 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
2528 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ in rtl92d_update_bbrf_configuration()
2529 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92d_update_bbrf_configuration()
2530 /* fc_area 0xd2c */ in rtl92d_update_bbrf_configuration()
2531 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92d_update_bbrf_configuration()
2533 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92d_update_bbrf_configuration()
2534 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
2536 0x40000100); in rtl92d_update_bbrf_configuration()
2538 0x40000100); in rtl92d_update_bbrf_configuration()
2548 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
2549 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
2550 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
2564 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
2565 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
2572 BIT(31) | BIT(15), 0); in rtl92d_update_bbrf_configuration()
2577 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
2578 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
2580 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
2581 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
2583 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ in rtl92d_update_bbrf_configuration()
2584 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92d_update_bbrf_configuration()
2586 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92d_update_bbrf_configuration()
2588 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92d_update_bbrf_configuration()
2589 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
2590 if (rtlefuse->internal_pa_5g[0]) in rtl92d_update_bbrf_configuration()
2592 0x2d4000b5); in rtl92d_update_bbrf_configuration()
2595 0x20000080); in rtl92d_update_bbrf_configuration()
2598 0x2d4000b5); in rtl92d_update_bbrf_configuration()
2601 0x20000080); in rtl92d_update_bbrf_configuration()
2627 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
2628 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
2629 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
2631 BIT(26) | BIT(24), 0x00); in rtl92d_update_bbrf_configuration()
2632 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
2633 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
2634 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92d_update_bbrf_configuration()
2640 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
2642 BIT(18), 0); in rtl92d_update_bbrf_configuration()
2644 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in rtl92d_update_bbrf_configuration()
2645 0x1c000, 0x07); in rtl92d_update_bbrf_configuration()
2647 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
2656 /* Use antenna 0,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
2657 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92d_update_bbrf_configuration()
2658 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92d_update_bbrf_configuration()
2661 if (rtlhal->interfaceindex == 0) { in rtl92d_update_bbrf_configuration()
2663 BIT(13), 0x3); in rtl92d_update_bbrf_configuration()
2667 "MAC1 use DBI to update 0x888\n"); in rtl92d_update_bbrf_configuration()
2668 /* 0x888 */ in rtl92d_update_bbrf_configuration()
2678 /* Use antenna 0 & 1,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
2679 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92d_update_bbrf_configuration()
2680 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92d_update_bbrf_configuration()
2681 /* disable ad/da clock1,0x888 */ in rtl92d_update_bbrf_configuration()
2682 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92d_update_bbrf_configuration()
2688 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, in rtl92d_update_bbrf_configuration()
2691 for (i = 0; i < 2; i++) in rtl92d_update_bbrf_configuration()
2692 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", in rtl92d_update_bbrf_configuration()
2711 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_check_poweroff()