Lines Matching +full:pcie +full:- +full:mac
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
52 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92de_set_bcn_ctrl_reg()
53 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; in _rtl92de_set_bcn_ctrl_reg()
54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); in _rtl92de_set_bcn_ctrl_reg()
73 *((u32 *) (val)) = rtlpci->receive_config; in rtl92de_get_hw_reg()
85 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); in rtl92de_set_hw_reg() local
91 if (rtlpci->acm_method != EACMWAY2_SW) in rtl92de_set_hw_reg()
92 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, in rtl92de_set_hw_reg()
99 (union aci_aifsn *)(&(mac->ac[0].aifs)); in rtl92de_set_hw_reg()
100 u8 acm = p_aci_aifsn->f.acm; in rtl92de_set_hw_reg()
103 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92de_set_hw_reg()
146 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92de_set_hw_reg()
154 rtlpriv->cfg->ops->set_hw_reg(hw, in rtl92de_set_hw_reg()
187 (u32) (mac->tsf & 0xffffffff)); in rtl92de_set_hw_reg()
189 (u32) ((mac->tsf >> 32) & 0xffffffff)); in rtl92de_set_hw_reg()
205 rtlpriv->dm.interrupt_migration = int_migration; in rtl92de_set_hw_reg()
209 rtlpriv->dm.interrupt_migration = int_migration; in rtl92de_set_hw_reg()
223 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, in rtl92de_set_hw_reg()
225 rtlpriv->dm.disable_tx_int = disable_ac_int; in rtl92de_set_hw_reg()
228 rtlpriv->cfg->ops->update_interrupt_mask(hw, in rtl92de_set_hw_reg()
230 rtlpriv->dm.disable_tx_int = disable_ac_int; in rtl92de_set_hw_reg()
250 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { in _rtl92de_llt_table_init()
297 for (i = 0; i < (txpktbuf_bndy - 1); i++) { in _rtl92de_llt_table_init()
304 status = rtl92d_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); in _rtl92de_llt_table_init()
310 /* config this MAC as two MAC transfer. */ in _rtl92de_llt_table_init()
331 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0; in _rtl92de_gen_refresh_led_state()
333 if (rtlpci->up_first_time) in _rtl92de_gen_refresh_led_state()
335 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) in _rtl92de_gen_refresh_led_state()
337 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) in _rtl92de_gen_refresh_led_state()
374 /* Power On Reset for MAC Block */ in _rtl92de_init_mac()
406 /* Release MAC IO register reset */ in _rtl92de_init_mac()
430 /* 22. PCIE configuration space configuration */ in _rtl92de_init_mac()
431 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */ in _rtl92de_init_mac()
432 /* and PCIe gated clock function is enabled. */ in _rtl92de_init_mac()
433 /* PCIE configuration space will be written after in _rtl92de_init_mac()
440 /* -------------------Software Relative Setting---------------------- */ in _rtl92de_init_mac()
456 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); in _rtl92de_init_mac()
460 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); in _rtl92de_init_mac()
467 rtlpci->tx_ring[BEACON_QUEUE].dma); in _rtl92de_init_mac()
468 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma); in _rtl92de_init_mac()
469 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma); in _rtl92de_init_mac()
470 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma); in _rtl92de_init_mac()
471 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma); in _rtl92de_init_mac()
472 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma); in _rtl92de_init_mac()
473 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma); in _rtl92de_init_mac()
476 rtlpci->rx_ring[RX_MPDU_QUEUE].dma); in _rtl92de_init_mac()
526 if (rtlhal->macphymode == DUALMAC_DUALPHY) in _rtl92de_hw_configure()
528 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) in _rtl92de_hw_configure()
534 rtlpci->reg_bcn_ctrl_val = 0x1f; in _rtl92de_hw_configure()
535 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); in _rtl92de_hw_configure()
554 switch (rtlpriv->phy.rf_type) { in _rtl92de_hw_configure()
557 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); in _rtl92de_hw_configure()
561 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); in _rtl92de_hw_configure()
574 if (ppsc->support_backdoor) in _rtl92de_enable_aspm_back_door()
586 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); in rtl92de_hw_init() local
587 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92de_hw_init()
596 rtlpci->being_init_adapter = true; in rtl92de_hw_init()
597 rtlpci->init_ready = false; in rtl92de_hw_init()
601 /* rtlpriv->intf_ops->disable_aspm(hw); */ in rtl92de_hw_init()
604 pr_err("Init MAC failed\n"); in rtl92de_hw_init()
616 rtlhal->last_hmeboxnum = 0; in rtl92de_hw_init()
617 rtlpriv->psc.fw_current_inpsmode = false; in rtl92de_hw_init()
623 if (rtlhal->earlymode_enable) { in rtl92de_hw_init()
638 if (mac->rdg_en) { in rtl92de_hw_init()
649 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); in rtl92de_hw_init()
650 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); in rtl92de_hw_init()
654 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; in rtl92de_hw_init()
661 /* After read predefined TXT, we must set BB/MAC/RF in rtl92de_hw_init()
667 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, in rtl92de_hw_init()
669 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, in rtl92de_hw_init()
672 /*---- Set CCK and OFDM Block "ON"----*/ in rtl92de_hw_init()
673 if (rtlhal->current_bandtype == BAND_ON_2_4G) in rtl92de_hw_init()
676 if (rtlhal->interfaceindex == 0) { in rtl92de_hw_init()
696 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92de_hw_init()
698 ppsc->rfpwr_state = ERFON; in rtl92de_hw_init()
700 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); in rtl92de_hw_init()
703 /* rtlpriv->intf_ops->enable_aspm(hw); */ in rtl92de_hw_init()
706 rtlpci->being_init_adapter = false; in rtl92de_hw_init()
708 if (ppsc->rfpwr_state == ERFON) { in rtl92de_hw_init()
709 rtl92d_phy_lc_calibrate(hw, IS_92D_SINGLEPHY(rtlhal->version)); in rtl92de_hw_init()
711 if (rtlhal->macphymode == DUALMAC_DUALPHY) { in rtl92de_hw_init()
725 rtlpci->init_ready = false; in rtl92de_hw_init()
730 rtlpci->init_ready = true; in rtl92de_hw_init()
784 rtlpriv->cfg->ops->led_control(hw, ledaction); in _rtl92de_set_media_status()
797 if (rtlpriv->psc.rfpwr_state != ERFON) in rtl92de_set_check_bssid()
800 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
804 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
809 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); in rtl92de_set_check_bssid()
818 return -EOPNOTSUPP; in rtl92de_set_network_type()
821 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { in rtl92de_set_network_type()
837 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92d_linked_set_reg()
839 u8 channel = rtlphy->current_channel; in rtl92d_linked_set_reg()
842 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) { in rtl92d_linked_set_reg()
854 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
855 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
856 rtlpci->irq_enabled = true; in rtl92de_enable_interrupt()
866 rtlpci->irq_enabled = false; in rtl92de_disable_interrupt()
875 rtlpriv->intf_ops->enable_aspm(hw); in _rtl92de_poweroff_adapter()
880 /* 0x20:value 05-->04 */ in _rtl92de_poweroff_adapter()
886 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */ in _rtl92de_poweroff_adapter()
927 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */ in _rtl92de_poweroff_adapter()
938 /* r. Note: for PCIe interface, PON will not turn */ in _rtl92de_poweroff_adapter()
939 /* off m-bias and BandGap in PCIe suspend mode. */ in _rtl92de_poweroff_adapter()
942 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { in _rtl92de_poweroff_adapter()
958 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); in rtl92de_card_disable() local
961 mac->link_state = MAC80211_NOLINK; in rtl92de_card_disable()
965 if (rtlpci->driver_is_goingto_unload || in rtl92de_card_disable()
966 ppsc->rfoff_reason > RF_CHANGE_BY_PS) in rtl92de_card_disable()
967 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); in rtl92de_card_disable()
969 /* Power sequence for each MAC. */ in rtl92de_card_disable()
974 /* e. reset MAC */ in rtl92de_card_disable()
980 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ in rtl92de_card_disable()
999 if (rtlpriv->rtlhal.interfaceindex == 1) in rtl92de_card_disable()
1020 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92de_interrupt_recognized()
1021 rtl_write_dword(rtlpriv, ISR, intvec->inta); in rtl92de_interrupt_recognized()
1027 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); in rtl92de_set_beacon_related_registers() local
1030 bcn_interval = mac->beacon_interval; in rtl92de_set_beacon_related_registers()
1037 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) in rtl92de_set_beacon_related_registers()
1047 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); in rtl92de_set_beacon_interval() local
1048 u16 bcn_interval = mac->beacon_interval; in rtl92de_set_beacon_interval()
1066 rtlpci->irq_mask[0] |= add_msr; in rtl92de_update_interrupt_mask()
1068 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92de_update_interrupt_mask()
1077 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv, in rtl92de_suspend()
1086 rtlpriv->rtlhal.macphyctl_reg); in rtl92de_resume()