Lines Matching +full:0 +full:x349
29 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); in rtl92de_read_dword_dbi()
41 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); in rtl92de_write_dword_dbi()
43 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); in rtl92de_write_dword_dbi()
59 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92de_enable_bcn_sub_func()
64 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92de_disable_bcn_sub_func()
99 (union aci_aifsn *)(&(mac->ac[0].aifs)); in rtl92de_set_hw_reg()
103 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92de_set_hw_reg()
139 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", in rtl92de_set_hw_reg()
145 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92de_set_hw_reg()
146 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92de_set_hw_reg()
158 (tmp_regcr | BIT(0))); in rtl92de_set_hw_reg()
159 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92de_set_hw_reg()
160 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92de_set_hw_reg()
167 rtl92d_set_fw_rsvdpagepkt(hw, 0); in rtl92de_set_hw_reg()
168 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92de_set_hw_reg()
169 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92de_set_hw_reg()
175 (tmp_regcr & ~(BIT(0)))); in rtl92de_set_hw_reg()
181 u8 btype_ibss = val[0]; in rtl92de_set_hw_reg()
185 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92de_set_hw_reg()
187 (u32) (mac->tsf & 0xffffffff)); in rtl92de_set_hw_reg()
189 (u32) ((mac->tsf >> 32) & 0xffffffff)); in rtl92de_set_hw_reg()
190 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92de_set_hw_reg()
202 * timer 25ns*0xfa0=100us for 0xf packets. in rtl92de_set_hw_reg()
203 * 0x306:Rx, 0x307:Tx */ in rtl92de_set_hw_reg()
204 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0); in rtl92de_set_hw_reg()
208 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in rtl92de_set_hw_reg()
223 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, in rtl92de_set_hw_reg()
229 RT_AC_INT_MASKS, 0); in rtl92de_set_hw_reg()
253 value8 = 0; in _rtl92de_llt_table_init()
254 value32 = 0x80bf0d29; in _rtl92de_llt_table_init()
258 value8 = 0; in _rtl92de_llt_table_init()
259 value32 = 0x80750005; in _rtl92de_llt_table_init()
263 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */ in _rtl92de_llt_table_init()
268 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */ in _rtl92de_llt_table_init()
274 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */ in _rtl92de_llt_table_init()
278 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */ in _rtl92de_llt_table_init()
283 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */ in _rtl92de_llt_table_init()
285 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); in _rtl92de_llt_table_init()
289 /* 16. PBP [7:0] = 0x11 */ in _rtl92de_llt_table_init()
291 rtl_write_byte(rtlpriv, REG_PBP, 0x11); in _rtl92de_llt_table_init()
293 /* 17. DRV_INFO_SZ = 0x04 */ in _rtl92de_llt_table_init()
294 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); in _rtl92de_llt_table_init()
297 for (i = 0; i < (txpktbuf_bndy - 1); i++) { in _rtl92de_llt_table_init()
304 status = rtl92d_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); in _rtl92de_llt_table_init()
354 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */ in _rtl92de_init_mac()
356 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); in _rtl92de_init_mac()
357 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05); in _rtl92de_init_mac()
359 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */ in _rtl92de_init_mac()
360 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */ in _rtl92de_init_mac()
364 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */ in _rtl92de_init_mac()
365 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92de_init_mac()
367 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */ in _rtl92de_init_mac()
368 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); in _rtl92de_init_mac()
373 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */ in _rtl92de_init_mac()
375 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); in _rtl92de_init_mac()
380 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */ in _rtl92de_init_mac()
383 retry = 0; in _rtl92de_init_mac()
384 while ((bytetmp & BIT(0)) && retry < 1000) { in _rtl92de_init_mac()
391 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */ in _rtl92de_init_mac()
392 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); in _rtl92de_init_mac()
395 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */ in _rtl92de_init_mac()
396 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */ in _rtl92de_init_mac()
397 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); in _rtl92de_init_mac()
401 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */ in _rtl92de_init_mac()
404 rtl_write_word(rtlpriv, REG_CR, 0x0); in _rtl92de_init_mac()
407 rtl_write_word(rtlpriv, REG_CR, 0x2ff); in _rtl92de_init_mac()
410 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0); in _rtl92de_init_mac()
412 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */ in _rtl92de_init_mac()
420 /* 19. HISR 0x124[31:0] = 0xffffffff; */ in _rtl92de_init_mac()
421 /* HISRE 0x12C[7:0] = 0xFF */ in _rtl92de_init_mac()
422 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); in _rtl92de_init_mac()
423 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); in _rtl92de_init_mac()
425 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */ in _rtl92de_init_mac()
426 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */ in _rtl92de_init_mac()
431 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */ in _rtl92de_init_mac()
442 wordtmp &= 0xf; in _rtl92de_init_mac()
443 wordtmp |= 0xF771; in _rtl92de_init_mac()
449 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); in _rtl92de_init_mac()
453 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */ in _rtl92de_init_mac()
463 rtl_write_byte(rtlpriv, 0x4d0, 0x0); in _rtl92de_init_mac()
481 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33); in _rtl92de_init_mac()
484 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in _rtl92de_init_mac()
498 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); in _rtl92de_init_mac()
512 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); in _rtl92de_hw_configure()
515 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in _rtl92de_hw_configure()
516 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); in _rtl92de_hw_configure()
517 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); in _rtl92de_hw_configure()
518 rtl_write_word(rtlpriv, REG_RL, 0x0707); in _rtl92de_hw_configure()
519 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); in _rtl92de_hw_configure()
520 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); in _rtl92de_hw_configure()
521 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); in _rtl92de_hw_configure()
522 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
523 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); in _rtl92de_hw_configure()
524 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); in _rtl92de_hw_configure()
527 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641); in _rtl92de_hw_configure()
529 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641); in _rtl92de_hw_configure()
531 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); in _rtl92de_hw_configure()
532 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); in _rtl92de_hw_configure()
533 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); in _rtl92de_hw_configure()
534 rtlpci->reg_bcn_ctrl_val = 0x1f; in _rtl92de_hw_configure()
536 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92de_hw_configure()
537 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); in _rtl92de_hw_configure()
538 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); in _rtl92de_hw_configure()
539 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); in _rtl92de_hw_configure()
541 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666); in _rtl92de_hw_configure()
543 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); in _rtl92de_hw_configure()
545 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
546 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); in _rtl92de_hw_configure()
548 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); in _rtl92de_hw_configure()
550 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); in _rtl92de_hw_configure()
552 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); in _rtl92de_hw_configure()
553 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); in _rtl92de_hw_configure()
571 rtl_write_byte(rtlpriv, 0x34b, 0x93); in _rtl92de_enable_aspm_back_door()
572 rtl_write_word(rtlpriv, 0x350, 0x870c); in _rtl92de_enable_aspm_back_door()
573 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
575 rtl_write_byte(rtlpriv, 0x349, 0x1b); in _rtl92de_enable_aspm_back_door()
577 rtl_write_byte(rtlpriv, 0x349, 0x03); in _rtl92de_enable_aspm_back_door()
578 rtl_write_word(rtlpriv, 0x350, 0x2718); in _rtl92de_enable_aspm_back_door()
579 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92de_enable_aspm_back_door()
616 rtlhal->last_hmeboxnum = 0; in rtl92de_hw_init()
619 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
620 tmp_u1b = tmp_u1b | 0x30; in rtl92de_hw_init()
621 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
627 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0); in rtl92de_hw_init()
628 tmp_u1b = tmp_u1b | 0x1f; in rtl92de_hw_init()
629 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b); in rtl92de_hw_init()
631 rtl_write_byte(rtlpriv, 0x4d3, 0x80); in rtl92de_hw_init()
633 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); in rtl92de_hw_init()
634 tmp_u1b = tmp_u1b | 0x40; in rtl92de_hw_init()
635 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); in rtl92de_hw_init()
639 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); in rtl92de_hw_init()
640 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); in rtl92de_hw_init()
641 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); in rtl92de_hw_init()
656 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in rtl92de_hw_init()
666 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in rtl92de_hw_init()
667 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, in rtl92de_hw_init()
674 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92de_hw_init()
675 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92de_hw_init()
676 if (rtlhal->interfaceindex == 0) { in rtl92de_hw_init()
713 for (i = 0; i < 10000; i++) { in rtl92de_hw_init()
718 0x2a, MASKDWORD); in rtl92de_hw_init()
741 bt_msr &= 0xfc; in _rtl92de_set_media_status()
786 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92de_set_media_status()
788 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92de_set_media_status()
789 return 0; in _rtl92de_set_media_status()
805 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92de_set_check_bssid()
808 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92de_set_check_bssid()
827 return 0; in rtl92de_set_network_type()
854 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
855 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92de_enable_interrupt()
876 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); in _rtl92de_poweroff_adapter()
877 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0); in _rtl92de_poweroff_adapter()
878 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0); in _rtl92de_poweroff_adapter()
880 /* 0x20:value 05-->04 */ in _rtl92de_poweroff_adapter()
881 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); in _rtl92de_poweroff_adapter()
886 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */ in _rtl92de_poweroff_adapter()
887 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); in _rtl92de_poweroff_adapter()
889 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */ in _rtl92de_poweroff_adapter()
890 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in _rtl92de_poweroff_adapter()
894 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */ in _rtl92de_poweroff_adapter()
895 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); in _rtl92de_poweroff_adapter()
897 /* i. Value = GPIO_PIN_CTRL[7:0] */ in _rtl92de_poweroff_adapter()
900 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */ in _rtl92de_poweroff_adapter()
903 0x00FF0000 | (u1b_tmp << 8)); in _rtl92de_poweroff_adapter()
905 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */ in _rtl92de_poweroff_adapter()
906 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); in _rtl92de_poweroff_adapter()
908 /* l. LEDCFG 0x4C[15:0] = 0x8080 */ in _rtl92de_poweroff_adapter()
909 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); in _rtl92de_poweroff_adapter()
913 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */ in _rtl92de_poweroff_adapter()
914 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); in _rtl92de_poweroff_adapter()
916 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */ in _rtl92de_poweroff_adapter()
917 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); in _rtl92de_poweroff_adapter()
919 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */ in _rtl92de_poweroff_adapter()
920 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
922 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */ in _rtl92de_poweroff_adapter()
923 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); in _rtl92de_poweroff_adapter()
927 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */ in _rtl92de_poweroff_adapter()
929 /* value as 0x18. Otherwise, we may not L0s sometimes. */ in _rtl92de_poweroff_adapter()
931 /* set as 0x00 do not affect power current. And if it */ in _rtl92de_poweroff_adapter()
932 /* is set as 0x18, they had ever met auto load fail problem. */ in _rtl92de_poweroff_adapter()
933 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); in _rtl92de_poweroff_adapter()
941 /* 0x17[7] 1b': power off in process 0b' : power off over */ in _rtl92de_poweroff_adapter()
977 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); in rtl92de_card_disable()
980 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ in rtl92de_card_disable()
983 /* 0x88c[23:20] = 0xf. */ in rtl92de_card_disable()
984 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in rtl92de_card_disable()
985 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in rtl92de_card_disable()
987 /* APSD_CTRL 0x600[7:0] = 0x40 */ in rtl92de_card_disable()
988 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in rtl92de_card_disable()
990 /* Close antenna 0,0xc04,0xd04 */ in rtl92de_card_disable()
991 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0); in rtl92de_card_disable()
992 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0); in rtl92de_card_disable()
994 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */ in rtl92de_card_disable()
995 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92de_card_disable()
998 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */ in rtl92de_card_disable()
1000 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); in rtl92de_card_disable()
1003 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */ in rtl92de_card_disable()
1005 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); in rtl92de_card_disable()
1007 rtl_write_byte(rtlpriv, REG_CR, 0x0); in rtl92de_card_disable()
1020 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92de_interrupt_recognized()
1035 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); in rtl92de_set_beacon_related_registers()
1036 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); in rtl92de_set_beacon_related_registers()
1038 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); in rtl92de_set_beacon_related_registers()
1040 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); in rtl92de_set_beacon_related_registers()
1041 rtl_write_byte(rtlpriv, 0x606, 0x30); in rtl92de_set_beacon_related_registers()
1066 rtlpci->irq_mask[0] |= add_msr; in rtl92de_update_interrupt_mask()
1068 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92de_update_interrupt_mask()