132 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);  in rtl92c_llt_write()
338 		rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &  in rtl92c_enable_interrupt()
340 		rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &  in rtl92c_enable_interrupt()
343 		rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &  in rtl92c_enable_interrupt()
345 		rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &  in rtl92c_enable_interrupt()
359 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);  in rtl92c_disable_interrupt()
360 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);  in rtl92c_disable_interrupt()
428 	rtl_write_dword(rtlpriv, REG_RRSR, value32);  in rtl92c_init_adaptive_ctrl()
434 	rtl_write_dword(rtlpriv,  REG_RL, value16);  in rtl92c_init_adaptive_ctrl()
442 	rtl_write_dword(rtlpriv,  REG_DARFRC, 0x00000000);  in rtl92c_init_rate_fallback()
443 	rtl_write_dword(rtlpriv,  REG_DARFRC+4, 0x10080404);  in rtl92c_init_rate_fallback()
444 	rtl_write_dword(rtlpriv,  REG_RARFRC, 0x04030201);  in rtl92c_init_rate_fallback()
445 	rtl_write_dword(rtlpriv,  REG_RARFRC+4, 0x08070605);  in rtl92c_init_rate_fallback()
480 	rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);  in rtl92c_init_edca_param()
500 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);  in rtl92c_init_edca()
502 	rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);  in rtl92c_init_edca()
503 	rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);  in rtl92c_init_edca()
504 	rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);  in rtl92c_init_edca()
505 	rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);  in rtl92c_init_edca()
519 	rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);  in rtl92c_init_ampdu_aggregation()