Lines Matching +full:0 +full:x349
42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ce_stop_tx_beacon()
44 tmp1byte &= ~(BIT(0)); in _rtl92ce_stop_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ce_resume_tx_beacon()
57 tmp1byte |= BIT(0); in _rtl92ce_resume_tx_beacon()
63 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92ce_enable_bcn_sub_func()
68 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92ce_disable_bcn_sub_func()
95 val_rcr &= 0x00070000; in rtl92ce_get_hw_reg()
138 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92ce_set_hw_reg()
145 u16 rate_cfg = ((u16 *) val)[0]; in rtl92ce_set_hw_reg()
146 u8 rate_index = 0; in rtl92ce_set_hw_reg()
148 rate_cfg &= 0x15f; in rtl92ce_set_hw_reg()
149 rate_cfg |= 0x01; in rtl92ce_set_hw_reg()
150 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); in rtl92ce_set_hw_reg()
152 (rate_cfg >> 8) & 0xff); in rtl92ce_set_hw_reg()
153 while (rate_cfg > 0x1) { in rtl92ce_set_hw_reg()
162 for (idx = 0; idx < ETH_ALEN; idx++) { in rtl92ce_set_hw_reg()
169 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); in rtl92ce_set_hw_reg()
172 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); in rtl92ce_set_hw_reg()
173 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); in rtl92ce_set_hw_reg()
177 0x0e0e); in rtl92ce_set_hw_reg()
187 "HW_VAR_SLOT_TIME %x\n", val[0]); in rtl92ce_set_hw_reg()
189 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); in rtl92ce_set_hw_reg()
191 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { in rtl92ce_set_hw_reg()
204 reg_tmp |= 0x80; in rtl92ce_set_hw_reg()
216 0xf8) | in rtl92ce_set_hw_reg()
246 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; in rtl92ce_set_hw_reg()
247 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; in rtl92ce_set_hw_reg()
251 u8 index = 0; in rtl92ce_set_hw_reg()
263 if (factor_toset > 0xf) in rtl92ce_set_hw_reg()
264 factor_toset = 0xf; in rtl92ce_set_hw_reg()
266 for (index = 0; index < 4; index++) { in rtl92ce_set_hw_reg()
267 if ((p_regtoset[index] & 0xf0) > in rtl92ce_set_hw_reg()
270 (p_regtoset[index] & 0x0f) | in rtl92ce_set_hw_reg()
273 if ((p_regtoset[index] & 0x0f) > in rtl92ce_set_hw_reg()
276 (p_regtoset[index] & 0xf0) | in rtl92ce_set_hw_reg()
305 (union aci_aifsn *)(&(mac->ac[0].aifs)); in rtl92ce_set_hw_reg()
310 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); in rtl92ce_set_hw_reg()
348 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", in rtl92ce_set_hw_reg()
354 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); in rtl92ce_set_hw_reg()
355 rtlpci->receive_config = ((u32 *) (val))[0]; in rtl92ce_set_hw_reg()
359 u8 retry_limit = val[0]; in rtl92ce_set_hw_reg()
367 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); in rtl92ce_set_hw_reg()
421 (tmp_regcr | BIT(0))); in rtl92ce_set_hw_reg()
423 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92ce_set_hw_reg()
424 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92ce_set_hw_reg()
436 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92ce_set_hw_reg()
437 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92ce_set_hw_reg()
446 (tmp_regcr & ~(BIT(0)))); in rtl92ce_set_hw_reg()
459 u2btmp &= 0xC000; in rtl92ce_set_hw_reg()
466 u8 btype_ibss = val[0]; in rtl92ce_set_hw_reg()
471 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); in rtl92ce_set_hw_reg()
474 (u32) (mac->tsf & 0xffffffff)); in rtl92ce_set_hw_reg()
476 (u32) ((mac->tsf >> 32) & 0xffffffff)); in rtl92ce_set_hw_reg()
478 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); in rtl92ce_set_hw_reg()
492 rpwm_val = 0x02; /* RF off */ in rtl92ce_set_hw_reg()
505 rpwm_val = 0x0C; /* RF on */ in rtl92ce_set_hw_reg()
523 array[0] = 0xff; in rtl92ce_set_hw_reg()
537 long count = 0; in _rtl92ce_llt_write()
585 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); in _rtl92ce_llt_table_init()
586 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); in _rtl92ce_llt_table_init()
588 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); in _rtl92ce_llt_table_init()
590 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); in _rtl92ce_llt_table_init()
592 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); in _rtl92ce_llt_table_init()
594 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); in _rtl92ce_llt_table_init()
596 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29); in _rtl92ce_llt_table_init()
599 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); in _rtl92ce_llt_table_init()
605 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); in _rtl92ce_llt_table_init()
606 rtl_write_byte(rtlpriv, REG_PBP, 0x11); in _rtl92ce_llt_table_init()
607 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); in _rtl92ce_llt_table_init()
609 for (i = 0; i < (txpktbuf_bndy - 1); i++) { in _rtl92ce_llt_table_init()
615 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); in _rtl92ce_llt_table_init()
660 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); in _rtl92ce_init_mac()
668 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92ce_init_mac()
669 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); in _rtl92ce_init_mac()
674 u4b_tmp &= (~0x00024800); in _rtl92ce_init_mac()
678 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); in _rtl92ce_init_mac()
687 retry = 0; in _rtl92ce_init_mac()
689 rtl_read_dword(rtlpriv, 0xEC), bytetmp); in _rtl92ce_init_mac()
691 while ((bytetmp & BIT(0)) && retry < 1000) { in _rtl92ce_init_mac()
696 rtl_read_dword(rtlpriv, 0xEC), bytetmp); in _rtl92ce_init_mac()
700 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); in _rtl92ce_init_mac()
702 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); in _rtl92ce_init_mac()
706 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd; in _rtl92ce_init_mac()
710 rtl_write_word(rtlpriv, REG_CR, 0x2ff); in _rtl92ce_init_mac()
715 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); in _rtl92ce_init_mac()
716 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); in _rtl92ce_init_mac()
718 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); in _rtl92ce_init_mac()
721 wordtmp &= 0xf; in _rtl92ce_init_mac()
722 wordtmp |= 0xF771; in _rtl92ce_init_mac()
725 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); in _rtl92ce_init_mac()
729 rtl_write_byte(rtlpriv, 0x4d0, 0x0); in _rtl92ce_init_mac()
753 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); in _rtl92ce_init_mac()
755 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22); in _rtl92ce_init_mac()
757 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in _rtl92ce_init_mac()
768 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); in _rtl92ce_init_mac()
783 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); in _rtl92ce_hw_configure()
789 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in _rtl92ce_hw_configure()
791 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); in _rtl92ce_hw_configure()
793 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); in _rtl92ce_hw_configure()
795 rtl_write_word(rtlpriv, REG_RL, 0x0707); in _rtl92ce_hw_configure()
797 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); in _rtl92ce_hw_configure()
799 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); in _rtl92ce_hw_configure()
801 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); in _rtl92ce_hw_configure()
802 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); in _rtl92ce_hw_configure()
803 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); in _rtl92ce_hw_configure()
804 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); in _rtl92ce_hw_configure()
808 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); in _rtl92ce_hw_configure()
810 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); in _rtl92ce_hw_configure()
812 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); in _rtl92ce_hw_configure()
814 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in _rtl92ce_hw_configure()
816 rtlpci->reg_bcn_ctrl_val = 0x1f; in _rtl92ce_hw_configure()
819 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ce_hw_configure()
821 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ce_hw_configure()
823 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); in _rtl92ce_hw_configure()
824 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); in _rtl92ce_hw_configure()
828 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); in _rtl92ce_hw_configure()
829 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); in _rtl92ce_hw_configure()
831 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); in _rtl92ce_hw_configure()
832 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); in _rtl92ce_hw_configure()
837 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); in _rtl92ce_hw_configure()
839 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); in _rtl92ce_hw_configure()
841 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); in _rtl92ce_hw_configure()
843 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); in _rtl92ce_hw_configure()
844 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); in _rtl92ce_hw_configure()
846 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); in _rtl92ce_hw_configure()
848 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); in _rtl92ce_hw_configure()
850 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); in _rtl92ce_hw_configure()
851 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); in _rtl92ce_hw_configure()
860 rtl_write_byte(rtlpriv, 0x34b, 0x93); in _rtl92ce_enable_aspm_back_door()
861 rtl_write_word(rtlpriv, 0x350, 0x870c); in _rtl92ce_enable_aspm_back_door()
862 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92ce_enable_aspm_back_door()
865 rtl_write_byte(rtlpriv, 0x349, 0x1b); in _rtl92ce_enable_aspm_back_door()
867 rtl_write_byte(rtlpriv, 0x349, 0x03); in _rtl92ce_enable_aspm_back_door()
869 rtl_write_word(rtlpriv, 0x350, 0x2718); in _rtl92ce_enable_aspm_back_door()
870 rtl_write_byte(rtlpriv, 0x352, 0x1); in _rtl92ce_enable_aspm_back_door()
898 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); in rtl92ce_enable_hw_security_config()
951 rtlhal->last_hmeboxnum = 0; in rtl92ce_hw_init()
965 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); in rtl92ce_hw_init()
966 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); in rtl92ce_hw_init()
968 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); in rtl92ce_hw_init()
969 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); in rtl92ce_hw_init()
970 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); in rtl92ce_hw_init()
971 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); in rtl92ce_hw_init()
972 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); in rtl92ce_hw_init()
973 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); in rtl92ce_hw_init()
975 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, in rtl92ce_hw_init()
979 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92ce_hw_init()
980 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92ce_hw_init()
1008 tmp_u1b = efuse_read_1byte(hw, 0x1FA); in rtl92ce_hw_init()
1009 if (!(tmp_u1b & BIT(0))) { in rtl92ce_hw_init()
1010 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); in rtl92ce_hw_init()
1015 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); in rtl92ce_hw_init()
1020 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); in rtl92ce_hw_init()
1021 tmp_u1b &= 0x0F; in rtl92ce_hw_init()
1022 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); in rtl92ce_hw_init()
1024 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); in rtl92ce_hw_init()
1048 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) | in _rtl92ce_read_chip_version()
1049 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); in _rtl92ce_read_chip_version()
1062 RF_TYPE_1T2R : 0)); in _rtl92ce_read_chip_version()
1104 switch (version & 0x3) { in _rtl92ce_read_chip_version()
1134 bt_msr &= 0xfc; in _rtl92ce_set_media_status()
1196 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92ce_set_media_status()
1198 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92ce_set_media_status()
1199 return 0; in _rtl92ce_set_media_status()
1216 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); in rtl92ce_set_check_bssid()
1219 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); in rtl92ce_set_check_bssid()
1241 return 0; in rtl92ce_set_network_type()
1252 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); in rtl92ce_set_qos()
1258 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); in rtl92ce_set_qos()
1261 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); in rtl92ce_set_qos()
1274 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92ce_enable_interrupt()
1275 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92ce_enable_interrupt()
1297 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92ce_poweroff_adapter()
1298 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92ce_poweroff_adapter()
1299 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); in _rtl92ce_poweroff_adapter()
1300 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92ce_poweroff_adapter()
1301 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92ce_poweroff_adapter()
1302 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); in _rtl92ce_poweroff_adapter()
1305 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); in _rtl92ce_poweroff_adapter()
1306 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in _rtl92ce_poweroff_adapter()
1307 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); in _rtl92ce_poweroff_adapter()
1312 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 | in _rtl92ce_poweroff_adapter()
1315 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 | in _rtl92ce_poweroff_adapter()
1318 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); in _rtl92ce_poweroff_adapter()
1319 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); in _rtl92ce_poweroff_adapter()
1320 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); in _rtl92ce_poweroff_adapter()
1322 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); in _rtl92ce_poweroff_adapter()
1325 u4b_tmp |= 0x03824800; in _rtl92ce_poweroff_adapter()
1328 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); in _rtl92ce_poweroff_adapter()
1331 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); in _rtl92ce_poweroff_adapter()
1332 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); in _rtl92ce_poweroff_adapter()
1362 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92ce_interrupt_recognized()
1378 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); in rtl92ce_set_beacon_related_registers()
1379 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); in rtl92ce_set_beacon_related_registers()
1380 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); in rtl92ce_set_beacon_related_registers()
1381 rtl_write_byte(rtlpriv, 0x606, 0x30); in rtl92ce_set_beacon_related_registers()
1408 rtlpci->irq_mask[0] |= add_msr; in rtl92ce_update_interrupt_mask()
1410 rtlpci->irq_mask[0] &= (~rm_msr); in rtl92ce_update_interrupt_mask()
1424 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92ce_read_txpower_info_from_hwpg()
1425 for (i = 0; i < 3; i++) { in _rtl92ce_read_txpower_info_from_hwpg()
1427 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i] != 0xff && in _rtl92ce_read_txpower_info_from_hwpg()
1428 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i] != 0xff) { in _rtl92ce_read_txpower_info_from_hwpg()
1447 for (i = 0; i < 3; i++) { in _rtl92ce_read_txpower_info_from_hwpg()
1449 hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i] != 0xff) in _rtl92ce_read_txpower_info_from_hwpg()
1454 (tempval & 0xf); in _rtl92ce_read_txpower_info_from_hwpg()
1456 ((tempval & 0xf0) >> 4); in _rtl92ce_read_txpower_info_from_hwpg()
1459 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92ce_read_txpower_info_from_hwpg()
1460 for (i = 0; i < 3; i++) in _rtl92ce_read_txpower_info_from_hwpg()
1462 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1466 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92ce_read_txpower_info_from_hwpg()
1467 for (i = 0; i < 3; i++) in _rtl92ce_read_txpower_info_from_hwpg()
1469 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1473 for (rf_path = 0; rf_path < 2; rf_path++) in _rtl92ce_read_txpower_info_from_hwpg()
1474 for (i = 0; i < 3; i++) in _rtl92ce_read_txpower_info_from_hwpg()
1476 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1481 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92ce_read_txpower_info_from_hwpg()
1482 for (i = 0; i < 14; i++) { in _rtl92ce_read_txpower_info_from_hwpg()
1495 > 0) { in _rtl92ce_read_txpower_info_from_hwpg()
1504 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; in _rtl92ce_read_txpower_info_from_hwpg()
1508 for (i = 0; i < 14; i++) { in _rtl92ce_read_txpower_info_from_hwpg()
1510 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", in _rtl92ce_read_txpower_info_from_hwpg()
1518 for (i = 0; i < 3; i++) { in _rtl92ce_read_txpower_info_from_hwpg()
1520 hwinfo[EEPROM_TXPWR_GROUP + i] != 0xff && in _rtl92ce_read_txpower_info_from_hwpg()
1521 hwinfo[EEPROM_TXPWR_GROUP + 3 + i] != 0xff) { in _rtl92ce_read_txpower_info_from_hwpg()
1527 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; in _rtl92ce_read_txpower_info_from_hwpg()
1528 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; in _rtl92ce_read_txpower_info_from_hwpg()
1532 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl92ce_read_txpower_info_from_hwpg()
1533 for (i = 0; i < 14; i++) { in _rtl92ce_read_txpower_info_from_hwpg()
1539 & 0xf); in _rtl92ce_read_txpower_info_from_hwpg()
1542 & 0xf); in _rtl92ce_read_txpower_info_from_hwpg()
1546 & 0xf0) >> 4); in _rtl92ce_read_txpower_info_from_hwpg()
1549 & 0xf0) >> 4); in _rtl92ce_read_txpower_info_from_hwpg()
1553 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1557 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1563 for (i = 0; i < 14; i++) { in _rtl92ce_read_txpower_info_from_hwpg()
1567 hwinfo[EEPROM_TXPOWERHT20DIFF + index] != 0xff) in _rtl92ce_read_txpower_info_from_hwpg()
1572 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); in _rtl92ce_read_txpower_info_from_hwpg()
1574 ((tempval >> 4) & 0xF); in _rtl92ce_read_txpower_info_from_hwpg()
1577 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; in _rtl92ce_read_txpower_info_from_hwpg()
1580 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; in _rtl92ce_read_txpower_info_from_hwpg()
1585 hwinfo[EEPROM_TXPOWER_OFDMDIFF + index] != 0xff) in _rtl92ce_read_txpower_info_from_hwpg()
1590 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); in _rtl92ce_read_txpower_info_from_hwpg()
1592 ((tempval >> 4) & 0xF); in _rtl92ce_read_txpower_info_from_hwpg()
1598 for (i = 0; i < 14; i++) in _rtl92ce_read_txpower_info_from_hwpg()
1600 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1602 for (i = 0; i < 14; i++) in _rtl92ce_read_txpower_info_from_hwpg()
1604 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1606 for (i = 0; i < 14; i++) in _rtl92ce_read_txpower_info_from_hwpg()
1608 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1610 for (i = 0; i < 14; i++) in _rtl92ce_read_txpower_info_from_hwpg()
1612 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1615 if (!autoload_fail && hwinfo[RF_OPTION1] != 0xff) in _rtl92ce_read_txpower_info_from_hwpg()
1616 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); in _rtl92ce_read_txpower_info_from_hwpg()
1618 rtlefuse->eeprom_regulatory = 0; in _rtl92ce_read_txpower_info_from_hwpg()
1620 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); in _rtl92ce_read_txpower_info_from_hwpg()
1623 hwinfo[EEPROM_TSSI_A] != 0xff && in _rtl92ce_read_txpower_info_from_hwpg()
1624 hwinfo[EEPROM_TSSI_B] != 0xff) { in _rtl92ce_read_txpower_info_from_hwpg()
1631 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", in _rtl92ce_read_txpower_info_from_hwpg()
1635 if (!autoload_fail && hwinfo[EEPROM_THERMAL_METER] != 0xff) in _rtl92ce_read_txpower_info_from_hwpg()
1639 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); in _rtl92ce_read_txpower_info_from_hwpg()
1641 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) in _rtl92ce_read_txpower_info_from_hwpg()
1644 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; in _rtl92ce_read_txpower_info_from_hwpg()
1646 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); in _rtl92ce_read_txpower_info_from_hwpg()
1677 if (rtlefuse->eeprom_did == 0x8176) { in _rtl92ce_read_adapter_info()
1678 if ((rtlefuse->eeprom_svid == 0x103C && in _rtl92ce_read_adapter_info()
1679 rtlefuse->eeprom_smid == 0x1629)) in _rtl92ce_read_adapter_info()
1722 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); in _rtl92ce_hal_customized_behavior()
1735 rtlpriv->dm.rfpath_rxenable[0] = true; in rtl92ce_read_eeprom_info()
1737 rtlpriv->dm.rfpath_rxenable[0] = in rtl92ce_read_eeprom_info()
1739 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", in rtl92ce_read_eeprom_info()
1767 u8 ratr_index = 0; in rtl92ce_update_hal_rate_table()
1773 1 : 0; in rtl92ce_update_hal_rate_table()
1775 1 : 0; in rtl92ce_update_hal_rate_table()
1782 ratr_value = sta->deflink.supp_rates[0]; in rtl92ce_update_hal_rate_table()
1784 ratr_value = 0xfff; in rtl92ce_update_hal_rate_table()
1787 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92ce_update_hal_rate_table()
1790 if (ratr_value & 0x0000000c) in rtl92ce_update_hal_rate_table()
1791 ratr_value &= 0x0000000d; in rtl92ce_update_hal_rate_table()
1793 ratr_value &= 0x0000000f; in rtl92ce_update_hal_rate_table()
1796 ratr_value &= 0x00000FF5; in rtl92ce_update_hal_rate_table()
1803 ratr_mask = 0x000ff005; in rtl92ce_update_hal_rate_table()
1805 ratr_mask = 0x0f0ff005; in rtl92ce_update_hal_rate_table()
1811 ratr_value &= 0x000ff0ff; in rtl92ce_update_hal_rate_table()
1813 ratr_value &= 0x0f0ff0ff; in rtl92ce_update_hal_rate_table()
1824 ratr_value &= 0x0fffcfc0; in rtl92ce_update_hal_rate_table()
1826 ratr_value &= 0x0FFFFFFF; in rtl92ce_update_hal_rate_table()
1832 ratr_value |= 0x10000000; in rtl92ce_update_hal_rate_table()
1835 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { in rtl92ce_update_hal_rate_table()
1861 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0; in rtl92ce_update_hal_rate_mask()
1863 IEEE80211_HT_CAP_SGI_40) ? 1 : 0; in rtl92ce_update_hal_rate_mask()
1865 1 : 0; in rtl92ce_update_hal_rate_mask()
1866 enum wireless_mode wirelessmode = 0; in rtl92ce_update_hal_rate_mask()
1869 u8 macid = 0; in rtl92ce_update_hal_rate_mask()
1883 ratr_bitmap = sta->deflink.supp_rates[0]; in rtl92ce_update_hal_rate_mask()
1885 ratr_bitmap = 0xfff; in rtl92ce_update_hal_rate_mask()
1887 sta->deflink.ht_cap.mcs.rx_mask[0] << 12); in rtl92ce_update_hal_rate_mask()
1891 if (ratr_bitmap & 0x0000000c) in rtl92ce_update_hal_rate_mask()
1892 ratr_bitmap &= 0x0000000d; in rtl92ce_update_hal_rate_mask()
1894 ratr_bitmap &= 0x0000000f; in rtl92ce_update_hal_rate_mask()
1900 ratr_bitmap &= 0x00000f00; in rtl92ce_update_hal_rate_mask()
1902 ratr_bitmap &= 0x00000ff0; in rtl92ce_update_hal_rate_mask()
1904 ratr_bitmap &= 0x00000ff5; in rtl92ce_update_hal_rate_mask()
1908 ratr_bitmap &= 0x00000ff0; in rtl92ce_update_hal_rate_mask()
1918 ratr_bitmap &= 0x000f0000; in rtl92ce_update_hal_rate_mask()
1920 ratr_bitmap &= 0x000ff000; in rtl92ce_update_hal_rate_mask()
1922 ratr_bitmap &= 0x000ff015; in rtl92ce_update_hal_rate_mask()
1925 ratr_bitmap &= 0x000f0000; in rtl92ce_update_hal_rate_mask()
1927 ratr_bitmap &= 0x000ff000; in rtl92ce_update_hal_rate_mask()
1929 ratr_bitmap &= 0x000ff005; in rtl92ce_update_hal_rate_mask()
1934 ratr_bitmap &= 0x0f0f0000; in rtl92ce_update_hal_rate_mask()
1936 ratr_bitmap &= 0x0f0ff000; in rtl92ce_update_hal_rate_mask()
1938 ratr_bitmap &= 0x0f0ff015; in rtl92ce_update_hal_rate_mask()
1941 ratr_bitmap &= 0x0f0f0000; in rtl92ce_update_hal_rate_mask()
1943 ratr_bitmap &= 0x0f0ff000; in rtl92ce_update_hal_rate_mask()
1945 ratr_bitmap &= 0x0f0ff005; in rtl92ce_update_hal_rate_mask()
1952 if (macid == 0) in rtl92ce_update_hal_rate_mask()
1962 ratr_bitmap &= 0x000ff0ff; in rtl92ce_update_hal_rate_mask()
1964 ratr_bitmap &= 0x0f0ff0ff; in rtl92ce_update_hal_rate_mask()
1971 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | in rtl92ce_update_hal_rate_mask()
1973 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; in rtl92ce_update_hal_rate_mask()
2000 sifs_timer = 0x0a0a; in rtl92ce_update_channel_access_setting()
2002 sifs_timer = 0x1010; in rtl92ce_update_channel_access_setting()
2079 u32 entry_id = 0; in rtl92ce_set_key()
2083 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, in rtl92ce_set_key()
2084 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, in rtl92ce_set_key()
2085 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, in rtl92ce_set_key()
2086 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} in rtl92ce_set_key()
2089 0xff, 0xff, 0xff, 0xff, 0xff, 0xff in rtl92ce_set_key()
2093 u8 idx = 0; in rtl92ce_set_key()
2094 u8 cam_offset = 0; in rtl92ce_set_key()
2099 for (idx = 0; idx < clear_number; idx++) { in rtl92ce_set_key()
2104 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92ce_set_key()
2106 rtlpriv->sec.key_len[idx] = 0; in rtl92ce_set_key()
2156 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92ce_set_key()
2170 rtlpriv->sec.key_buf[0][0], in rtl92ce_set_key()
2171 rtlpriv->sec.key_buf[0][1]); in rtl92ce_set_key()
2248 rtlpriv->btcoexist.bt_edca_ul = 0; in rtl8192ce_bt_var_init()
2249 rtlpriv->btcoexist.bt_edca_dl = 0; in rtl8192ce_bt_var_init()
2250 rtlpriv->btcoexist.bt_rssi_state = 0xff; in rtl8192ce_bt_var_init()
2262 ((hwinfo[RF_OPTION1] & 0xe0) >> 5); in rtl8192ce_read_bt_coexist_info_from_hwpg()
2264 rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1); in rtl8192ce_read_bt_coexist_info_from_hwpg()
2265 rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1); in rtl8192ce_read_bt_coexist_info_from_hwpg()
2266 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); in rtl8192ce_read_bt_coexist_info_from_hwpg()
2268 ((val & 0x20) >> 5); in rtl8192ce_read_bt_coexist_info_from_hwpg()
2270 rtlpriv->btcoexist.eeprom_bt_coexist = 0; in rtl8192ce_read_bt_coexist_info_from_hwpg()
2273 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0; in rtl8192ce_read_bt_coexist_info_from_hwpg()
2284 /* 0:Low, 1:High, 2:From Efuse. */ in rtl8192ce_bt_reg_init()
2286 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ in rtl8192ce_bt_reg_init()
2288 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ in rtl8192ce_bt_reg_init()
2289 rtlpriv->btcoexist.reg_bt_sco = 0; in rtl8192ce_bt_reg_init()
2304 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); in rtl8192ce_bt_hw_init()
2306 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0); in rtl8192ce_bt_hw_init()
2309 0 : BIT(1)) | in rtl8192ce_bt_hw_init()
2311 0 : BIT(2)); in rtl8192ce_bt_hw_init()
2312 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); in rtl8192ce_bt_hw_init()
2314 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); in rtl8192ce_bt_hw_init()
2315 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); in rtl8192ce_bt_hw_init()
2316 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); in rtl8192ce_bt_hw_init()