Lines Matching +full:0 +full:x80800000
24 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92c_phy_query_bb_reg()
59 return 0; in _rtl92c_phy_fw_rf_serial_read()
79 u8 rfpi_enable = 0; in _rtl92c_phy_rf_serial_read()
82 offset &= 0x3f; in _rtl92c_phy_rf_serial_read()
86 return 0xFFFFFFFF; in _rtl92c_phy_rf_serial_read()
115 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_read()
136 offset &= 0x3f; in _rtl92c_phy_rf_serial_write()
138 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92c_phy_rf_serial_write()
140 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_write()
148 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl92c_phy_bb_config_1t()
149 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); in _rtl92c_phy_bb_config_1t()
150 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); in _rtl92c_phy_bb_config_1t()
151 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); in _rtl92c_phy_bb_config_1t()
152 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); in _rtl92c_phy_bb_config_1t()
153 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
154 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
155 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
156 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
157 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
186 rtlphy->pwrgroup_cnt = 0; in _rtl92c_phy_bb8192c_config_parafile()
201 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl92c_phy_bb8192c_config_parafile()
216 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] = in _rtl92c_store_pwrindex_diffrate_offset()
219 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
222 [rtlphy->pwrgroup_cnt][0]); in _rtl92c_store_pwrindex_diffrate_offset()
228 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
237 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
242 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { in _rtl92c_store_pwrindex_diffrate_offset()
246 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
255 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
264 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
273 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
282 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
291 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
300 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
309 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
314 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { in _rtl92c_store_pwrindex_diffrate_offset()
318 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
327 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
336 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
345 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
354 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
369 rtlphy->default_initialgain[0] = in rtl92c_phy_get_hw_reg_originalvalue()
379 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl92c_phy_get_hw_reg_originalvalue()
380 rtlphy->default_initialgain[0], in rtl92c_phy_get_hw_reg_originalvalue()
391 "Default framesync (0x%x) = 0x%x\n", in rtl92c_phy_get_hw_reg_originalvalue()
542 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92c_ccxpower_index_check()
543 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92c_ccxpower_index_check()
555 &cckpowerlevel[0], &ofdmpowerlevel[0]); in rtl92c_phy_set_txpower_level()
556 _rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0], in rtl92c_phy_set_txpower_level()
557 &ofdmpowerlevel[0]); in rtl92c_phy_set_txpower_level()
558 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl92c_phy_set_txpower_level()
559 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], in rtl92c_phy_set_txpower_level()
575 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0) in rtl92c_phy_update_txpower_dbm()
578 ofdmtxpwridx = 0; in rtl92c_phy_update_txpower_dbm()
582 for (idx = 0; idx < 14; idx++) { in rtl92c_phy_update_txpower_dbm()
583 for (rf_path = 0; rf_path < 2; rf_path++) { in rtl92c_phy_update_txpower_dbm()
616 if ((power_indbm - offset) > 0) in _rtl92c_phy_dbm_to_txpwr_idx()
619 txpwridx = 0; in _rtl92c_phy_dbm_to_txpwr_idx()
691 if (delay > 0) in rtl92c_phy_sw_chnl_callback()
711 return 0; in rtl92c_phy_sw_chnl()
713 return 0; in rtl92c_phy_sw_chnl()
717 rtlphy->sw_chnl_stage = 0; in rtl92c_phy_sw_chnl()
718 rtlphy->sw_chnl_step = 0; in rtl92c_phy_sw_chnl()
743 MASKDWORD, 0x00255); in _rtl92c_phy_sw_rf_seting()
793 precommoncmdcnt = 0; in _rtl92c_phy_sw_chnl_step_by_step()
796 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92c_phy_sw_chnl_step_by_step()
798 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92c_phy_sw_chnl_step_by_step()
800 postcommoncmdcnt = 0; in _rtl92c_phy_sw_chnl_step_by_step()
803 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92c_phy_sw_chnl_step_by_step()
805 rfdependcmdcnt = 0; in _rtl92c_phy_sw_chnl_step_by_step()
815 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, in _rtl92c_phy_sw_chnl_step_by_step()
816 0); in _rtl92c_phy_sw_chnl_step_by_step()
820 case 0: in _rtl92c_phy_sw_chnl_step_by_step()
840 (*step) = 0; in _rtl92c_phy_sw_chnl_step_by_step()
862 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92c_phy_sw_chnl_step_by_step()
865 0xfffffc00) | currentcmd->para2); in _rtl92c_phy_sw_chnl_step_by_step()
898 u8 result = 0x00; in _rtl92c_phy_path_a_iqk()
900 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92c_phy_path_a_iqk()
901 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92c_phy_path_a_iqk()
902 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92c_phy_path_a_iqk()
903 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, in _rtl92c_phy_path_a_iqk()
904 config_pathb ? 0x28160202 : 0x28160502); in _rtl92c_phy_path_a_iqk()
907 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92c_phy_path_a_iqk()
908 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92c_phy_path_a_iqk()
909 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92c_phy_path_a_iqk()
910 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); in _rtl92c_phy_path_a_iqk()
913 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); in _rtl92c_phy_path_a_iqk()
914 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92c_phy_path_a_iqk()
915 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92c_phy_path_a_iqk()
919 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92c_phy_path_a_iqk()
920 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92c_phy_path_a_iqk()
921 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92c_phy_path_a_iqk()
922 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92c_phy_path_a_iqk()
925 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92c_phy_path_a_iqk()
926 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92c_phy_path_a_iqk()
927 result |= 0x01; in _rtl92c_phy_path_a_iqk()
932 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92c_phy_path_a_iqk()
933 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl92c_phy_path_a_iqk()
934 result |= 0x02; in _rtl92c_phy_path_a_iqk()
941 u8 result = 0x00; in _rtl92c_phy_path_b_iqk()
943 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92c_phy_path_b_iqk()
944 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92c_phy_path_b_iqk()
946 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92c_phy_path_b_iqk()
947 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92c_phy_path_b_iqk()
948 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92c_phy_path_b_iqk()
949 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92c_phy_path_b_iqk()
950 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92c_phy_path_b_iqk()
953 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92c_phy_path_b_iqk()
954 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92c_phy_path_b_iqk()
955 result |= 0x01; in _rtl92c_phy_path_b_iqk()
959 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92c_phy_path_b_iqk()
960 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92c_phy_path_b_iqk()
961 result |= 0x02; in _rtl92c_phy_path_b_iqk()
972 if (final_candidate == 0xFF) { in _rtl92c_phy_path_a_fill_iqk_matrix()
976 MASKDWORD) >> 22) & 0x3FF; in _rtl92c_phy_path_a_fill_iqk_matrix()
977 x = result[final_candidate][0]; in _rtl92c_phy_path_a_fill_iqk_matrix()
978 if ((x & 0x00000200) != 0) in _rtl92c_phy_path_a_fill_iqk_matrix()
979 x = x | 0xFFFFFC00; in _rtl92c_phy_path_a_fill_iqk_matrix()
981 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92c_phy_path_a_fill_iqk_matrix()
983 ((x * oldval_0 >> 7) & 0x1)); in _rtl92c_phy_path_a_fill_iqk_matrix()
985 if ((y & 0x00000200) != 0) in _rtl92c_phy_path_a_fill_iqk_matrix()
986 y = y | 0xFFFFFC00; in _rtl92c_phy_path_a_fill_iqk_matrix()
988 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92c_phy_path_a_fill_iqk_matrix()
989 ((tx0_c & 0x3C0) >> 6)); in _rtl92c_phy_path_a_fill_iqk_matrix()
990 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92c_phy_path_a_fill_iqk_matrix()
991 (tx0_c & 0x3F)); in _rtl92c_phy_path_a_fill_iqk_matrix()
993 ((y * oldval_0 >> 7) & 0x1)); in _rtl92c_phy_path_a_fill_iqk_matrix()
997 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
998 reg = result[final_candidate][3] & 0x3F; in _rtl92c_phy_path_a_fill_iqk_matrix()
999 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
1000 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92c_phy_path_a_fill_iqk_matrix()
1001 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
1012 if (final_candidate == 0xFF) { in _rtl92c_phy_path_b_fill_iqk_matrix()
1016 MASKDWORD) >> 22) & 0x3FF; in _rtl92c_phy_path_b_fill_iqk_matrix()
1018 if ((x & 0x00000200) != 0) in _rtl92c_phy_path_b_fill_iqk_matrix()
1019 x = x | 0xFFFFFC00; in _rtl92c_phy_path_b_fill_iqk_matrix()
1021 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92c_phy_path_b_fill_iqk_matrix()
1023 ((x * oldval_1 >> 7) & 0x1)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1025 if ((y & 0x00000200) != 0) in _rtl92c_phy_path_b_fill_iqk_matrix()
1026 y = y | 0xFFFFFC00; in _rtl92c_phy_path_b_fill_iqk_matrix()
1028 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92c_phy_path_b_fill_iqk_matrix()
1029 ((tx1_c & 0x3C0) >> 6)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1030 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92c_phy_path_b_fill_iqk_matrix()
1031 (tx1_c & 0x3F)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1033 ((y * oldval_1 >> 7) & 0x1)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1037 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1038 reg = result[final_candidate][7] & 0x3F; in _rtl92c_phy_path_b_fill_iqk_matrix()
1039 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1040 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92c_phy_path_b_fill_iqk_matrix()
1041 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1051 for (i = 0; i < registernum; i++) in _rtl92c_phy_save_adda_registers()
1061 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92c_phy_save_mac_registers()
1072 for (i = 0; i < regiesternum; i++) in _rtl92c_phy_reload_adda_registers()
1082 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92c_phy_reload_mac_registers()
1093 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; in _rtl92c_phy_path_adda_on()
1095 pathon = 0x0bdb25a0; in _rtl92c_phy_path_adda_on()
1096 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); in _rtl92c_phy_path_adda_on()
1098 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); in _rtl92c_phy_path_adda_on()
1109 u32 i = 0; in _rtl92c_phy_mac_setting_calibration()
1111 rtl_write_byte(rtlpriv, macreg[i], 0x3F); in _rtl92c_phy_mac_setting_calibration()
1121 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92c_phy_path_a_standby()
1122 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl92c_phy_path_a_standby()
1123 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92c_phy_path_a_standby()
1130 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl92c_phy_pi_mode_switch()
1131 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92c_phy_pi_mode_switch()
1132 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92c_phy_pi_mode_switch()
1141 u8 final_candidate[2] = { 0xFF, 0xFF }; in _rtl92c_phy_simularity_compare()
1149 simularity_bitmap = 0; in _rtl92c_phy_simularity_compare()
1151 for (i = 0; i < bound; i++) { in _rtl92c_phy_simularity_compare()
1158 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92c_phy_simularity_compare()
1160 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92c_phy_simularity_compare()
1171 if (simularity_bitmap == 0) { in _rtl92c_phy_simularity_compare()
1172 for (i = 0; i < (bound / 4); i++) { in _rtl92c_phy_simularity_compare()
1173 if (final_candidate[i] != 0xFF) { in _rtl92c_phy_simularity_compare()
1181 } else if (!(simularity_bitmap & 0x0F)) { in _rtl92c_phy_simularity_compare()
1182 for (i = 0; i < 4; i++) in _rtl92c_phy_simularity_compare()
1185 } else if (!(simularity_bitmap & 0xF0) && is2t) { in _rtl92c_phy_simularity_compare()
1202 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl92c_phy_iq_calibrate()
1203 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92c_phy_iq_calibrate()
1204 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92c_phy_iq_calibrate()
1205 0xed8, 0xedc, 0xee0, 0xeec in _rtl92c_phy_iq_calibrate()
1208 0x522, 0x550, 0x551, 0x040 in _rtl92c_phy_iq_calibrate()
1212 if (t == 0) { in _rtl92c_phy_iq_calibrate()
1213 rtl_get_bbreg(hw, 0x800, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1221 if (t == 0) { in _rtl92c_phy_iq_calibrate()
1229 if (t == 0) { in _rtl92c_phy_iq_calibrate()
1230 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1231 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1232 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1234 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl92c_phy_iq_calibrate()
1235 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl92c_phy_iq_calibrate()
1236 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl92c_phy_iq_calibrate()
1238 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl92c_phy_iq_calibrate()
1239 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); in _rtl92c_phy_iq_calibrate()
1243 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); in _rtl92c_phy_iq_calibrate()
1245 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); in _rtl92c_phy_iq_calibrate()
1246 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92c_phy_iq_calibrate()
1247 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92c_phy_iq_calibrate()
1248 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92c_phy_iq_calibrate()
1249 for (i = 0; i < retrycount; i++) { in _rtl92c_phy_iq_calibrate()
1251 if (patha_ok == 0x03) { in _rtl92c_phy_iq_calibrate()
1252 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1253 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1254 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1255 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1256 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1257 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1258 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1259 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1261 } else if (i == (retrycount - 1) && patha_ok == 0x01) in _rtl92c_phy_iq_calibrate()
1263 result[t][0] = (rtl_get_bbreg(hw, 0xe94, in _rtl92c_phy_iq_calibrate()
1264 MASKDWORD) & 0x3FF0000) >> in _rtl92c_phy_iq_calibrate()
1267 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1274 for (i = 0; i < retrycount; i++) { in _rtl92c_phy_iq_calibrate()
1276 if (pathb_ok == 0x03) { in _rtl92c_phy_iq_calibrate()
1278 0xeb4, in _rtl92c_phy_iq_calibrate()
1280 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1282 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1283 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1285 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1286 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1288 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1289 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1291 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl92c_phy_iq_calibrate()
1293 0xeb4, in _rtl92c_phy_iq_calibrate()
1295 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1297 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1298 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1301 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); in _rtl92c_phy_iq_calibrate()
1302 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); in _rtl92c_phy_iq_calibrate()
1303 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); in _rtl92c_phy_iq_calibrate()
1304 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92c_phy_iq_calibrate()
1305 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); in _rtl92c_phy_iq_calibrate()
1307 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); in _rtl92c_phy_iq_calibrate()
1308 if (t != 0) { in _rtl92c_phy_iq_calibrate()
1329 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); in _rtl92c_phy_set_rfpath_switch()
1330 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92c_phy_set_rfpath_switch()
1335 BIT(5) | BIT(6), 0x1); in _rtl92c_phy_set_rfpath_switch()
1338 BIT(5) | BIT(6), 0x2); in _rtl92c_phy_set_rfpath_switch()
1341 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); in _rtl92c_phy_set_rfpath_switch()
1343 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); in _rtl92c_phy_set_rfpath_switch()
1360 reg_tmp = 0; in rtl92c_phy_iq_calibrate()
1381 for (i = 0; i < 8; i++) { in rtl92c_phy_iq_calibrate()
1382 result[0][i] = 0; in rtl92c_phy_iq_calibrate()
1383 result[1][i] = 0; in rtl92c_phy_iq_calibrate()
1384 result[2][i] = 0; in rtl92c_phy_iq_calibrate()
1385 result[3][i] = 0; in rtl92c_phy_iq_calibrate()
1387 final_candidate = 0xff; in rtl92c_phy_iq_calibrate()
1393 for (i = 0; i < 3; i++) { in rtl92c_phy_iq_calibrate()
1400 result, 0, in rtl92c_phy_iq_calibrate()
1403 final_candidate = 0; in rtl92c_phy_iq_calibrate()
1409 result, 0, in rtl92c_phy_iq_calibrate()
1412 final_candidate = 0; in rtl92c_phy_iq_calibrate()
1421 for (i = 0; i < 8; i++) in rtl92c_phy_iq_calibrate()
1424 if (reg_tmp != 0) in rtl92c_phy_iq_calibrate()
1427 final_candidate = 0xFF; in rtl92c_phy_iq_calibrate()
1431 for (i = 0; i < 4; i++) { in rtl92c_phy_iq_calibrate()
1432 reg_e94 = result[i][0]; in rtl92c_phy_iq_calibrate()
1439 if (final_candidate != 0xff) { in rtl92c_phy_iq_calibrate()
1440 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; in rtl92c_phy_iq_calibrate()
1449 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; in rtl92c_phy_iq_calibrate()
1450 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; in rtl92c_phy_iq_calibrate()
1452 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ in rtl92c_phy_iq_calibrate()
1455 (reg_ea4 == 0)); in rtl92c_phy_iq_calibrate()
1457 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */ in rtl92c_phy_iq_calibrate()
1461 (reg_ec4 == 0)); in rtl92c_phy_iq_calibrate()
1558 dm_digtable->cur_igvalue = 0x17; in rtl92c_phy_set_io()
1577 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl92ce_phy_set_rf_on()
1578 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ce_phy_set_rf_on()
1579 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in rtl92ce_phy_set_rf_on()
1580 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92ce_phy_set_rf_on()
1581 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ce_phy_set_rf_on()
1582 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl92ce_phy_set_rf_on()
1592 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92c_phy_set_rf_sleep()
1593 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92c_phy_set_rf_sleep()
1594 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92c_phy_set_rf_sleep()
1595 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92c_phy_set_rf_sleep()
1596 while (u4b_tmp != 0 && delay > 0) { in _rtl92c_phy_set_rf_sleep()
1597 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl92c_phy_set_rf_sleep()
1598 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92c_phy_set_rf_sleep()
1599 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92c_phy_set_rf_sleep()
1600 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92c_phy_set_rf_sleep()
1603 if (delay == 0) { in _rtl92c_phy_set_rf_sleep()
1604 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92c_phy_set_rf_sleep()
1605 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92c_phy_set_rf_sleep()
1606 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92c_phy_set_rf_sleep()
1607 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92c_phy_set_rf_sleep()
1612 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92c_phy_set_rf_sleep()
1613 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92c_phy_set_rf_sleep()