Lines Matching refs:rtl_set_bbreg
164 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl88e_phy_rf_serial_read()
167 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl88e_phy_rf_serial_read()
204 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl88e_phy_rf_serial_write()
326 rtl_set_bbreg(hw, addr, MASKDWORD, data); in _rtl8188e_config_bb_reg()
443 rtl_set_bbreg(hw, array_table[i], MASKDWORD, in handle_branch2()
467 rtl_set_bbreg(hw, array_table[i], in handle_branch2()
1105 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl88e_phy_set_bw_mode_callback()
1106 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl88e_phy_set_bw_mode_callback()
1110 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl88e_phy_set_bw_mode_callback()
1111 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl88e_phy_set_bw_mode_callback()
1113 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, in rtl88e_phy_set_bw_mode_callback()
1115 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl88e_phy_set_bw_mode_callback()
1118 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl88e_phy_set_bw_mode_callback()
1348 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_iqk()
1349 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_iqk()
1350 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); in _rtl88e_phy_path_a_iqk()
1351 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); in _rtl88e_phy_path_a_iqk()
1353 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl88e_phy_path_a_iqk()
1354 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_iqk()
1355 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_iqk()
1376 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl88e_phy_path_b_iqk()
1377 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl88e_phy_path_b_iqk()
1405 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl88e_phy_path_a_rx_iqk()
1410 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_rx_iqk()
1413 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl88e_phy_path_a_rx_iqk()
1414 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); in _rtl88e_phy_path_a_rx_iqk()
1417 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_rx_iqk()
1418 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_rx_iqk()
1419 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); in _rtl88e_phy_path_a_rx_iqk()
1420 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); in _rtl88e_phy_path_a_rx_iqk()
1423 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl88e_phy_path_a_rx_iqk()
1425 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_rx_iqk()
1426 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_rx_iqk()
1444 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl88e_phy_path_a_rx_iqk()
1447 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl88e_phy_path_a_rx_iqk()
1452 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_rx_iqk()
1455 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl88e_phy_path_a_rx_iqk()
1458 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_rx_iqk()
1459 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_rx_iqk()
1460 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); in _rtl88e_phy_path_a_rx_iqk()
1461 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); in _rtl88e_phy_path_a_rx_iqk()
1464 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl88e_phy_path_a_rx_iqk()
1466 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_rx_iqk()
1467 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_rx_iqk()
1499 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl88e_phy_path_a_fill_iqk_matrix()
1500 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), in _rtl88e_phy_path_a_fill_iqk_matrix()
1506 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl88e_phy_path_a_fill_iqk_matrix()
1508 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl88e_phy_path_a_fill_iqk_matrix()
1510 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), in _rtl88e_phy_path_a_fill_iqk_matrix()
1515 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1517 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1519 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1551 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); in _rtl88e_phy_reload_adda_registers()
1574 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); in _rtl88e_phy_path_adda_on()
1576 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); in _rtl88e_phy_path_adda_on()
1580 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); in _rtl88e_phy_path_adda_on()
1599 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl88e_phy_path_a_standby()
1600 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl88e_phy_path_a_standby()
1601 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_standby()
1609 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl88e_phy_pi_mode_switch()
1610 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl88e_phy_pi_mode_switch()
1714 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); in _rtl88e_phy_iq_calibrate()
1715 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl88e_phy_iq_calibrate()
1716 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl88e_phy_iq_calibrate()
1717 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl88e_phy_iq_calibrate()
1719 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); in _rtl88e_phy_iq_calibrate()
1720 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); in _rtl88e_phy_iq_calibrate()
1721 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); in _rtl88e_phy_iq_calibrate()
1722 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); in _rtl88e_phy_iq_calibrate()
1725 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl88e_phy_iq_calibrate()
1726 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); in _rtl88e_phy_iq_calibrate()
1730 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl88e_phy_iq_calibrate()
1732 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl88e_phy_iq_calibrate()
1734 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl88e_phy_iq_calibrate()
1735 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl88e_phy_iq_calibrate()
1736 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); in _rtl88e_phy_iq_calibrate()
1800 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl88e_phy_iq_calibrate()
1813 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); in _rtl88e_phy_iq_calibrate()
1815 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); in _rtl88e_phy_iq_calibrate()
1816 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl88e_phy_iq_calibrate()
1817 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl88e_phy_iq_calibrate()
1880 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl88e_phy_set_rfpath_switch()
1884 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl88e_phy_set_rfpath_switch()
1887 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl88e_phy_set_rfpath_switch()
1890 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl88e_phy_set_rfpath_switch()
1891 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl88e_phy_set_rfpath_switch()
1898 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl88e_phy_set_rfpath_switch()
1900 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl88e_phy_set_rfpath_switch()
1903 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl88e_phy_set_rfpath_switch()
1905 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl88e_phy_set_rfpath_switch()
1907 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl88e_phy_set_rfpath_switch()
1910 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); in _rtl88e_phy_set_rfpath_switch()
2111 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); in rtl88e_phy_set_io()
2116 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); in rtl88e_phy_set_io()