157 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in _rtl88e_phy_rf_serial_read()
161 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in _rtl88e_phy_rf_serial_read()
170 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,  in _rtl88e_phy_rf_serial_read()
173 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,  in _rtl88e_phy_rf_serial_read()
176 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,  in _rtl88e_phy_rf_serial_read()
179 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,  in _rtl88e_phy_rf_serial_read()
360 	  (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));  in _rtl88e_phy_bb8188e_config_parafile()
781 	    (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);  in rtl88e_phy_get_hw_reg_originalvalue()
783 	    (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);  in rtl88e_phy_get_hw_reg_originalvalue()
785 	    (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);  in rtl88e_phy_get_hw_reg_originalvalue()
787 	    (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);  in rtl88e_phy_get_hw_reg_originalvalue()
796 	rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,  in rtl88e_phy_get_hw_reg_originalvalue()
798 	rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,  in rtl88e_phy_get_hw_reg_originalvalue()
1359 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl88e_phy_path_a_iqk()
1360 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl88e_phy_path_a_iqk()
1361 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl88e_phy_path_a_iqk()
1362 	rtl_get_bbreg(hw, 0xea4, MASKDWORD);  in _rtl88e_phy_path_a_iqk()
1379 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl88e_phy_path_b_iqk()
1380 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);  in _rtl88e_phy_path_b_iqk()
1381 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);  in _rtl88e_phy_path_b_iqk()
1382 	reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);  in _rtl88e_phy_path_b_iqk()
1383 	reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);  in _rtl88e_phy_path_b_iqk()
1430 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl88e_phy_path_a_rx_iqk()
1431 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl88e_phy_path_a_rx_iqk()
1432 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl88e_phy_path_a_rx_iqk()
1471 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl88e_phy_path_a_rx_iqk()
1472 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl88e_phy_path_a_rx_iqk()
1473 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl88e_phy_path_a_rx_iqk()
1474 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl88e_phy_path_a_rx_iqk()
1493 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,  in _rtl88e_phy_path_a_fill_iqk_matrix()
1530 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in _rtl88e_phy_save_adda_registers()
1708 		  (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8));  in _rtl88e_phy_iq_calibrate()
1742 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()
1744 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()
1755 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()
1757 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()
1775 				result[t][4] = (rtl_get_bbreg(hw,  in _rtl88e_phy_iq_calibrate()
1780 				    (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()
1783 				    (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()
1786 				    (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()
1790 				result[t][4] = (rtl_get_bbreg(hw,  in _rtl88e_phy_iq_calibrate()
1795 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &  in _rtl88e_phy_iq_calibrate()