Lines Matching refs:RFREG_OFFSET_MASK
120 if (bitmask != RFREG_OFFSET_MASK) { in rtl88e_phy_set_rf_reg()
294 RFREG_OFFSET_MASK, in _rtl8188e_config_rf_reg()
1301 RFREG_OFFSET_MASK, in _rtl88e_phy_sw_chnl_step_by_step()
1406 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1407 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1408 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1409 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl88e_phy_path_a_rx_iqk()
1448 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1449 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1450 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1451 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl88e_phy_path_a_rx_iqk()
2146 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl88ee_phy_set_rf_sleep()