Lines Matching +full:0 +full:x80800000
52 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, in rtl88e_phy_query_bb_reg()
148 u8 rfpi_enable = 0; in _rtl88e_phy_rf_serial_read()
151 offset &= 0xff; in _rtl88e_phy_rf_serial_read()
155 return 0xFFFFFFFF; in _rtl88e_phy_rf_serial_read()
182 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_read()
201 offset &= 0xff; in _rtl88e_phy_rf_serial_write()
203 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl88e_phy_rf_serial_write()
206 "RFW-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_write()
215 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl88e_phy_mac_config()
229 regval | BIT(13) | BIT(0) | BIT(1)); in rtl88e_phy_bb_config()
235 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl88e_phy_bb_config()
236 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl88e_phy_bb_config()
254 u32 _platform = 0x08;/*SupportPlatform */ in _rtl88e_check_condition()
257 if (condition == 0xCDCDCDCD) in _rtl88e_check_condition()
260 cond = condition & 0xFF; in _rtl88e_check_condition()
261 if ((_board & cond) == 0 && cond != 0x1F) in _rtl88e_check_condition()
264 cond = condition & 0xFF00; in _rtl88e_check_condition()
266 if ((_interface & cond) == 0 && cond != 0x07) in _rtl88e_check_condition()
269 cond = condition & 0xFF0000; in _rtl88e_check_condition()
271 if ((_platform & cond) == 0 && cond != 0x0F) in _rtl88e_check_condition()
280 if (addr == 0xffe) { in _rtl8188e_config_rf_reg()
282 } else if (addr == 0xfd) { in _rtl8188e_config_rf_reg()
284 } else if (addr == 0xfc) { in _rtl8188e_config_rf_reg()
286 } else if (addr == 0xfb) { in _rtl8188e_config_rf_reg()
288 } else if (addr == 0xfa) { in _rtl8188e_config_rf_reg()
290 } else if (addr == 0xf9) { in _rtl8188e_config_rf_reg()
303 u32 content = 0x1000; /*RF Content: radio_a_txt*/ in _rtl8188e_config_rf_radio_a()
304 u32 maskforphyset = (u32)(content & 0xE000); in _rtl8188e_config_rf_radio_a()
313 if (addr == 0xfe) { in _rtl8188e_config_bb_reg()
315 } else if (addr == 0xfd) { in _rtl8188e_config_bb_reg()
317 } else if (addr == 0xfc) { in _rtl8188e_config_bb_reg()
319 } else if (addr == 0xfb) { in _rtl8188e_config_bb_reg()
321 } else if (addr == 0xfa) { in _rtl8188e_config_bb_reg()
323 } else if (addr == 0xf9) { in _rtl8188e_config_bb_reg()
345 rtlphy->pwrgroup_cnt = 0; in _rtl88e_phy_bb8188e_config_parafile()
360 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl88e_phy_bb8188e_config_parafile()
377 for (i = 0; i < arraylength; i = i + 2) in _rtl88e_phy_config_mac_with_headerfile()
386 } while (0)
395 for (i = 0; i < arraylen; i = i + 2) { in handle_branch1()
398 if (v1 < 0xcdcdcdcd) { in handle_branch1()
408 while (v2 != 0xDEAD && in handle_branch1()
409 v2 != 0xCDEF && in handle_branch1()
410 v2 != 0xCDCD && i < arraylen - 2) in handle_branch1()
417 while (v2 != 0xDEAD && in handle_branch1()
418 v2 != 0xCDEF && in handle_branch1()
419 v2 != 0xCDCD && i < arraylen - 2) { in handle_branch1()
424 while (v2 != 0xDEAD && i < arraylen - 2) in handle_branch1()
439 for (i = 0; i < arraylen; i = i + 2) { in handle_branch2()
442 if (v1 < 0xCDCDCDCD) { in handle_branch2()
455 while (v2 != 0xDEAD && in handle_branch2()
456 v2 != 0xCDEF && in handle_branch2()
457 v2 != 0xCDCD && i < arraylen - 2) in handle_branch2()
464 while (v2 != 0xDEAD && in handle_branch2()
465 v2 != 0xCDEF && in handle_branch2()
466 v2 != 0xCDCD && i < arraylen - 2) { in handle_branch2()
474 while (v2 != 0xDEAD && i < arraylen - 2) in handle_branch2()
479 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", in handle_branch2()
511 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data; in store_pwrindex_rate_offset()
513 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", in store_pwrindex_rate_offset()
515 rtlphy->mcs_txpwrlevel_origoffset[count][0]); in store_pwrindex_rate_offset()
520 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", in store_pwrindex_rate_offset()
527 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", in store_pwrindex_rate_offset()
531 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { in store_pwrindex_rate_offset()
534 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", in store_pwrindex_rate_offset()
541 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", in store_pwrindex_rate_offset()
548 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", in store_pwrindex_rate_offset()
555 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", in store_pwrindex_rate_offset()
566 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", in store_pwrindex_rate_offset()
573 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", in store_pwrindex_rate_offset()
580 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", in store_pwrindex_rate_offset()
587 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", in store_pwrindex_rate_offset()
591 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { in store_pwrindex_rate_offset()
594 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", in store_pwrindex_rate_offset()
601 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", in store_pwrindex_rate_offset()
608 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", in store_pwrindex_rate_offset()
615 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", in store_pwrindex_rate_offset()
622 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", in store_pwrindex_rate_offset()
638 u32 v1 = 0, v2 = 0; in phy_config_bb_with_pghdr()
644 for (i = 0; i < phy_reg_page_len; i = i + 3) { in phy_config_bb_with_pghdr()
648 if (v1 < 0xcdcdcdcd) { in phy_config_bb_with_pghdr()
649 if (phy_reg_page[i] == 0xfe) in phy_config_bb_with_pghdr()
651 else if (phy_reg_page[i] == 0xfd) in phy_config_bb_with_pghdr()
653 else if (phy_reg_page[i] == 0xfc) in phy_config_bb_with_pghdr()
655 else if (phy_reg_page[i] == 0xfb) in phy_config_bb_with_pghdr()
657 else if (phy_reg_page[i] == 0xfa) in phy_config_bb_with_pghdr()
659 else if (phy_reg_page[i] == 0xf9) in phy_config_bb_with_pghdr()
677 while (v2 != 0xDEAD && in phy_config_bb_with_pghdr()
698 } while (0)
708 for (i = 0; i < radioa_arraylen; i = i + 2) { in process_path_a()
711 if (v1 < 0xcdcdcdcd) { in process_path_a()
721 while (v2 != 0xDEAD && in process_path_a()
722 v2 != 0xCDEF && in process_path_a()
723 v2 != 0xCDCD && in process_path_a()
732 while (v2 != 0xDEAD && in process_path_a()
733 v2 != 0xCDEF && in process_path_a()
734 v2 != 0xCDCD && in process_path_a()
740 while (v2 != 0xDEAD && in process_path_a()
748 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD); in process_path_a()
780 rtlphy->default_initialgain[0] = in rtl88e_phy_get_hw_reg_originalvalue()
790 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl88e_phy_get_hw_reg_originalvalue()
791 rtlphy->default_initialgain[0], in rtl88e_phy_get_hw_reg_originalvalue()
802 "Default framesync (0x%x) = 0x%x\n", in rtl88e_phy_get_hw_reg_originalvalue()
926 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f) in handle_path_a()
934 if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf) in handle_path_a()
952 u8 rf_path = 0; in _rtl88e_get_txpower_index()
954 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl88e_get_txpower_index()
983 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl88e_ccxpower_index_check()
984 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl88e_ccxpower_index_check()
985 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0]; in _rtl88e_ccxpower_index_check()
986 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0]; in _rtl88e_ccxpower_index_check()
993 u8 cckpowerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
994 u8 ofdmpowerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
995 u8 bw20powerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
996 u8 bw40powerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
1001 &cckpowerlevel[0], &ofdmpowerlevel[0], in rtl88e_phy_set_txpower_level()
1002 &bw20powerlevel[0], &bw40powerlevel[0]); in rtl88e_phy_set_txpower_level()
1004 &cckpowerlevel[0], &ofdmpowerlevel[0], in rtl88e_phy_set_txpower_level()
1005 &bw20powerlevel[0], &bw40powerlevel[0]); in rtl88e_phy_set_txpower_level()
1006 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl88e_phy_set_txpower_level()
1007 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], in rtl88e_phy_set_txpower_level()
1008 &bw20powerlevel[0], in rtl88e_phy_set_txpower_level()
1009 &bw40powerlevel[0], channel); in rtl88e_phy_set_txpower_level()
1094 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); in rtl88e_phy_set_bw_mode_callback()
1105 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl88e_phy_set_bw_mode_callback()
1106 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl88e_phy_set_bw_mode_callback()
1110 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl88e_phy_set_bw_mode_callback()
1111 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl88e_phy_set_bw_mode_callback()
1115 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl88e_phy_set_bw_mode_callback()
1116 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ in rtl88e_phy_set_bw_mode_callback()
1118 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl88e_phy_set_bw_mode_callback()
1170 if (delay > 0) in rtl88e_phy_sw_chnl_callback()
1189 return 0; in rtl88e_phy_sw_chnl()
1191 return 0; in rtl88e_phy_sw_chnl()
1195 rtlphy->sw_chnl_stage = 0; in rtl88e_phy_sw_chnl()
1196 rtlphy->sw_chnl_step = 0; in rtl88e_phy_sw_chnl()
1227 precommoncmdcnt = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1230 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl88e_phy_sw_chnl_step_by_step()
1232 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl88e_phy_sw_chnl_step_by_step()
1234 postcommoncmdcnt = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1237 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl88e_phy_sw_chnl_step_by_step()
1239 rfdependcmdcnt = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1249 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, in _rtl88e_phy_sw_chnl_step_by_step()
1250 0); in _rtl88e_phy_sw_chnl_step_by_step()
1254 case 0: in _rtl88e_phy_sw_chnl_step_by_step()
1273 (*step) = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1294 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl88e_phy_sw_chnl_step_by_step()
1297 0xfffffc00) | currentcmd->para2); in _rtl88e_phy_sw_chnl_step_by_step()
1346 u8 result = 0x00; in _rtl88e_phy_path_a_iqk()
1348 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_iqk()
1349 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_iqk()
1350 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); in _rtl88e_phy_path_a_iqk()
1351 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); in _rtl88e_phy_path_a_iqk()
1353 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl88e_phy_path_a_iqk()
1354 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_iqk()
1355 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_iqk()
1359 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1360 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1361 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1362 rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1365 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl88e_phy_path_a_iqk()
1366 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl88e_phy_path_a_iqk()
1367 result |= 0x01; in _rtl88e_phy_path_a_iqk()
1374 u8 result = 0x00; in _rtl88e_phy_path_b_iqk()
1376 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl88e_phy_path_b_iqk()
1377 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl88e_phy_path_b_iqk()
1379 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1380 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1381 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1382 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1383 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1386 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl88e_phy_path_b_iqk()
1387 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) in _rtl88e_phy_path_b_iqk()
1388 result |= 0x01; in _rtl88e_phy_path_b_iqk()
1392 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl88e_phy_path_b_iqk()
1393 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) in _rtl88e_phy_path_b_iqk()
1394 result |= 0x02; in _rtl88e_phy_path_b_iqk()
1401 u8 result = 0x00; in _rtl88e_phy_path_a_rx_iqk()
1405 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl88e_phy_path_a_rx_iqk()
1406 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1407 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1408 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1409 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl88e_phy_path_a_rx_iqk()
1410 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_rx_iqk()
1413 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl88e_phy_path_a_rx_iqk()
1414 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); in _rtl88e_phy_path_a_rx_iqk()
1417 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_rx_iqk()
1418 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_rx_iqk()
1419 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); in _rtl88e_phy_path_a_rx_iqk()
1420 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); in _rtl88e_phy_path_a_rx_iqk()
1423 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl88e_phy_path_a_rx_iqk()
1425 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_rx_iqk()
1426 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_rx_iqk()
1436 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl88e_phy_path_a_rx_iqk()
1437 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl88e_phy_path_a_rx_iqk()
1438 result |= 0x01; in _rtl88e_phy_path_a_rx_iqk()
1442 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) | in _rtl88e_phy_path_a_rx_iqk()
1443 ((reg_e9c&0x3FF0000) >> 16); in _rtl88e_phy_path_a_rx_iqk()
1447 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl88e_phy_path_a_rx_iqk()
1448 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1449 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1450 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1451 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl88e_phy_path_a_rx_iqk()
1452 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_rx_iqk()
1455 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl88e_phy_path_a_rx_iqk()
1458 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_rx_iqk()
1459 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_rx_iqk()
1460 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); in _rtl88e_phy_path_a_rx_iqk()
1461 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); in _rtl88e_phy_path_a_rx_iqk()
1464 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl88e_phy_path_a_rx_iqk()
1466 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_rx_iqk()
1467 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_rx_iqk()
1477 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl88e_phy_path_a_rx_iqk()
1478 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl88e_phy_path_a_rx_iqk()
1479 result |= 0x02; in _rtl88e_phy_path_a_rx_iqk()
1490 if (final_candidate == 0xFF) { in _rtl88e_phy_path_a_fill_iqk_matrix()
1494 MASKDWORD) >> 22) & 0x3FF; in _rtl88e_phy_path_a_fill_iqk_matrix()
1495 x = result[final_candidate][0]; in _rtl88e_phy_path_a_fill_iqk_matrix()
1496 if ((x & 0x00000200) != 0) in _rtl88e_phy_path_a_fill_iqk_matrix()
1497 x = x | 0xFFFFFC00; in _rtl88e_phy_path_a_fill_iqk_matrix()
1499 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl88e_phy_path_a_fill_iqk_matrix()
1501 ((x * oldval_0 >> 7) & 0x1)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1503 if ((y & 0x00000200) != 0) in _rtl88e_phy_path_a_fill_iqk_matrix()
1504 y = y | 0xFFFFFC00; in _rtl88e_phy_path_a_fill_iqk_matrix()
1506 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl88e_phy_path_a_fill_iqk_matrix()
1507 ((tx0_c & 0x3C0) >> 6)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1508 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl88e_phy_path_a_fill_iqk_matrix()
1509 (tx0_c & 0x3F)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1511 ((y * oldval_0 >> 7) & 0x1)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1515 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1516 reg = result[final_candidate][3] & 0x3F; in _rtl88e_phy_path_a_fill_iqk_matrix()
1517 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1518 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl88e_phy_path_a_fill_iqk_matrix()
1519 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1529 for (i = 0; i < registernum; i++) in _rtl88e_phy_save_adda_registers()
1539 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl88e_phy_save_mac_registers()
1550 for (i = 0; i < regiesternum; i++) in _rtl88e_phy_reload_adda_registers()
1560 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl88e_phy_reload_mac_registers()
1571 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; in _rtl88e_phy_path_adda_on()
1573 pathon = 0x0bdb25a0; in _rtl88e_phy_path_adda_on()
1574 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); in _rtl88e_phy_path_adda_on()
1576 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); in _rtl88e_phy_path_adda_on()
1587 u32 i = 0; in _rtl88e_phy_mac_setting_calibration()
1589 rtl_write_byte(rtlpriv, macreg[i], 0x3F); in _rtl88e_phy_mac_setting_calibration()
1599 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl88e_phy_path_a_standby()
1600 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl88e_phy_path_a_standby()
1601 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_standby()
1608 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl88e_phy_pi_mode_switch()
1609 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl88e_phy_pi_mode_switch()
1610 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl88e_phy_pi_mode_switch()
1619 u8 final_candidate[2] = { 0xFF, 0xFF }; in _rtl88e_phy_simularity_compare()
1627 simularity_bitmap = 0; in _rtl88e_phy_simularity_compare()
1629 for (i = 0; i < bound; i++) { in _rtl88e_phy_simularity_compare()
1636 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl88e_phy_simularity_compare()
1638 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl88e_phy_simularity_compare()
1649 if (simularity_bitmap == 0) { in _rtl88e_phy_simularity_compare()
1650 for (i = 0; i < (bound / 4); i++) { in _rtl88e_phy_simularity_compare()
1651 if (final_candidate[i] != 0xFF) { in _rtl88e_phy_simularity_compare()
1659 } else if (!(simularity_bitmap & 0x0F)) { in _rtl88e_phy_simularity_compare()
1660 for (i = 0; i < 4; i++) in _rtl88e_phy_simularity_compare()
1663 } else if (!(simularity_bitmap & 0xF0) && is2t) { in _rtl88e_phy_simularity_compare()
1681 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl88e_phy_iq_calibrate()
1682 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl88e_phy_iq_calibrate()
1683 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl88e_phy_iq_calibrate()
1684 0xed8, 0xedc, 0xee0, 0xeec in _rtl88e_phy_iq_calibrate()
1687 0x522, 0x550, 0x551, 0x040 in _rtl88e_phy_iq_calibrate()
1691 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, in _rtl88e_phy_iq_calibrate()
1692 0x870, 0x860, 0x864, 0x800 in _rtl88e_phy_iq_calibrate()
1696 if (t == 0) { in _rtl88e_phy_iq_calibrate()
1706 if (t == 0) { in _rtl88e_phy_iq_calibrate()
1714 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); in _rtl88e_phy_iq_calibrate()
1715 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl88e_phy_iq_calibrate()
1716 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl88e_phy_iq_calibrate()
1717 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl88e_phy_iq_calibrate()
1719 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); in _rtl88e_phy_iq_calibrate()
1720 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); in _rtl88e_phy_iq_calibrate()
1721 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); in _rtl88e_phy_iq_calibrate()
1722 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); in _rtl88e_phy_iq_calibrate()
1725 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl88e_phy_iq_calibrate()
1726 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); in _rtl88e_phy_iq_calibrate()
1730 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl88e_phy_iq_calibrate()
1732 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl88e_phy_iq_calibrate()
1734 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl88e_phy_iq_calibrate()
1735 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl88e_phy_iq_calibrate()
1736 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); in _rtl88e_phy_iq_calibrate()
1737 for (i = 0; i < retrycount; i++) { in _rtl88e_phy_iq_calibrate()
1739 if (patha_ok == 0x01) { in _rtl88e_phy_iq_calibrate()
1742 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1743 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1744 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1745 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1750 for (i = 0; i < retrycount; i++) { in _rtl88e_phy_iq_calibrate()
1752 if (patha_ok == 0x03) { in _rtl88e_phy_iq_calibrate()
1755 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1756 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1757 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1758 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1766 if (0 == patha_ok) in _rtl88e_phy_iq_calibrate()
1772 for (i = 0; i < retrycount; i++) { in _rtl88e_phy_iq_calibrate()
1774 if (pathb_ok == 0x03) { in _rtl88e_phy_iq_calibrate()
1776 0xeb4, in _rtl88e_phy_iq_calibrate()
1778 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1780 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1781 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1783 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1784 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1786 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1787 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1789 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl88e_phy_iq_calibrate()
1791 0xeb4, in _rtl88e_phy_iq_calibrate()
1793 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1795 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1796 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1800 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl88e_phy_iq_calibrate()
1802 if (t != 0) { in _rtl88e_phy_iq_calibrate()
1813 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); in _rtl88e_phy_iq_calibrate()
1815 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); in _rtl88e_phy_iq_calibrate()
1816 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl88e_phy_iq_calibrate()
1817 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl88e_phy_iq_calibrate()
1825 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; in _rtl88e_phy_lc_calibrate()
1828 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl88e_phy_lc_calibrate()
1830 if ((tmpreg & 0x70) != 0) in _rtl88e_phy_lc_calibrate()
1831 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl88e_phy_lc_calibrate()
1833 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl88e_phy_lc_calibrate()
1835 if ((tmpreg & 0x70) != 0) { in _rtl88e_phy_lc_calibrate()
1836 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl88e_phy_lc_calibrate()
1839 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, in _rtl88e_phy_lc_calibrate()
1842 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl88e_phy_lc_calibrate()
1843 (rf_a_mode & 0x8FFFF) | 0x10000); in _rtl88e_phy_lc_calibrate()
1846 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl88e_phy_lc_calibrate()
1847 (rf_b_mode & 0x8FFFF) | 0x10000); in _rtl88e_phy_lc_calibrate()
1849 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl88e_phy_lc_calibrate()
1851 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl88e_phy_lc_calibrate()
1855 if ((tmpreg & 0x70) != 0) { in _rtl88e_phy_lc_calibrate()
1856 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl88e_phy_lc_calibrate()
1857 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl88e_phy_lc_calibrate()
1860 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl88e_phy_lc_calibrate()
1863 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl88e_phy_lc_calibrate()
1880 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl88e_phy_set_rfpath_switch()
1885 BIT(5) | BIT(6), 0x1); in _rtl88e_phy_set_rfpath_switch()
1888 BIT(5) | BIT(6), 0x2); in _rtl88e_phy_set_rfpath_switch()
1890 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl88e_phy_set_rfpath_switch()
1891 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl88e_phy_set_rfpath_switch()
1899 BIT(14) | BIT(13) | BIT(12), 0); in _rtl88e_phy_set_rfpath_switch()
1901 BIT(5) | BIT(4) | BIT(3), 0); in _rtl88e_phy_set_rfpath_switch()
1903 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl88e_phy_set_rfpath_switch()
1926 reg_tmp = 0; in rtl88e_phy_iq_calibrate()
1947 for (i = 0; i < 8; i++) { in rtl88e_phy_iq_calibrate()
1948 result[0][i] = 0; in rtl88e_phy_iq_calibrate()
1949 result[1][i] = 0; in rtl88e_phy_iq_calibrate()
1950 result[2][i] = 0; in rtl88e_phy_iq_calibrate()
1951 result[3][i] = 0; in rtl88e_phy_iq_calibrate()
1953 final_candidate = 0xff; in rtl88e_phy_iq_calibrate()
1958 for (i = 0; i < 3; i++) { in rtl88e_phy_iq_calibrate()
1965 _rtl88e_phy_simularity_compare(hw, result, 0, 1); in rtl88e_phy_iq_calibrate()
1967 final_candidate = 0; in rtl88e_phy_iq_calibrate()
1973 _rtl88e_phy_simularity_compare(hw, result, 0, 2); in rtl88e_phy_iq_calibrate()
1975 final_candidate = 0; in rtl88e_phy_iq_calibrate()
1983 for (i = 0; i < 8; i++) in rtl88e_phy_iq_calibrate()
1986 if (reg_tmp != 0) in rtl88e_phy_iq_calibrate()
1989 final_candidate = 0xFF; in rtl88e_phy_iq_calibrate()
1993 for (i = 0; i < 4; i++) { in rtl88e_phy_iq_calibrate()
1994 reg_e94 = result[i][0]; in rtl88e_phy_iq_calibrate()
2000 if (final_candidate != 0xff) { in rtl88e_phy_iq_calibrate()
2001 reg_e94 = result[final_candidate][0]; in rtl88e_phy_iq_calibrate()
2012 rtlphy->reg_e94 = 0x100; in rtl88e_phy_iq_calibrate()
2013 rtlphy->reg_eb4 = 0x100; in rtl88e_phy_iq_calibrate()
2014 rtlphy->reg_e9c = 0x0; in rtl88e_phy_iq_calibrate()
2015 rtlphy->reg_ebc = 0x0; in rtl88e_phy_iq_calibrate()
2017 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ in rtl88e_phy_iq_calibrate()
2020 (reg_ea4 == 0)); in rtl88e_phy_iq_calibrate()
2021 if (final_candidate != 0xFF) { in rtl88e_phy_iq_calibrate()
2022 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl88e_phy_iq_calibrate()
2023 rtlphy->iqk_matrix[0].value[0][i] = in rtl88e_phy_iq_calibrate()
2025 rtlphy->iqk_matrix[0].iqk_done = true; in rtl88e_phy_iq_calibrate()
2037 u32 timeout = 2000, timecount = 0; in rtl88e_phy_lc_calibrate()
2111 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); in rtl88e_phy_set_io()
2115 dm_digtable->cur_igvalue = 0x17; in rtl88e_phy_set_io()
2116 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); in rtl88e_phy_set_io()
2133 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl88ee_phy_set_rf_on()
2134 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl88ee_phy_set_rf_on()
2135 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ in rtl88ee_phy_set_rf_on()
2136 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl88ee_phy_set_rf_on()
2137 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl88ee_phy_set_rf_on()
2138 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl88ee_phy_set_rf_on()
2145 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl88ee_phy_set_rf_sleep()
2146 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl88ee_phy_set_rf_sleep()
2147 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl88ee_phy_set_rf_sleep()
2148 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl88ee_phy_set_rf_sleep()
2167 u32 initializecount = 0; in _rtl88ee_phy_set_rf_power_state()
2195 for (queue_id = 0, i = 0; in _rtl88ee_phy_set_rf_power_state()
2199 skb_queue_len(&ring->queue) == 0) { in _rtl88ee_phy_set_rf_power_state()
2239 for (queue_id = 0, i = 0; in _rtl88ee_phy_set_rf_power_state()
2242 if (skb_queue_len(&ring->queue) == 0) { in _rtl88ee_phy_set_rf_power_state()