Lines Matching full:bit
10 #define SYS_ISO_MD2PP BIT(0)
11 #define SYS_ISO_ANALOG_IPS BIT(5)
12 #define SYS_ISO_DIOR BIT(9)
13 #define SYS_ISO_PWC_EV25V BIT(14)
14 #define SYS_ISO_PWC_EV12V BIT(15)
17 #define SYS_FUNC_BBRSTB BIT(0)
18 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
19 #define SYS_FUNC_USBA BIT(2)
20 #define SYS_FUNC_UPLL BIT(3)
21 #define SYS_FUNC_USBD BIT(4)
22 #define SYS_FUNC_DIO_PCIE BIT(5)
23 #define SYS_FUNC_PCIEA BIT(6)
24 #define SYS_FUNC_PPLL BIT(7)
25 #define SYS_FUNC_PCIED BIT(8)
26 #define SYS_FUNC_DIOE BIT(9)
27 #define SYS_FUNC_CPU_ENABLE BIT(10)
28 #define SYS_FUNC_DCORE BIT(11)
29 #define SYS_FUNC_ELDR BIT(12)
30 #define SYS_FUNC_DIO_RF BIT(13)
31 #define SYS_FUNC_HWPDN BIT(14)
32 #define SYS_FUNC_MREGEN BIT(15)
35 #define APS_FSMCO_PFM_ALDN BIT(1)
36 #define APS_FSMCO_PFM_WOWL BIT(3)
37 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4)
38 #define APS_FSMCO_MAC_ENABLE BIT(8)
39 #define APS_FSMCO_MAC_OFF BIT(9)
40 #define APS_FSMCO_SW_LPS BIT(10)
41 #define APS_FSMCO_HW_SUSPEND BIT(11)
42 #define APS_FSMCO_PCIE BIT(12)
43 #define APS_FSMCO_HW_POWERDOWN BIT(15)
44 #define APS_FSMCO_WLON_RESET BIT(16)
47 #define SYS_CLK_ANAD16V_ENABLE BIT(0)
48 #define SYS_CLK_ANA8M BIT(1)
49 #define SYS_CLK_MACSLP BIT(4)
50 #define SYS_CLK_LOADER_ENABLE BIT(5)
51 #define SYS_CLK_80M_SSC_DISABLE BIT(7)
52 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8)
53 #define SYS_CLK_PHY_SSC_RSTB BIT(9)
54 #define SYS_CLK_SEC_CLK_ENABLE BIT(10)
55 #define SYS_CLK_MAC_CLK_ENABLE BIT(11)
56 #define SYS_CLK_ENABLE BIT(12)
57 #define SYS_CLK_RING_CLK_ENABLE BIT(13)
60 #define EEPROM_BOOT BIT(4)
61 #define EEPROM_ENABLE BIT(5)
65 #define AFE_MISC_WL_XTAL_CTRL BIT(6)
72 #define RSV_CTRL_WLOCK_1C BIT(5)
73 #define RSV_CTRL_DIS_PRST BIT(6)
76 #define RF_ENABLE BIT(0)
77 #define RF_RSTB BIT(1)
78 #define RF_SDMRSTB BIT(2)
81 #define LDOA15_ENABLE BIT(0)
82 #define LDOA15_STANDBY BIT(1)
83 #define LDOA15_OBUF BIT(2)
84 #define LDOA15_REG_VOS BIT(3)
88 #define LDOV12D_ENABLE BIT(0)
89 #define LDOV12D_STANDBY BIT(1)
95 #define LPLDO_HSM BIT(2)
96 #define LPLDO_LSM_DIS BIT(3)
99 #define AFE_XTAL_ENABLE BIT(0)
100 #define AFE_XTAL_B_SELECT BIT(1)
101 #define AFE_XTAL_GATE_USB BIT(8)
102 #define AFE_XTAL_GATE_AFE BIT(11)
103 #define AFE_XTAL_RF_GATE BIT(14)
104 #define AFE_XTAL_GATE_DIG BIT(17)
105 #define AFE_XTAL_BT_GATE BIT(20)
111 #define AFE_PLL_ENABLE BIT(0)
112 #define AFE_PLL_320_ENABLE BIT(1)
113 #define APE_PLL_FREF_SELECT BIT(2)
114 #define AFE_PLL_EDGE_SELECT BIT(3)
115 #define AFE_PLL_WDOGB BIT(4)
116 #define AFE_PLL_LPF_ENABLE BIT(5)
122 #define EFUSE_TRPT BIT(7)
124 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
125 #define EFUSE_LDOE25_ENABLE BIT(31)
136 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11)
141 #define GPIO_MUXCFG_IO_SEL_ENBT BIT(5)
146 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9)
153 #define LEDCFG0_LED0SV BIT(3)
154 #define LEDCFG0_LED1SV BIT(11)
157 #define LEDCFG0_LED0_IO_MODE BIT(7)
158 #define LEDCFG0_LED1_IO_MODE BIT(15)
161 #define LEDCFG0_LED2EN BIT(21)
164 #define LEDCFG0_DPDT_SELECT BIT(23)
166 #define LEDCFG1_HW_LED_CONTROL BIT(1)
167 #define LEDCFG1_LED_DISABLE BIT(7)
169 #define LEDCFG2_HW_LED_CONTROL BIT(1)
170 #define LEDCFG2_HW_LED_ENABLE BIT(5)
171 #define LEDCFG2_SW_LED_DISABLE BIT(3)
172 #define LEDCFG2_SW_LED_CONTROL BIT(5)
173 #define LEDCFG2_DPDT_SELECT BIT(7)
184 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1)
185 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9)
189 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0)
194 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW
196 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity
198 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */
200 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW
202 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW
204 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity
206 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */
207 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS
209 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW
211 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity
213 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */
219 #define MCU_FW_DL_ENABLE BIT(0)
220 #define MCU_FW_DL_READY BIT(1)
221 #define MCU_FW_DL_CSUM_REPORT BIT(2)
222 #define MCU_MAC_INIT_READY BIT(3)
223 #define MCU_BB_INIT_READY BIT(4)
224 #define MCU_RF_INIT_READY BIT(5)
225 #define MCU_WINT_INIT_READY BIT(6)
226 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */
227 #define MCU_CP_RESET BIT(23)
238 #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit
240 #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */
241 #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */
242 #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */
243 #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */
244 #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */
245 #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle
247 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
248 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */
249 #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR &
251 #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt
253 #define IMR0_ATIMEND BIT(12) /* CTWidnow End or
255 #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator
257 #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT
259 #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT
261 #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT
263 #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */
264 #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */
265 #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */
266 #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */
267 #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */
268 #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */
269 #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */
270 #define IMR0_ROK BIT(0) /* Receive DMA OK */
273 #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
274 #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
275 #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
276 #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
277 #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
278 #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
279 #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
280 #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */
281 #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */
282 #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */
283 #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */
284 #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */
285 #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */
286 #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */
287 #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension
289 #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status,
291 #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status,
293 #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */
294 #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */
309 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
310 #define HPON_FSM_BONDING_1T2R BIT(22)
312 #define SYS_CFG_XCLK_VLD BIT(0)
313 #define SYS_CFG_ACLK_VLD BIT(1)
314 #define SYS_CFG_UCLK_VLD BIT(2)
315 #define SYS_CFG_PCLK_VLD BIT(3)
316 #define SYS_CFG_PCIRSTB BIT(4)
317 #define SYS_CFG_V15_VLD BIT(5)
318 #define SYS_CFG_TRP_B15V_EN BIT(7)
319 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */
320 #define SYS_CFG_SIC_IDLE BIT(8)
321 #define SYS_CFG_BD_MAC2 BIT(9)
322 #define SYS_CFG_BD_MAC1 BIT(10)
323 #define SYS_CFG_IC_MACPHY_MODE BIT(11)
324 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
325 #define SYS_CFG_BT_FUNC BIT(16)
326 #define SYS_CFG_VENDOR_ID BIT(19)
327 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
329 #define SYS_CFG_VENDOR_ID_SMIC BIT(18)
330 #define SYS_CFG_VENDOR_ID_UMC BIT(19)
331 #define SYS_CFG_PAD_HWPD_IDN BIT(22)
332 #define SYS_CFG_TRP_VAUX_EN BIT(23)
333 #define SYS_CFG_TRP_BT_EN BIT(24)
334 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */
335 #define SYS_CFG_BD_PKG_SEL BIT(25)
336 #define SYS_CFG_BD_HCI_SEL BIT(26)
337 #define SYS_CFG_TYPE_ID BIT(27)
338 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID,
340 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode;
342 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */
345 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
346 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
347 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
348 #define GPIO_PKG_SEL_HCI BIT(6)
349 #define GPIO_FEN_GPS BIT(7)
350 #define GPIO_FEN_BT BIT(8)
351 #define GPIO_FEN_WL BIT(9)
352 #define GPIO_FEN_PCI BIT(10)
353 #define GPIO_FEN_USB BIT(11)
354 #define GPIO_BTRF_HWPDN_N BIT(12)
355 #define GPIO_WLRF_HWPDN_N BIT(13)
356 #define GPIO_PDN_BT_N BIT(14)
357 #define GPIO_PDN_GPS_N BIT(15)
358 #define GPIO_BT_CTL_HWPDN BIT(16)
359 #define GPIO_GPS_CTL_HWPDN BIT(17)
360 #define GPIO_PPHY_SUSB BIT(20)
361 #define GPIO_UPHY_SUSB BIT(21)
362 #define GPIO_PCI_SUSEN BIT(22)
363 #define GPIO_USB_SUSEN BIT(23)
364 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
370 #define CR_HCI_TXDMA_ENABLE BIT(0)
371 #define CR_HCI_RXDMA_ENABLE BIT(1)
372 #define CR_TXDMA_ENABLE BIT(2)
373 #define CR_RXDMA_ENABLE BIT(3)
374 #define CR_PROTOCOL_ENABLE BIT(4)
375 #define CR_SCHEDULE_ENABLE BIT(5)
376 #define CR_MAC_TX_ENABLE BIT(6)
377 #define CR_MAC_RX_ENABLE BIT(7)
378 #define CR_SW_BEACON_ENABLE BIT(8)
379 #define CR_SECURITY_ENABLE BIT(9)
380 #define CR_CALTIMER_ENABLE BIT(10)
405 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2)
480 #define RQPN_LOAD BIT(31)
484 #define BIT_BCN_VALID BIT(16)
489 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
496 #define AUTO_LLT_INIT_LLT BIT(16)
499 #define BIT_SW_BCN_SEL BIT(20)
507 #define RXDMA_USB_AGG_ENABLE BIT(31)
509 #define RXPKT_NUM_RXDMA_IDLE BIT(17)
510 #define RXPKT_NUM_RW_RELEASE_EN BIT(18)
516 #define RXDMA_PRO_DMA_MODE BIT(1) /* Set to 0x1. */
544 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7)
545 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12)
546 #define EN_BCNQ_DL BIT(22)
573 #define RSR_1M BIT(0)
574 #define RSR_2M BIT(1)
575 #define RSR_5_5M BIT(2)
576 #define RSR_11M BIT(3)
577 #define RSR_6M BIT(4)
578 #define RSR_9M BIT(5)
579 #define RSR_12M BIT(6)
580 #define RSR_18M BIT(7)
581 #define RSR_24M BIT(8)
582 #define RSR_36M BIT(9)
583 #define RSR_48M BIT(10)
584 #define RSR_54M BIT(11)
585 #define RSR_MCS0 BIT(12)
586 #define RSR_MCS1 BIT(13)
587 #define RSR_MCS2 BIT(14)
588 #define RSR_MCS3 BIT(15)
589 #define RSR_MCS4 BIT(16)
590 #define RSR_MCS5 BIT(17)
591 #define RSR_MCS6 BIT(18)
592 #define RSR_MCS7 BIT(19)
593 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */
594 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */
597 #define RSR_ACK_SHORT_PREAMBLE BIT(23)
604 #define BIT_BCN_PORT_SEL BIT(5)
629 #define HT_SINGLE_AMPDU_ENABLE BIT(7)
648 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1)
679 #define BEACON_ATIM BIT(0)
680 #define BEACON_CTRL_MBSSID BIT(1)
681 #define BEACON_CTRL_TX_BEACON_RPT BIT(2)
682 #define BEACON_FUNCTION_ENABLE BIT(3)
683 #define BEACON_DISABLE_TSF_UPDATE BIT(4)
687 #define DUAL_TSF_RESET_TSF0 BIT(0)
688 #define DUAL_TSF_RESET_TSF1 BIT(1)
689 #define DUAL_TSF_RESET_P2P BIT(4)
690 #define DUAL_TSF_TX_OK BIT(5)
715 #define ACM_HW_CTRL_BK BIT(0)
716 #define ACM_HW_CTRL_BE BIT(1)
717 #define ACM_HW_CTRL_VI BIT(2)
718 #define ACM_HW_CTRL_VO BIT(3)
735 #define APSD_CTRL_OFF BIT(6)
736 #define APSD_CTRL_OFF_STATUS BIT(7)
738 #define BW_OPMODE_20MHZ BIT(2)
739 #define BW_OPMODE_5G BIT(1)
740 #define BW_OPMODE_11J BIT(0)
746 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */
747 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */
748 #define RCR_ACCEPT_MCAST BIT(2)
749 #define RCR_ACCEPT_BCAST BIT(3)
750 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match
752 #define RCR_ACCEPT_PM BIT(5) /* Accept power management
754 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */
755 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet
757 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */
758 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */
759 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use
761 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use
763 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use
765 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
766 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet
768 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet
770 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/
771 #define RCR_MFBEN BIT(22)
772 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection
775 LSIGEN bit is set. */
776 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */
777 #define RCR_FORCE_ACK BIT(26)
778 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */
779 #define RCR_APPEND_PHYSTAT BIT(28)
780 #define RCR_APPEND_ICV BIT(29)
781 #define RCR_APPEND_MIC BIT(30)
782 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */
817 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
819 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7)
820 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8)
824 #define CAM_CMD_POLLING BIT(31)
825 #define CAM_CMD_WRITE BIT(16)
828 #define CAM_WRITE_VALID BIT(15)
832 #define SEC_CFG_TX_USE_DEFKEY BIT(0)
833 #define SEC_CFG_RX_USE_DEFKEY BIT(1)
834 #define SEC_CFG_TX_SEC_ENABLE BIT(2)
835 #define SEC_CFG_RX_SEC_ENABLE BIT(3)
836 #define SEC_CFG_SKBYA2 BIT(4)
837 #define SEC_CFG_NO_SKMC BIT(5)
838 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6)
839 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7)
850 * RX Filters: each bit corresponds to the numerical value of the subtype.
852 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit
856 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception.
878 #define BT_CONTROL_BT_GRANT BIT(12)
884 #define FPGA_RF_MODE BIT(0)
885 #define FPGA_RF_MODE_JAPAN BIT(1)
886 #define FPGA_RF_MODE_CCK BIT(24)
887 #define FPGA_RF_MODE_OFDM BIT(25)
890 #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0)
891 #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1)
892 #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2)
893 #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3)
899 #define FPGA0_PS_LOWER_CHANNEL BIT(26)
900 #define FPGA0_PS_UPPER_CHANNEL BIT(27)
903 #define FPGA0_HSSI_PARM1_PI BIT(8)
911 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9)
912 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31)
933 #define FPGA0_INT_OE_ANTENNA_A BIT(8)
934 #define FPGA0_INT_OE_ANTENNA_B BIT(9)
942 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */
943 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */
945 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */
946 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */
947 #define FPGA0_RF_3WIRE_DATA BIT(0)
948 #define FPGA0_RF_3WIRE_CLOC BIT(1)
949 #define FPGA0_RF_3WIRE_LOAD BIT(2)
950 #define FPGA0_RF_3WIRE_RW BIT(3)
952 #define FPGA0_RF_RFENV BIT(4)
953 #define FPGA0_RF_TRSW BIT(5) /* Useless now */
954 #define FPGA0_RF_TRSWB BIT(6)
955 #define FPGA0_RF_ANTSW BIT(8)
956 #define FPGA0_RF_ANTSWB BIT(9)
957 #define FPGA0_RF_PAPE BIT(10)
958 #define FPGA0_RF_PAPE5G BIT(11)
962 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */
963 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */
965 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */
966 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */
967 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1)
968 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17)
969 #define FPGA0_RF_PARM_CLK_GATE BIT(31)
973 #define FPGA0_ANALOG2_20MHZ BIT(10)
1015 #define CCK0_SIDEBAND BIT(4)
1021 #define CCK0_AFE_RX_ANT_B BIT(26)
1022 #define CCK0_AFE_RX_ANT_C BIT(27)
1023 #define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27))
1025 #define CCK0_AFE_RX_ANT_OPTION_B BIT(24)
1026 #define CCK0_AFE_RX_ANT_OPTION_C BIT(25)
1027 #define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25))
1028 #define CCK0_AFE_TX_ANT_A BIT(31)
1029 #define CCK0_AFE_TX_ANT_B BIT(30)
1036 #define LNA_SWITCH_DISABLE_CSCG BIT(22)
1037 #define LNA_SWITCH_OUTPUT_CG BIT(31)
1050 #define AGC_RPT_CCK BIT(7)
1058 #define OFDM_RF_PATH_RX_A BIT(0)
1059 #define OFDM_RF_PATH_RX_B BIT(1)
1060 #define OFDM_RF_PATH_RX_C BIT(2)
1061 #define OFDM_RF_PATH_RX_D BIT(3)
1063 #define OFDM_RF_PATH_TX_A BIT(4)
1064 #define OFDM_RF_PATH_TX_B BIT(5)
1065 #define OFDM_RF_PATH_TX_C BIT(6)
1066 #define OFDM_RF_PATH_TX_D BIT(7)
1081 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1)
1116 #define OFDM_LSTF_PRIME_CH_LOW BIT(10)
1117 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11)
1120 #define OFDM_LSTF_CONTINUE_TX BIT(28)
1121 #define OFDM_LSTF_SINGLE_CARRIER BIT(29)
1122 #define OFDM_LSTF_SINGLE_TONE BIT(30)
1127 #define CFO_TRACKING_ATC_STATUS BIT(11)
1209 #define USB_HIMR_TIMEOUT2 BIT(31)
1210 #define USB_HIMR_TIMEOUT1 BIT(30)
1211 #define USB_HIMR_PSTIMEOUT BIT(29)
1212 #define USB_HIMR_GTINT4 BIT(28)
1213 #define USB_HIMR_GTINT3 BIT(27)
1214 #define USB_HIMR_TXBCNERR BIT(26)
1215 #define USB_HIMR_TXBCNOK BIT(25)
1216 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24)
1217 #define USB_HIMR_BCNDMAINT3 BIT(23)
1218 #define USB_HIMR_BCNDMAINT2 BIT(22)
1219 #define USB_HIMR_BCNDMAINT1 BIT(21)
1220 #define USB_HIMR_BCNDMAINT0 BIT(20)
1221 #define USB_HIMR_BCNDOK3 BIT(19)
1222 #define USB_HIMR_BCNDOK2 BIT(18)
1223 #define USB_HIMR_BCNDOK1 BIT(17)
1224 #define USB_HIMR_BCNDOK0 BIT(16)
1225 #define USB_HIMR_HSISR_IND BIT(15)
1226 #define USB_HIMR_BCNDMAINT_E BIT(14)
1227 /* RSVD BIT(13) */
1228 #define USB_HIMR_CTW_END BIT(12)
1229 /* RSVD BIT(11) */
1230 #define USB_HIMR_C2HCMD BIT(10)
1231 #define USB_HIMR_CPWM2 BIT(9)
1232 #define USB_HIMR_CPWM BIT(8)
1233 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK
1235 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
1237 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
1238 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
1239 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
1240 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
1241 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor
1243 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
1248 #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */
1249 #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to
1334 #define MODE_AG_CHANNEL_20MHZ BIT(10)
1335 #define MODE_AG_BW_MASK (BIT(10) | BIT(11))
1336 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11))
1337 #define MODE_AG_BW_40MHZ_8723B BIT(10)