Lines Matching refs:priv
291 static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv) in rtl8723bu_identify_chip() argument
293 struct device *dev = &priv->udev->dev; in rtl8723bu_identify_chip()
297 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8723bu_identify_chip()
298 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8723bu_identify_chip()
305 strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); in rtl8723bu_identify_chip()
306 priv->rtl_chip = RTL8723B; in rtl8723bu_identify_chip()
307 priv->rf_paths = 1; in rtl8723bu_identify_chip()
308 priv->rx_paths = 1; in rtl8723bu_identify_chip()
309 priv->tx_paths = 1; in rtl8723bu_identify_chip()
311 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8723bu_identify_chip()
313 priv->has_wifi = 1; in rtl8723bu_identify_chip()
315 priv->has_bluetooth = 1; in rtl8723bu_identify_chip()
317 priv->has_gps = 1; in rtl8723bu_identify_chip()
318 priv->is_multi_func = 1; in rtl8723bu_identify_chip()
321 rtl8xxxu_identify_vendor_2bits(priv, vendor); in rtl8723bu_identify_chip()
323 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8723bu_identify_chip()
324 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8723bu_identify_chip()
326 rtl8xxxu_config_endpoints_sie(priv); in rtl8723bu_identify_chip()
331 if (!priv->ep_tx_count) in rtl8723bu_identify_chip()
332 ret = rtl8xxxu_config_endpoints_no_sie(priv); in rtl8723bu_identify_chip()
338 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) in rtl8723bu_write_btreg() argument
348 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); in rtl8723bu_write_btreg()
356 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); in rtl8723bu_write_btreg()
359 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) in rtl8723bu_reset_8051() argument
364 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); in rtl8723bu_reset_8051()
366 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); in rtl8723bu_reset_8051()
368 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); in rtl8723bu_reset_8051()
370 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); in rtl8723bu_reset_8051()
372 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_reset_8051()
374 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); in rtl8723bu_reset_8051()
376 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); in rtl8723bu_reset_8051()
378 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); in rtl8723bu_reset_8051()
380 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); in rtl8723bu_reset_8051()
382 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); in rtl8723bu_reset_8051()
385 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); in rtl8723bu_reset_8051()
389 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8723b_set_tx_power() argument
398 cck = priv->cck_tx_power_index_B[group]; in rtl8723b_set_tx_power()
399 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723b_set_tx_power()
402 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
404 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723b_set_tx_power()
407 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
409 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8723b_set_tx_power()
410 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8723b_set_tx_power()
413 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8723b_set_tx_power()
414 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8723b_set_tx_power()
416 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8723b_set_tx_power()
418 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8723b_set_tx_power()
420 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8723b_set_tx_power()
423 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8723b_set_tx_power()
424 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8723b_set_tx_power()
427 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8723bu_parse_efuse() argument
429 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; in rtl8723bu_parse_efuse()
435 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8723bu_parse_efuse()
437 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8723bu_parse_efuse()
439 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8723bu_parse_efuse()
442 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8723bu_parse_efuse()
445 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8723bu_parse_efuse()
449 priv->ofdm_tx_power_diff[0].a = in rtl8723bu_parse_efuse()
451 priv->ofdm_tx_power_diff[0].b = in rtl8723bu_parse_efuse()
454 priv->ht20_tx_power_diff[0].a = in rtl8723bu_parse_efuse()
456 priv->ht20_tx_power_diff[0].b = in rtl8723bu_parse_efuse()
459 priv->ht40_tx_power_diff[0].a = 0; in rtl8723bu_parse_efuse()
460 priv->ht40_tx_power_diff[0].b = 0; in rtl8723bu_parse_efuse()
463 priv->ofdm_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
465 priv->ofdm_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
468 priv->ht20_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
470 priv->ht20_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
473 priv->ht40_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
475 priv->ht40_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
479 priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; in rtl8723bu_parse_efuse()
484 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8723bu_load_firmware() argument
489 if (priv->enable_bluetooth) in rtl8723bu_load_firmware()
494 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8723bu_load_firmware()
498 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8723bu_init_phy_bb() argument
503 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_init_phy_bb()
505 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_init_phy_bb()
507 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_init_phy_bb()
511 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8723bu_init_phy_bb()
514 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); in rtl8723bu_init_phy_bb()
515 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723bu_init_phy_bb()
516 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); in rtl8723bu_init_phy_bb()
518 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); in rtl8723bu_init_phy_bb()
521 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8723bu_init_phy_rf() argument
525 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); in rtl8723bu_init_phy_rf()
529 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); in rtl8723bu_init_phy_rf()
530 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); in rtl8723bu_init_phy_rf()
532 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); in rtl8723bu_init_phy_rf()
537 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) in rtl8723bu_phy_init_antenna_selection() argument
541 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); in rtl8723bu_phy_init_antenna_selection()
543 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
545 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
547 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
549 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
551 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
553 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
555 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
557 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
559 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
561 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723bu_phy_init_antenna_selection()
563 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723bu_phy_init_antenna_selection()
565 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); in rtl8723bu_phy_init_antenna_selection()
568 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); in rtl8723bu_phy_init_antenna_selection()
570 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723bu_phy_init_antenna_selection()
572 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723bu_phy_init_antenna_selection()
575 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8723bu_iqk_path_a() argument
580 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8723bu_iqk_path_a()
585 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
587 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
592 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_iqk_path_a()
594 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_iqk_path_a()
595 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); in rtl8723bu_iqk_path_a()
596 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); in rtl8723bu_iqk_path_a()
597 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); in rtl8723bu_iqk_path_a()
602 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_iqk_path_a()
603 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_iqk_path_a()
606 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_iqk_path_a()
607 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_iqk_path_a()
608 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
609 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
611 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); in rtl8723bu_iqk_path_a()
612 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_iqk_path_a()
613 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_iqk_path_a()
614 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_iqk_path_a()
617 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8723bu_iqk_path_a()
622 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
625 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
631 if (priv->rf_paths > 1) in rtl8723bu_iqk_path_a()
632 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_iqk_path_a()
634 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_iqk_path_a()
640 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_iqk_path_a()
643 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_iqk_path_a()
644 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_iqk_path_a()
649 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_iqk_path_a()
652 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_iqk_path_a()
658 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
660 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
663 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_iqk_path_a()
664 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8723bu_iqk_path_a()
665 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8723bu_iqk_path_a()
685 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8723bu_rx_iqk_path_a() argument
690 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8723bu_rx_iqk_path_a()
695 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
697 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
702 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
704 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
705 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_rx_iqk_path_a()
706 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_rx_iqk_path_a()
707 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); in rtl8723bu_rx_iqk_path_a()
712 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_rx_iqk_path_a()
713 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
716 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
717 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
718 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
719 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
721 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); in rtl8723bu_rx_iqk_path_a()
722 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_rx_iqk_path_a()
723 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
724 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
727 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8723bu_rx_iqk_path_a()
732 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
735 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
741 if (priv->rf_paths > 1) in rtl8723bu_rx_iqk_path_a()
742 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
744 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
750 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
753 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
754 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
759 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
762 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
768 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
770 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
773 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
774 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8723bu_rx_iqk_path_a()
775 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8723bu_rx_iqk_path_a()
793 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8723bu_rx_iqk_path_a()
798 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
800 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
801 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
803 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
804 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_rx_iqk_path_a()
805 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_rx_iqk_path_a()
806 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); in rtl8723bu_rx_iqk_path_a()
811 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0xf80); in rtl8723bu_rx_iqk_path_a()
812 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); in rtl8723bu_rx_iqk_path_a()
817 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
820 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
821 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
822 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
823 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
825 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); in rtl8723bu_rx_iqk_path_a()
826 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); in rtl8723bu_rx_iqk_path_a()
827 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
828 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
831 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); in rtl8723bu_rx_iqk_path_a()
836 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
839 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
841 if (priv->rf_paths > 1) in rtl8723bu_rx_iqk_path_a()
842 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
844 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
849 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
852 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
853 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
858 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
861 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
867 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
869 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
872 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
873 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
875 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x780); in rtl8723bu_rx_iqk_path_a()
894 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8723bu_phy_iqcalibrate() argument
897 struct device *dev = &priv->udev->dev; in rtl8723bu_phy_iqcalibrate()
921 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8723bu_phy_iqcalibrate()
922 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; in rtl8723bu_phy_iqcalibrate()
931 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8723bu_phy_iqcalibrate()
933 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
934 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8723bu_phy_iqcalibrate()
935 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iqcalibrate()
938 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8723bu_phy_iqcalibrate()
941 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
943 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8723bu_phy_iqcalibrate()
945 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8723bu_phy_iqcalibrate()
947 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8723bu_phy_iqcalibrate()
948 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8723bu_phy_iqcalibrate()
949 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8723bu_phy_iqcalibrate()
955 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
957 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
959 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iqcalibrate()
961 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iqcalibrate()
963 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_phy_iqcalibrate()
964 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_phy_iqcalibrate()
965 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); in rtl8723bu_phy_iqcalibrate()
967 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iqcalibrate()
969 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iqcalibrate()
971 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); in rtl8723bu_phy_iqcalibrate()
974 path_a_ok = rtl8723bu_iqk_path_a(priv); in rtl8723bu_phy_iqcalibrate()
976 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
978 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
980 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
983 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
995 path_a_ok = rtl8723bu_rx_iqk_path_a(priv); in rtl8723bu_phy_iqcalibrate()
997 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1000 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1011 if (priv->tx_paths > 1) { in rtl8723bu_phy_iqcalibrate()
1019 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1021 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1022 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); in rtl8723bu_phy_iqcalibrate()
1024 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1027 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1030 rtl8xxxu_path_adda_on(priv, adda_regs, false); in rtl8723bu_phy_iqcalibrate()
1033 path_b_ok = rtl8xxxu_iqk_path_b(priv); in rtl8723bu_phy_iqcalibrate()
1035 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8723bu_phy_iqcalibrate()
1037 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8723bu_phy_iqcalibrate()
1047 path_b_ok = rtl8723bu_rx_iqk_path_b(priv); in rtl8723bu_phy_iqcalibrate()
1049 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1052 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1065 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1067 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1071 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8723bu_phy_iqcalibrate()
1075 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
1078 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8723bu_phy_iqcalibrate()
1079 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iqcalibrate()
1082 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1084 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1085 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8723bu_phy_iqcalibrate()
1087 if (priv->tx_paths > 1) { in rtl8723bu_phy_iqcalibrate()
1088 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1090 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1092 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1097 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1098 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1102 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8723bu_phy_iq_calibrate() argument
1104 struct device *dev = &priv->udev->dev; in rtl8723bu_phy_iq_calibrate()
1114 rtl8xxxu_gen2_prepare_calibrate(priv, 1); in rtl8723bu_phy_iq_calibrate()
1122 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); in rtl8723bu_phy_iq_calibrate()
1125 rtl8723bu_phy_iqcalibrate(priv, result, i); in rtl8723bu_phy_iq_calibrate()
1128 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1137 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1144 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1173 priv->rege94 = reg_e94; in rtl8723bu_phy_iq_calibrate()
1175 priv->rege9c = reg_e9c; in rtl8723bu_phy_iq_calibrate()
1179 priv->regeb4 = reg_eb4; in rtl8723bu_phy_iq_calibrate()
1181 priv->regebc = reg_ebc; in rtl8723bu_phy_iq_calibrate()
1192 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8723bu_phy_iq_calibrate()
1193 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8723bu_phy_iq_calibrate()
1197 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8723bu_phy_iq_calibrate()
1200 if (priv->tx_paths > 1 && reg_eb4) in rtl8723bu_phy_iq_calibrate()
1201 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8723bu_phy_iq_calibrate()
1204 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8723bu_phy_iq_calibrate()
1205 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iq_calibrate()
1207 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); in rtl8723bu_phy_iq_calibrate()
1209 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iq_calibrate()
1211 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iq_calibrate()
1212 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); in rtl8723bu_phy_iq_calibrate()
1213 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_phy_iq_calibrate()
1214 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); in rtl8723bu_phy_iq_calibrate()
1215 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iq_calibrate()
1217 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iq_calibrate()
1218 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); in rtl8723bu_phy_iq_calibrate()
1220 if (priv->rf_paths > 1) in rtl8723bu_phy_iq_calibrate()
1223 rtl8xxxu_gen2_prepare_calibrate(priv, 0); in rtl8723bu_phy_iq_calibrate()
1226 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8723bu_active_to_emu() argument
1234 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); in rtl8723bu_active_to_emu()
1237 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); in rtl8723bu_active_to_emu()
1239 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); in rtl8723bu_active_to_emu()
1242 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723bu_active_to_emu()
1244 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723bu_active_to_emu()
1247 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_active_to_emu()
1249 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8723bu_active_to_emu()
1252 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_active_to_emu()
1259 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8723bu_active_to_emu()
1266 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); in rtl8723bu_active_to_emu()
1268 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); in rtl8723bu_active_to_emu()
1271 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); in rtl8723bu_active_to_emu()
1273 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); in rtl8723bu_active_to_emu()
1276 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); in rtl8723bu_active_to_emu()
1278 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); in rtl8723bu_active_to_emu()
1284 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8723b_emu_to_active() argument
1291 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); in rtl8723b_emu_to_active()
1293 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); in rtl8723b_emu_to_active()
1296 val8 = rtl8xxxu_read8(priv, 0x0067); in rtl8723b_emu_to_active()
1298 rtl8xxxu_write8(priv, 0x0067, val8); in rtl8723b_emu_to_active()
1303 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); in rtl8723b_emu_to_active()
1305 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); in rtl8723b_emu_to_active()
1308 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1310 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1314 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1329 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1331 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1334 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1336 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1339 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1341 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1344 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1346 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1349 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1363 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); in rtl8723b_emu_to_active()
1365 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); in rtl8723b_emu_to_active()
1368 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); in rtl8723b_emu_to_active()
1370 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); in rtl8723b_emu_to_active()
1373 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); in rtl8723b_emu_to_active()
1375 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); in rtl8723b_emu_to_active()
1378 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); in rtl8723b_emu_to_active()
1380 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); in rtl8723b_emu_to_active()
1383 val8 = rtl8xxxu_read8(priv, REG_HSIMR); in rtl8723b_emu_to_active()
1385 rtl8xxxu_write8(priv, REG_HSIMR, val8); in rtl8723b_emu_to_active()
1388 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); in rtl8723b_emu_to_active()
1390 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); in rtl8723b_emu_to_active()
1392 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); in rtl8723b_emu_to_active()
1394 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); in rtl8723b_emu_to_active()
1397 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); in rtl8723b_emu_to_active()
1399 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); in rtl8723b_emu_to_active()
1405 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) in rtl8723bu_power_on() argument
1412 rtl8xxxu_disabled_to_emu(priv); in rtl8723bu_power_on()
1414 ret = rtl8723b_emu_to_active(priv); in rtl8723bu_power_on()
1422 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8723bu_power_on()
1428 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8723bu_power_on()
1434 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); in rtl8723bu_power_on()
1436 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_power_on()
1438 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_power_on()
1440 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); in rtl8723bu_power_on()
1441 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); in rtl8723bu_power_on()
1442 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_power_on()
1444 rtl8xxxu_write8(priv, 0xfe08, 0x01); in rtl8723bu_power_on()
1446 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); in rtl8723bu_power_on()
1448 rtl8xxxu_write16(priv, REG_PWR_DATA, val16); in rtl8723bu_power_on()
1450 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_power_on()
1452 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_power_on()
1454 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723bu_power_on()
1456 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723bu_power_on()
1461 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) in rtl8723bu_power_off() argument
1466 rtl8xxxu_flush_fifo(priv); in rtl8723bu_power_off()
1471 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8723bu_power_off()
1473 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8723bu_power_off()
1475 rtl8xxxu_write8(priv, REG_CR, 0x0000); in rtl8723bu_power_off()
1477 rtl8xxxu_active_to_lps(priv); in rtl8723bu_power_off()
1480 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8723bu_power_off()
1481 rtl8xxxu_firmware_self_reset(priv); in rtl8723bu_power_off()
1484 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_power_off()
1486 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_power_off()
1489 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8723bu_power_off()
1491 rtl8723bu_active_to_emu(priv); in rtl8723bu_power_off()
1493 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_power_off()
1495 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8723bu_power_off()
1498 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); in rtl8723bu_power_off()
1500 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); in rtl8723bu_power_off()
1503 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) in rtl8723b_enable_rf() argument
1509 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8723b_enable_rf()
1511 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8723b_enable_rf()
1517 rtl8xxxu_write8(priv, 0x0790, 0x05); in rtl8723b_enable_rf()
1523 rtl8xxxu_write8(priv, 0x0778, 0x01); in rtl8723b_enable_rf()
1525 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); in rtl8723b_enable_rf()
1527 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); in rtl8723b_enable_rf()
1529 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); in rtl8723b_enable_rf()
1531 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ in rtl8723b_enable_rf()
1539 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); in rtl8723b_enable_rf()
1544 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); in rtl8723b_enable_rf()
1549 val8 = rtl8xxxu_read8(priv, 0x0067); in rtl8723b_enable_rf()
1551 rtl8xxxu_write8(priv, 0x0067, val8); in rtl8723b_enable_rf()
1553 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723b_enable_rf()
1555 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723b_enable_rf()
1560 rtl8xxxu_write8(priv, 0x0974, 0xff); in rtl8723b_enable_rf()
1562 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723b_enable_rf()
1564 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723b_enable_rf()
1566 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); in rtl8723b_enable_rf()
1568 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723b_enable_rf()
1571 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723b_enable_rf()
1576 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723b_enable_rf()
1578 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723b_enable_rf()
1584 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); in rtl8723b_enable_rf()
1594 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); in rtl8723b_enable_rf()
1599 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); in rtl8723b_enable_rf()
1601 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); in rtl8723b_enable_rf()
1602 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); in rtl8723b_enable_rf()
1603 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); in rtl8723b_enable_rf()
1604 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); in rtl8723b_enable_rf()
1609 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); in rtl8723b_enable_rf()
1614 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); in rtl8723b_enable_rf()
1617 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) in rtl8723bu_init_aggregation() argument
1625 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); in rtl8723bu_init_aggregation()
1628 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); in rtl8723bu_init_aggregation()
1632 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); in rtl8723bu_init_aggregation()
1633 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); in rtl8723bu_init_aggregation()
1636 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) in rtl8723bu_init_statistics() argument
1641 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); in rtl8723bu_init_statistics()
1642 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); in rtl8723bu_init_statistics()
1643 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); in rtl8723bu_init_statistics()
1644 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); in rtl8723bu_init_statistics()
1646 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_init_statistics()
1648 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_init_statistics()
1650 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8723bu_init_statistics()
1652 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8723bu_init_statistics()
1654 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8723bu_init_statistics()
1656 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8723bu_init_statistics()
1659 static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) in rtl8723b_cck_rssi() argument
1691 struct rtl8xxxu_priv *priv = container_of(led_cdev, in rtl8723bu_led_brightness_set() local
1694 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); in rtl8723bu_led_brightness_set()
1705 rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); in rtl8723bu_led_brightness_set()