Lines Matching refs:priv
392 static int rtl8192fu_identify_chip(struct rtl8xxxu_priv *priv) in rtl8192fu_identify_chip() argument
394 struct device *dev = &priv->udev->dev; in rtl8192fu_identify_chip()
397 strscpy(priv->chip_name, "8192FU", sizeof(priv->chip_name)); in rtl8192fu_identify_chip()
398 priv->rtl_chip = RTL8192F; in rtl8192fu_identify_chip()
399 priv->rf_paths = 2; in rtl8192fu_identify_chip()
400 priv->rx_paths = 2; in rtl8192fu_identify_chip()
401 priv->tx_paths = 2; in rtl8192fu_identify_chip()
403 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192fu_identify_chip()
404 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8192fu_identify_chip()
410 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8192fu_identify_chip()
411 priv->has_wifi = u32_get_bits(val32, MULTI_WIFI_FUNC_EN); in rtl8192fu_identify_chip()
412 priv->has_bluetooth = u32_get_bits(val32, MULTI_BT_FUNC_EN); in rtl8192fu_identify_chip()
413 priv->has_gps = u32_get_bits(val32, MULTI_GPS_FUNC_EN); in rtl8192fu_identify_chip()
414 priv->is_multi_func = 1; in rtl8192fu_identify_chip()
417 rtl8xxxu_identify_vendor_1bit(priv, vendor); in rtl8192fu_identify_chip()
419 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192fu_identify_chip()
420 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192fu_identify_chip()
422 return rtl8xxxu_config_endpoints_no_sie(priv); in rtl8192fu_identify_chip()
426 rtl8192f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8192f_set_tx_power() argument
434 cck = priv->cck_tx_power_index_A[cck_group]; in rtl8192f_set_tx_power()
436 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_CCK1_MCS32, 0x00007f00, cck); in rtl8192f_set_tx_power()
439 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, in rtl8192f_set_tx_power()
442 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192f_set_tx_power()
443 ofdmbase += priv->ofdm_tx_power_diff[RF_A].a; in rtl8192f_set_tx_power()
446 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE18_06, 0x7f7f7f7f, ofdm); in rtl8192f_set_tx_power()
447 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE54_24, 0x7f7f7f7f, ofdm); in rtl8192f_set_tx_power()
449 mcsbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192f_set_tx_power()
451 mcsbase += priv->ht40_tx_power_diff[RF_A].a; in rtl8192f_set_tx_power()
453 mcsbase += priv->ht20_tx_power_diff[RF_A].a; in rtl8192f_set_tx_power()
456 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS03_MCS00, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
457 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS07_MCS04, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
458 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS11_MCS08, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
459 rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS15_MCS12, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
461 if (priv->tx_paths == 1) in rtl8192f_set_tx_power()
464 cck = priv->cck_tx_power_index_B[cck_group]; in rtl8192f_set_tx_power()
467 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK1_55_MCS32, in rtl8192f_set_tx_power()
470 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, in rtl8192f_set_tx_power()
473 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192f_set_tx_power()
474 ofdmbase += priv->ofdm_tx_power_diff[RF_B].b; in rtl8192f_set_tx_power()
477 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE18_06, 0x7f7f7f7f, ofdm); in rtl8192f_set_tx_power()
478 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE54_24, 0x7f7f7f7f, ofdm); in rtl8192f_set_tx_power()
480 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192f_set_tx_power()
482 mcsbase += priv->ht40_tx_power_diff[RF_B].b; in rtl8192f_set_tx_power()
484 mcsbase += priv->ht20_tx_power_diff[RF_B].b; in rtl8192f_set_tx_power()
487 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS03_MCS00, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
488 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS07_MCS04, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
489 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS11_MCS08, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
490 rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS15_MCS12, 0x7f7f7f7f, mcs); in rtl8192f_set_tx_power()
493 static void rtl8192f_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel) in rtl8192f_revise_cck_tx_psf() argument
497 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xf8fe0001); in rtl8192f_revise_cck_tx_psf()
499 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); in rtl8192f_revise_cck_tx_psf()
500 rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); in rtl8192f_revise_cck_tx_psf()
501 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); in rtl8192f_revise_cck_tx_psf()
504 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); in rtl8192f_revise_cck_tx_psf()
506 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C); in rtl8192f_revise_cck_tx_psf()
507 rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x0000); in rtl8192f_revise_cck_tx_psf()
508 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667); in rtl8192f_revise_cck_tx_psf()
511 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); in rtl8192f_revise_cck_tx_psf()
512 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); in rtl8192f_revise_cck_tx_psf()
513 rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); in rtl8192f_revise_cck_tx_psf()
514 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); in rtl8192f_revise_cck_tx_psf()
518 static void rtl8192fu_config_kfree(struct rtl8xxxu_priv *priv, u8 channel) in rtl8192fu_config_kfree() argument
533 rtl8xxxu_read_efuse8(priv, 0x1ee, &bb_gain[1]); in rtl8192fu_config_kfree()
534 rtl8xxxu_read_efuse8(priv, 0x1ec, &bb_gain[0]); in rtl8192fu_config_kfree()
535 rtl8xxxu_read_efuse8(priv, 0x1ea, &bb_gain[2]); in rtl8192fu_config_kfree()
546 for (rfpath = RF_A; rfpath < priv->rf_paths; rfpath++) { in rtl8192fu_config_kfree()
548 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_UNKNOWN_55, in rtl8192fu_config_kfree()
552 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CTRL, in rtl8192fu_config_kfree()
556 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, in rtl8192fu_config_kfree()
560 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 1); in rtl8192fu_config_kfree()
565 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, in rtl8192fu_config_kfree()
567 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, in rtl8192fu_config_kfree()
570 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, in rtl8192fu_config_kfree()
572 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, in rtl8192fu_config_kfree()
576 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, in rtl8192fu_config_kfree()
580 rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 0); in rtl8192fu_config_kfree()
586 struct rtl8xxxu_priv *priv = hw->priv; in rtl8192fu_config_channel() local
604 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8192fu_config_channel()
606 rtl8192f_revise_cck_tx_psf(priv, channel); in rtl8192fu_config_channel()
611 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
612 if (priv->rf_paths > 1) in rtl8192fu_config_channel()
613 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
615 rtl8192fu_config_kfree(priv, channel); in rtl8192fu_config_channel()
617 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); in rtl8192fu_config_channel()
620 rtl8xxxu_write32_clear(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, GENMASK(31, 30)); in rtl8192fu_config_channel()
622 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE, ht40); in rtl8192fu_config_channel()
623 rtl8xxxu_write32_mask(priv, REG_FPGA1_RF_MODE, FPGA_RF_MODE, ht40); in rtl8192fu_config_channel()
626 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), 4); in rtl8192fu_config_channel()
629 rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, BIT(13) | BIT(12), 2); in rtl8192fu_config_channel()
632 rtl8xxxu_write32_mask(priv, REG_ANTDIV_PARA1, BIT(27) | BIT(26), 2); in rtl8192fu_config_channel()
636 rtl8xxxu_write32_mask(priv, REG_CCK0_SYSTEM, in rtl8192fu_config_channel()
640 rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK); in rtl8192fu_config_channel()
643 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8192fu_config_channel()
649 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
650 if (priv->rf_paths > 1) in rtl8192fu_config_channel()
651 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); in rtl8192fu_config_channel()
654 rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, BIT(21) | BIT(20), 2); in rtl8192fu_config_channel()
656 rtl8xxxu_write32_mask(priv, REG_DOWNSAM_FACTOR, BIT(29) | BIT(28), 2); in rtl8192fu_config_channel()
662 rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, 0x1ff, val32); in rtl8192fu_config_channel()
665 static void rtl8192fu_init_aggregation(struct rtl8xxxu_priv *priv) in rtl8192fu_init_aggregation() argument
671 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); in rtl8192fu_init_aggregation()
674 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); in rtl8192fu_init_aggregation()
678 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); in rtl8192fu_init_aggregation()
679 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); in rtl8192fu_init_aggregation()
682 static int rtl8192fu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8192fu_parse_efuse() argument
684 struct rtl8192fu_efuse *efuse = &priv->efuse_wifi.efuse8192fu; in rtl8192fu_parse_efuse()
690 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8192fu_parse_efuse()
692 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8192fu_parse_efuse()
694 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8192fu_parse_efuse()
697 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8192fu_parse_efuse()
700 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8192fu_parse_efuse()
704 priv->ht20_tx_power_diff[0].a = in rtl8192fu_parse_efuse()
706 priv->ht20_tx_power_diff[0].b = in rtl8192fu_parse_efuse()
709 priv->ht40_tx_power_diff[0].a = 0; in rtl8192fu_parse_efuse()
710 priv->ht40_tx_power_diff[0].b = 0; in rtl8192fu_parse_efuse()
713 priv->ofdm_tx_power_diff[i].a = in rtl8192fu_parse_efuse()
715 priv->ofdm_tx_power_diff[i].b = in rtl8192fu_parse_efuse()
718 priv->ht20_tx_power_diff[i].a = in rtl8192fu_parse_efuse()
720 priv->ht20_tx_power_diff[i].b = in rtl8192fu_parse_efuse()
723 priv->ht40_tx_power_diff[i].a = in rtl8192fu_parse_efuse()
725 priv->ht40_tx_power_diff[i].b = in rtl8192fu_parse_efuse()
729 priv->default_crystal_cap = efuse->xtal_k & 0x3f; in rtl8192fu_parse_efuse()
731 priv->rfe_type = efuse->rfe_option & 0x1f; in rtl8192fu_parse_efuse()
733 if (priv->rfe_type != 5 && priv->rfe_type != 1) in rtl8192fu_parse_efuse()
734 dev_warn(&priv->udev->dev, in rtl8192fu_parse_efuse()
736 __func__, priv->rfe_type); in rtl8192fu_parse_efuse()
741 static int rtl8192fu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8192fu_load_firmware() argument
743 return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8192fufw.bin"); in rtl8192fu_load_firmware()
746 static void rtl8192fu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8192fu_init_phy_bb() argument
749 rtl8xxxu_write16_set(priv, REG_SYS_FUNC, in rtl8192fu_init_phy_bb()
752 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); in rtl8192fu_init_phy_bb()
755 rtl8xxxu_write8(priv, REG_LDOHCI12_CTRL, 0xf); in rtl8192fu_init_phy_bb()
756 rtl8xxxu_write8(priv, REG_SYS_SWR_CTRL2 + 1, 0xe9); in rtl8192fu_init_phy_bb()
758 rtl8xxxu_init_phy_regs(priv, rtl8192fu_phy_init_table); in rtl8192fu_init_phy_bb()
760 rtl8xxxu_init_phy_regs(priv, rtl8192f_agc_table); in rtl8192fu_init_phy_bb()
763 static int rtl8192fu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8192fu_init_phy_rf() argument
767 ret = rtl8xxxu_init_phy_rf(priv, rtl8192fu_radioa_init_table, RF_A); in rtl8192fu_init_phy_rf()
771 return rtl8xxxu_init_phy_rf(priv, rtl8192fu_radiob_init_table, RF_B); in rtl8192fu_init_phy_rf()
774 static void rtl8192f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) in rtl8192f_phy_lc_calibrate() argument
781 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8192f_phy_lc_calibrate()
785 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8192f_phy_lc_calibrate()
787 rtl8188f_phy_lc_calibrate(priv); in rtl8192f_phy_lc_calibrate()
790 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8192f_phy_lc_calibrate()
792 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8192f_phy_lc_calibrate()
795 rtl8xxxu_write32_clear(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); in rtl8192f_phy_lc_calibrate()
796 rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); in rtl8192f_phy_lc_calibrate()
799 static int rtl8192fu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192fu_iqk_path_a() argument
803 u8 rfe = priv->rfe_type; in rtl8192fu_iqk_path_a()
808 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_a()
810 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); in rtl8192fu_iqk_path_a()
811 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); in rtl8192fu_iqk_path_a()
812 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); in rtl8192fu_iqk_path_a()
813 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); in rtl8192fu_iqk_path_a()
814 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); in rtl8192fu_iqk_path_a()
815 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_iqk_path_a()
816 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); in rtl8192fu_iqk_path_a()
818 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(4), 1); in rtl8192fu_iqk_path_a()
819 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); in rtl8192fu_iqk_path_a()
824 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, val32); in rtl8192fu_iqk_path_a()
826 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_iqk_path_a()
829 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192fu_iqk_path_a()
830 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_iqk_path_a()
831 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_iqk_path_a()
832 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_iqk_path_a()
834 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214000f); in rtl8192fu_iqk_path_a()
835 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28140000); in rtl8192fu_iqk_path_a()
837 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192fu_iqk_path_a()
838 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_iqk_path_a()
841 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); in rtl8192fu_iqk_path_a()
844 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); in rtl8192fu_iqk_path_a()
845 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); in rtl8192fu_iqk_path_a()
850 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { in rtl8192fu_iqk_path_a()
856 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_iqk_path_a()
857 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192fu_iqk_path_a()
858 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192fu_iqk_path_a()
861 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_a()
863 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 1); in rtl8192fu_iqk_path_a()
865 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXMOD); in rtl8192fu_iqk_path_a()
870 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, in rtl8192fu_iqk_path_a()
872 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, in rtl8192fu_iqk_path_a()
874 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, in rtl8192fu_iqk_path_a()
878 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_AC, BIT(14), 0); in rtl8192fu_iqk_path_a()
879 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 0); in rtl8192fu_iqk_path_a()
880 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00810, 0); in rtl8192fu_iqk_path_a()
890 static int rtl8192fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192fu_rx_iqk_path_a() argument
897 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
900 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); in rtl8192fu_rx_iqk_path_a()
901 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); in rtl8192fu_rx_iqk_path_a()
902 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); in rtl8192fu_rx_iqk_path_a()
903 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x27); in rtl8192fu_rx_iqk_path_a()
906 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_a()
909 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192fu_rx_iqk_path_a()
910 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_rx_iqk_path_a()
911 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_rx_iqk_path_a()
912 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_rx_iqk_path_a()
914 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160027); in rtl8192fu_rx_iqk_path_a()
915 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); in rtl8192fu_rx_iqk_path_a()
918 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192fu_rx_iqk_path_a()
919 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_rx_iqk_path_a()
922 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); in rtl8192fu_rx_iqk_path_a()
925 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); in rtl8192fu_rx_iqk_path_a()
926 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); in rtl8192fu_rx_iqk_path_a()
931 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { in rtl8192fu_rx_iqk_path_a()
937 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_rx_iqk_path_a()
938 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192fu_rx_iqk_path_a()
939 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192fu_rx_iqk_path_a()
947 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
949 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, in rtl8192fu_rx_iqk_path_a()
956 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192fu_rx_iqk_path_a()
959 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
962 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); in rtl8192fu_rx_iqk_path_a()
963 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); in rtl8192fu_rx_iqk_path_a()
964 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); in rtl8192fu_rx_iqk_path_a()
965 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); in rtl8192fu_rx_iqk_path_a()
967 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); in rtl8192fu_rx_iqk_path_a()
968 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); in rtl8192fu_rx_iqk_path_a()
969 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); in rtl8192fu_rx_iqk_path_a()
970 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); in rtl8192fu_rx_iqk_path_a()
971 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); in rtl8192fu_rx_iqk_path_a()
972 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_a()
973 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); in rtl8192fu_rx_iqk_path_a()
976 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_a()
979 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_rx_iqk_path_a()
980 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8192fu_rx_iqk_path_a()
981 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_rx_iqk_path_a()
982 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_rx_iqk_path_a()
984 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82170000); in rtl8192fu_rx_iqk_path_a()
985 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28170000); in rtl8192fu_rx_iqk_path_a()
988 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_rx_iqk_path_a()
991 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); in rtl8192fu_rx_iqk_path_a()
994 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); in rtl8192fu_rx_iqk_path_a()
995 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); in rtl8192fu_rx_iqk_path_a()
1000 while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) { in rtl8192fu_rx_iqk_path_a()
1006 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_rx_iqk_path_a()
1007 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8192fu_rx_iqk_path_a()
1010 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
1012 rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 0); in rtl8192fu_rx_iqk_path_a()
1013 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0x02000); in rtl8192fu_rx_iqk_path_a()
1023 static int rtl8192fu_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192fu_iqk_path_b() argument
1027 u8 rfe = priv->rfe_type; in rtl8192fu_iqk_path_b()
1032 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_b()
1034 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); in rtl8192fu_iqk_path_b()
1035 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); in rtl8192fu_iqk_path_b()
1036 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); in rtl8192fu_iqk_path_b()
1037 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); in rtl8192fu_iqk_path_b()
1038 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); in rtl8192fu_iqk_path_b()
1039 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_iqk_path_b()
1040 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); in rtl8192fu_iqk_path_b()
1042 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(4), 1); in rtl8192fu_iqk_path_b()
1043 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); in rtl8192fu_iqk_path_b()
1045 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, in rtl8192fu_iqk_path_b()
1048 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, in rtl8192fu_iqk_path_b()
1051 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_iqk_path_b()
1054 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_iqk_path_b()
1055 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_iqk_path_b()
1056 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192fu_iqk_path_b()
1057 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_iqk_path_b()
1059 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8214000F); in rtl8192fu_iqk_path_b()
1060 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28140000); in rtl8192fu_iqk_path_b()
1062 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192fu_iqk_path_b()
1063 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_iqk_path_b()
1066 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); in rtl8192fu_iqk_path_b()
1069 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); in rtl8192fu_iqk_path_b()
1070 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); in rtl8192fu_iqk_path_b()
1075 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { in rtl8192fu_iqk_path_b()
1081 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_iqk_path_b()
1082 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192fu_iqk_path_b()
1083 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192fu_iqk_path_b()
1086 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_b()
1088 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 1); in rtl8192fu_iqk_path_b()
1090 val32 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_TXMOD); in rtl8192fu_iqk_path_b()
1095 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, in rtl8192fu_iqk_path_b()
1097 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, in rtl8192fu_iqk_path_b()
1099 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, in rtl8192fu_iqk_path_b()
1103 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_AC, BIT(14), 0); in rtl8192fu_iqk_path_b()
1104 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 0); in rtl8192fu_iqk_path_b()
1105 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00810, 0); in rtl8192fu_iqk_path_b()
1112 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", in rtl8192fu_iqk_path_b()
1118 static int rtl8192fu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192fu_rx_iqk_path_b() argument
1125 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_b()
1127 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); in rtl8192fu_rx_iqk_path_b()
1128 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); in rtl8192fu_rx_iqk_path_b()
1129 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); in rtl8192fu_rx_iqk_path_b()
1130 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x67); in rtl8192fu_rx_iqk_path_b()
1132 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); in rtl8192fu_rx_iqk_path_b()
1133 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); in rtl8192fu_rx_iqk_path_b()
1134 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); in rtl8192fu_rx_iqk_path_b()
1135 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); in rtl8192fu_rx_iqk_path_b()
1136 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); in rtl8192fu_rx_iqk_path_b()
1137 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_b()
1138 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); in rtl8192fu_rx_iqk_path_b()
1140 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_b()
1143 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_rx_iqk_path_b()
1144 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_rx_iqk_path_b()
1145 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192fu_rx_iqk_path_b()
1146 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_rx_iqk_path_b()
1148 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160027); in rtl8192fu_rx_iqk_path_b()
1149 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160000); in rtl8192fu_rx_iqk_path_b()
1152 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); in rtl8192fu_rx_iqk_path_b()
1155 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); in rtl8192fu_rx_iqk_path_b()
1156 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); in rtl8192fu_rx_iqk_path_b()
1161 while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { in rtl8192fu_rx_iqk_path_b()
1167 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_rx_iqk_path_b()
1168 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192fu_rx_iqk_path_b()
1169 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192fu_rx_iqk_path_b()
1177 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_b()
1179 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, in rtl8192fu_rx_iqk_path_b()
1186 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192fu_rx_iqk_path_b()
1189 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_b()
1191 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); in rtl8192fu_rx_iqk_path_b()
1192 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); in rtl8192fu_rx_iqk_path_b()
1193 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); in rtl8192fu_rx_iqk_path_b()
1194 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); in rtl8192fu_rx_iqk_path_b()
1196 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); in rtl8192fu_rx_iqk_path_b()
1197 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); in rtl8192fu_rx_iqk_path_b()
1198 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); in rtl8192fu_rx_iqk_path_b()
1199 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); in rtl8192fu_rx_iqk_path_b()
1200 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); in rtl8192fu_rx_iqk_path_b()
1201 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_b()
1202 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); in rtl8192fu_rx_iqk_path_b()
1204 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_b()
1207 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_rx_iqk_path_b()
1208 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192fu_rx_iqk_path_b()
1209 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192fu_rx_iqk_path_b()
1210 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); in rtl8192fu_rx_iqk_path_b()
1212 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82170000); in rtl8192fu_rx_iqk_path_b()
1213 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28170000); in rtl8192fu_rx_iqk_path_b()
1216 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_rx_iqk_path_b()
1219 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192fu_rx_iqk_path_b()
1222 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); in rtl8192fu_rx_iqk_path_b()
1223 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); in rtl8192fu_rx_iqk_path_b()
1228 while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) { in rtl8192fu_rx_iqk_path_b()
1233 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_rx_iqk_path_b()
1234 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8192fu_rx_iqk_path_b()
1235 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8192fu_rx_iqk_path_b()
1237 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_b()
1238 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); in rtl8192fu_rx_iqk_path_b()
1240 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 0); in rtl8192fu_rx_iqk_path_b()
1241 rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 0); in rtl8192fu_rx_iqk_path_b()
1242 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0x02000); in rtl8192fu_rx_iqk_path_b()
1249 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", in rtl8192fu_rx_iqk_path_b()
1255 static void rtl8192fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8192fu_phy_iqcalibrate() argument
1272 struct device *dev = &priv->udev->dev; in rtl8192fu_phy_iqcalibrate()
1274 u8 rfe = priv->rfe_type; in rtl8192fu_phy_iqcalibrate()
1283 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_phy_iqcalibrate()
1285 rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192fu_phy_iqcalibrate()
1286 rx_initial_gain_b = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8192fu_phy_iqcalibrate()
1290 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8192fu_phy_iqcalibrate()
1292 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192fu_phy_iqcalibrate()
1293 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8192fu_phy_iqcalibrate()
1294 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192fu_phy_iqcalibrate()
1298 rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); in rtl8192fu_phy_iqcalibrate()
1301 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8192fu_phy_iqcalibrate()
1302 rtl8xxxu_write8_clear(priv, REG_GPIO_MUXCFG, GPIO_MUXCFG_IO_SEL_ENBT); in rtl8192fu_phy_iqcalibrate()
1307 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF, 0x7); in rtl8192fu_phy_iqcalibrate()
1308 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x1, 0x0); in rtl8192fu_phy_iqcalibrate()
1310 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF00, 0x7); in rtl8192fu_phy_iqcalibrate()
1311 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x4, 0x0); in rtl8192fu_phy_iqcalibrate()
1313 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF000, 0x7); in rtl8192fu_phy_iqcalibrate()
1314 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8, 0x0); in rtl8192fu_phy_iqcalibrate()
1317 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0, 0x7); in rtl8192fu_phy_iqcalibrate()
1318 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x20000, 0x0); in rtl8192fu_phy_iqcalibrate()
1320 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0000, 0x7); in rtl8192fu_phy_iqcalibrate()
1321 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x100000, 0x0); in rtl8192fu_phy_iqcalibrate()
1323 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 0xF000, 0x7); in rtl8192fu_phy_iqcalibrate()
1324 rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8000000, 0x0); in rtl8192fu_phy_iqcalibrate()
1327 if (priv->rf_paths > 1) { in rtl8192fu_phy_iqcalibrate()
1329 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000); in rtl8192fu_phy_iqcalibrate()
1330 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000); in rtl8192fu_phy_iqcalibrate()
1331 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_phy_iqcalibrate()
1335 path_a_ok = rtl8192fu_iqk_path_a(priv); in rtl8192fu_phy_iqcalibrate()
1338 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192fu_phy_iqcalibrate()
1341 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192fu_phy_iqcalibrate()
1351 path_a_ok = rtl8192fu_rx_iqk_path_a(priv); in rtl8192fu_phy_iqcalibrate()
1354 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8192fu_phy_iqcalibrate()
1357 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192fu_phy_iqcalibrate()
1369 if (priv->rf_paths > 1) { in rtl8192fu_phy_iqcalibrate()
1371 path_b_ok = rtl8192fu_iqk_path_b(priv); in rtl8192fu_phy_iqcalibrate()
1374 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192fu_phy_iqcalibrate()
1377 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192fu_phy_iqcalibrate()
1387 path_b_ok = rtl8192fu_rx_iqk_path_b(priv); in rtl8192fu_phy_iqcalibrate()
1390 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8192fu_phy_iqcalibrate()
1393 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8192fu_phy_iqcalibrate()
1407 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_phy_iqcalibrate()
1409 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xcc0000c0); in rtl8192fu_phy_iqcalibrate()
1411 rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44bbbb44); in rtl8192fu_phy_iqcalibrate()
1412 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x80408040); in rtl8192fu_phy_iqcalibrate()
1413 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005433); in rtl8192fu_phy_iqcalibrate()
1414 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000004e4); in rtl8192fu_phy_iqcalibrate()
1415 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400); in rtl8192fu_phy_iqcalibrate()
1416 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); in rtl8192fu_phy_iqcalibrate()
1419 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8192fu_phy_iqcalibrate()
1423 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192fu_phy_iqcalibrate()
1426 rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192fu_phy_iqcalibrate()
1428 rtl8xxxu_write32_clear(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); in rtl8192fu_phy_iqcalibrate()
1431 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 0x50); in rtl8192fu_phy_iqcalibrate()
1432 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, in rtl8192fu_phy_iqcalibrate()
1434 if (priv->rf_paths > 1) { in rtl8192fu_phy_iqcalibrate()
1435 rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, 0x50); in rtl8192fu_phy_iqcalibrate()
1436 rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, in rtl8192fu_phy_iqcalibrate()
1441 static void rtl8192fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8192fu_phy_iq_calibrate() argument
1445 struct device *dev = &priv->udev->dev; in rtl8192fu_phy_iq_calibrate()
1449 u8 rfe = priv->rfe_type; in rtl8192fu_phy_iq_calibrate()
1457 rfe_path_select = rtl8xxxu_read32(priv, REG_RFE_PATH_SELECT); in rtl8192fu_phy_iq_calibrate()
1459 path_a_0xdf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); in rtl8192fu_phy_iq_calibrate()
1460 path_a_0x35 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_P1); in rtl8192fu_phy_iq_calibrate()
1461 path_b_0xdf = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA); in rtl8192fu_phy_iq_calibrate()
1462 path_b_0x35 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_P1); in rtl8192fu_phy_iq_calibrate()
1471 rtl8192fu_phy_iqcalibrate(priv, result, i); in rtl8192fu_phy_iq_calibrate()
1474 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); in rtl8192fu_phy_iq_calibrate()
1482 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); in rtl8192fu_phy_iq_calibrate()
1488 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); in rtl8192fu_phy_iq_calibrate()
1522 rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_A, 0x3ff00000, 0x100); in rtl8192fu_phy_iq_calibrate()
1523 rtl8xxxu_write32_mask(priv, REG_NP_ANTA, 0x3ff, 0); in rtl8192fu_phy_iq_calibrate()
1524 rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_B, 0x3ff00000, 0x100); in rtl8192fu_phy_iq_calibrate()
1525 rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, 0x3ff, 0); in rtl8192fu_phy_iq_calibrate()
1529 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8192fu_phy_iq_calibrate()
1533 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8192fu_phy_iq_calibrate()
1537 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, path_a_0xdf); in rtl8192fu_phy_iq_calibrate()
1538 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, path_a_0x35); in rtl8192fu_phy_iq_calibrate()
1539 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, path_b_0xdf); in rtl8192fu_phy_iq_calibrate()
1540 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, path_b_0x35); in rtl8192fu_phy_iq_calibrate()
1543 rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x70000); in rtl8192fu_phy_iq_calibrate()
1544 rtl8xxxu_write32_clear(priv, REG_LEDCFG0, 0x6c00000); in rtl8192fu_phy_iq_calibrate()
1545 rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28)); in rtl8192fu_phy_iq_calibrate()
1546 rtl8xxxu_write32_clear(priv, REG_SW_GPIO_SHARE_CTRL_0, in rtl8192fu_phy_iq_calibrate()
1557 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192fu_phy_iq_calibrate()
1560 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192fu_phy_iq_calibrate()
1563 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, in rtl8192fu_phy_iq_calibrate()
1565 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, in rtl8192fu_phy_iq_calibrate()
1567 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, in rtl8192fu_phy_iq_calibrate()
1569 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, in rtl8192fu_phy_iq_calibrate()
1572 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, in rtl8192fu_phy_iq_calibrate()
1574 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, in rtl8192fu_phy_iq_calibrate()
1576 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, in rtl8192fu_phy_iq_calibrate()
1578 rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, in rtl8192fu_phy_iq_calibrate()
1582 rtl8xxxu_write32_clear(priv, REG_RFE_OPT62, BIT(2)); in rtl8192fu_phy_iq_calibrate()
1585 rtl8xxxu_write32(priv, REG_RFE_OPT, 0x03000003); in rtl8192fu_phy_iq_calibrate()
1587 rtl8xxxu_write32(priv, REG_RFE_PATH_SELECT, rfe_path_select); in rtl8192fu_phy_iq_calibrate()
1591 static void rtl8192fu_disabled_to_emu(struct rtl8xxxu_priv *priv) in rtl8192fu_disabled_to_emu() argument
1593 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, in rtl8192fu_disabled_to_emu()
1596 rtl8xxxu_write32_clear(priv, REG_GPIO_INTM, BIT(16)); in rtl8192fu_disabled_to_emu()
1598 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, in rtl8192fu_disabled_to_emu()
1602 static int rtl8192fu_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8192fu_emu_to_active() argument
1609 rtl8xxxu_write8_set(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); in rtl8192fu_emu_to_active()
1612 rtl8xxxu_write32_clear(priv, REG_PAD_CTRL1, BIT(28)); in rtl8192fu_emu_to_active()
1617 rtl8xxxu_write8_clear(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); in rtl8192fu_emu_to_active()
1620 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, val16); in rtl8192fu_emu_to_active()
1624 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_emu_to_active()
1634 rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); in rtl8192fu_emu_to_active()
1637 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_emu_to_active()
1648 rtl8xxxu_write32_set(priv, REG_AFE_MISC, BIT(18)); in rtl8192fu_emu_to_active()
1650 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN); in rtl8192fu_emu_to_active()
1652 rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, in rtl8192fu_emu_to_active()
1656 rtl8xxxu_write32_set(priv, REG_LDO_SW_CTRL, BIT(31)); in rtl8192fu_emu_to_active()
1658 rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_ENABLE); in rtl8192fu_emu_to_active()
1661 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_emu_to_active()
1672 rtl8xxxu_write8_set(priv, REG_AFE_MISC, AFE_MISC_WL_XTAL_CTRL); in rtl8192fu_emu_to_active()
1675 rtl8xxxu_write16_set(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); in rtl8192fu_emu_to_active()
1678 rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_IRQ); in rtl8192fu_emu_to_active()
1681 rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_INPUT); in rtl8192fu_emu_to_active()
1684 rtl8xxxu_write8_set(priv, REG_HSIMR, BIT(0)); in rtl8192fu_emu_to_active()
1687 rtl8xxxu_write8_clear(priv, REG_MULTI_FUNC_CTRL, MULTI_WIFI_HW_ROF_EN); in rtl8192fu_emu_to_active()
1690 rtl8xxxu_write8_set(priv, REG_RSV_CTRL, BIT(7)); in rtl8192fu_emu_to_active()
1693 rtl8xxxu_write16_set(priv, REG_MULTI_FUNC_CTRL, BIT(14)); in rtl8192fu_emu_to_active()
1696 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); in rtl8192fu_emu_to_active()
1699 rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, 0); in rtl8192fu_emu_to_active()
1702 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_SDMRSTB | RF_RSTB | RF_ENABLE); in rtl8192fu_emu_to_active()
1705 rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, RF_SDMRSTB | RF_RSTB | RF_ENABLE); in rtl8192fu_emu_to_active()
1708 rtl8xxxu_write8_set(priv, REG_RSVD_1, BIT(5)); in rtl8192fu_emu_to_active()
1711 rtl8xxxu_write8(priv, REG_RSVD_4, 0xcc); in rtl8192fu_emu_to_active()
1714 rtl8xxxu_write8_clear(priv, REG_AFE_XTAL_CTRL, BIT(4) | BIT(3)); in rtl8192fu_emu_to_active()
1717 rtl8xxxu_write32(priv, REG_GPIO_A0, 0xffffffff); in rtl8192fu_emu_to_active()
1720 rtl8xxxu_write8(priv, REG_GPIO_B0, 0xff); in rtl8192fu_emu_to_active()
1723 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(7)); in rtl8192fu_emu_to_active()
1728 static int rtl8192fu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8192fu_active_to_emu() argument
1734 rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); in rtl8192fu_active_to_emu()
1737 rtl8xxxu_write16_clear(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); in rtl8192fu_active_to_emu()
1740 rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); in rtl8192fu_active_to_emu()
1743 rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_OFF); in rtl8192fu_active_to_emu()
1746 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192fu_active_to_emu()
1757 rtl8xxxu_write8_set(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); in rtl8192fu_active_to_emu()
1760 rtl8xxxu_write8_clear(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); in rtl8192fu_active_to_emu()
1765 static int rtl8192fu_emu_to_disabled(struct rtl8xxxu_priv *priv) in rtl8192fu_emu_to_disabled() argument
1770 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); in rtl8192fu_emu_to_disabled()
1773 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); in rtl8192fu_emu_to_disabled()
1776 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); in rtl8192fu_emu_to_disabled()
1779 rtl8xxxu_write32_set(priv, REG_GPIO_INTM, BIT(16)); in rtl8192fu_emu_to_disabled()
1784 static int rtl8192fu_active_to_lps(struct rtl8xxxu_priv *priv) in rtl8192fu_active_to_lps() argument
1786 struct device *dev = &priv->udev->dev; in rtl8192fu_active_to_lps()
1792 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8192fu_active_to_lps()
1798 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192fu_active_to_lps()
1811 rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); in rtl8192fu_active_to_lps()
1816 rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BB_GLB_RSTN); in rtl8192fu_active_to_lps()
1819 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192fu_active_to_lps()
1823 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192fu_active_to_lps()
1826 rtl8xxxu_write8_set(priv, REG_DUAL_TSF_RST, DUAL_TSF_TX_OK); in rtl8192fu_active_to_lps()
1831 static int rtl8192fu_power_on(struct rtl8xxxu_priv *priv) in rtl8192fu_power_on() argument
1836 rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80); in rtl8192fu_power_on()
1838 rtl8192fu_disabled_to_emu(priv); in rtl8192fu_power_on()
1840 ret = rtl8192fu_emu_to_active(priv); in rtl8192fu_power_on()
1844 rtl8xxxu_write16(priv, REG_CR, 0); in rtl8192fu_power_on()
1846 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192fu_power_on()
1852 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192fu_power_on()
1857 static void rtl8192fu_power_off(struct rtl8xxxu_priv *priv) in rtl8192fu_power_off() argument
1859 rtl8xxxu_flush_fifo(priv); in rtl8192fu_power_off()
1862 rtl8xxxu_write8_clear(priv, REG_TX_REPORT_CTRL, in rtl8192fu_power_off()
1866 rtl8xxxu_write8(priv, REG_CR, 0x00); in rtl8192fu_power_off()
1868 rtl8192fu_active_to_lps(priv); in rtl8192fu_power_off()
1871 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8192fu_power_off()
1872 rtl8xxxu_firmware_self_reset(priv); in rtl8192fu_power_off()
1875 rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); in rtl8192fu_power_off()
1878 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8192fu_power_off()
1880 rtl8192fu_active_to_emu(priv); in rtl8192fu_power_off()
1881 rtl8192fu_emu_to_disabled(priv); in rtl8192fu_power_off()
1884 static void rtl8192f_reset_8051(struct rtl8xxxu_priv *priv) in rtl8192f_reset_8051() argument
1886 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); in rtl8192f_reset_8051()
1888 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL + 1, BIT(0)); in rtl8192f_reset_8051()
1890 rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); in rtl8192f_reset_8051()
1892 rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); in rtl8192f_reset_8051()
1894 rtl8xxxu_write8_set(priv, REG_RSV_CTRL + 1, BIT(0)); in rtl8192f_reset_8051()
1896 rtl8xxxu_write16_set(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); in rtl8192f_reset_8051()
1899 static void rtl8192f_enable_rf(struct rtl8xxxu_priv *priv) in rtl8192f_enable_rf() argument
1903 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); in rtl8192f_enable_rf()
1905 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8192f_enable_rf()
1909 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8192f_enable_rf()
1911 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); in rtl8192f_enable_rf()
1914 static void rtl8192f_disable_rf(struct rtl8xxxu_priv *priv) in rtl8192f_disable_rf() argument
1918 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8192f_disable_rf()
1920 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8192f_disable_rf()
1923 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); in rtl8192f_disable_rf()
1926 static void rtl8192f_usb_quirks(struct rtl8xxxu_priv *priv) in rtl8192f_usb_quirks() argument
1930 rtl8xxxu_gen2_usb_quirks(priv); in rtl8192f_usb_quirks()
1932 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192f_usb_quirks()
1934 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192f_usb_quirks()
1940 static void rtl8192f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) in rtl8192f_set_crystal_cap() argument
1942 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; in rtl8192f_set_crystal_cap()
1948 xtal1 = rtl8xxxu_read32(priv, REG_AFE_PLL_CTRL); in rtl8192f_set_crystal_cap()
1949 xtal0 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); in rtl8192f_set_crystal_cap()
1951 dev_dbg(&priv->udev->dev, in rtl8192f_set_crystal_cap()
1961 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, xtal1); in rtl8192f_set_crystal_cap()
1962 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, xtal0); in rtl8192f_set_crystal_cap()
1967 static s8 rtl8192f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) in rtl8192f_cck_rssi() argument
1998 struct rtl8xxxu_priv *priv = container_of(led_cdev, in rtl8192fu_led_brightness_set() local
2004 rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_0, 0x20080); in rtl8192fu_led_brightness_set()
2005 rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x1b0000); in rtl8192fu_led_brightness_set()
2007 ledcfg = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8192fu_led_brightness_set()
2034 rtl8xxxu_write32(priv, REG_LEDCFG0, ledcfg); in rtl8192fu_led_brightness_set()