Lines Matching refs:priv
308 static int rtl8188fu_identify_chip(struct rtl8xxxu_priv *priv) in rtl8188fu_identify_chip() argument
310 struct device *dev = &priv->udev->dev; in rtl8188fu_identify_chip()
314 strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name)); in rtl8188fu_identify_chip()
315 priv->rtl_chip = RTL8188F; in rtl8188fu_identify_chip()
316 priv->rf_paths = 1; in rtl8188fu_identify_chip()
317 priv->rx_paths = 1; in rtl8188fu_identify_chip()
318 priv->tx_paths = 1; in rtl8188fu_identify_chip()
319 priv->has_wifi = 1; in rtl8188fu_identify_chip()
321 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8188fu_identify_chip()
322 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8188fu_identify_chip()
330 rtl8xxxu_identify_vendor_2bits(priv, vendor); in rtl8188fu_identify_chip()
332 ret = rtl8xxxu_config_endpoints_no_sie(priv); in rtl8188fu_identify_chip()
358 rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8188f_set_tx_power() argument
366 cck = priv->cck_tx_power_index_A[cck_group]; in rtl8188f_set_tx_power()
368 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8188f_set_tx_power()
371 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8188f_set_tx_power()
373 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8188f_set_tx_power()
376 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8188f_set_tx_power()
378 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8188f_set_tx_power()
379 ofdmbase += priv->ofdm_tx_power_diff[0].a; in rtl8188f_set_tx_power()
382 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8188f_set_tx_power()
383 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8188f_set_tx_power()
385 mcsbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8188f_set_tx_power()
388 mcsbase += priv->ht40_tx_power_diff[0].a; in rtl8188f_set_tx_power()
390 mcsbase += priv->ht20_tx_power_diff[0].a; in rtl8188f_set_tx_power()
393 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8188f_set_tx_power()
394 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8188f_set_tx_power()
395 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); in rtl8188f_set_tx_power()
396 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); in rtl8188f_set_tx_power()
400 static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) in rtl8188f_spur_calibration() argument
432 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); in rtl8188f_spur_calibration()
434 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
437 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); in rtl8188f_spur_calibration()
439 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
442 reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8188f_spur_calibration()
447 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8188f_spur_calibration()
455 initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188f_spur_calibration()
458 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
460 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
464 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188f_spur_calibration()
467 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); in rtl8188f_spur_calibration()
470 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); in rtl8188f_spur_calibration()
473 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); in rtl8188f_spur_calibration()
477 do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; in rtl8188f_spur_calibration()
480 rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); in rtl8188f_spur_calibration()
483 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); in rtl8188f_spur_calibration()
486 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
488 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
490 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); in rtl8188f_spur_calibration()
493 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); in rtl8188f_spur_calibration()
494 rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); in rtl8188f_spur_calibration()
495 rtl8xxxu_write32(priv, 0xd48, 0x0); in rtl8188f_spur_calibration()
496 rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); in rtl8188f_spur_calibration()
499 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); in rtl8188f_spur_calibration()
501 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); in rtl8188f_spur_calibration()
509 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); in rtl8188f_spur_calibration()
511 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); in rtl8188f_spur_calibration()
516 struct rtl8xxxu_priv *priv = hw->priv; in rtl8188fu_config_channel() local
524 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8188fu_config_channel()
527 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8188fu_config_channel()
530 rtl8188f_spur_calibration(priv, channel); in rtl8188fu_config_channel()
533 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
536 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
538 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8188fu_config_channel()
541 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188fu_config_channel()
544 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
546 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
552 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
555 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8188fu_config_channel()
557 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8188fu_config_channel()
560 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8188fu_config_channel()
563 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8188fu_config_channel()
566 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); in rtl8188fu_config_channel()
569 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); in rtl8188fu_config_channel()
571 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); in rtl8188fu_config_channel()
573 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); in rtl8188fu_config_channel()
575 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); in rtl8188fu_config_channel()
583 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); in rtl8188fu_config_channel()
596 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); in rtl8188fu_config_channel()
600 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); in rtl8188fu_config_channel()
602 val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); in rtl8188fu_config_channel()
609 rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); in rtl8188fu_config_channel()
611 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); in rtl8188fu_config_channel()
613 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8188fu_config_channel()
623 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8188fu_config_channel()
631 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); in rtl8188fu_config_channel()
638 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); in rtl8188fu_config_channel()
641 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00140); in rtl8188fu_config_channel()
642 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); in rtl8188fu_config_channel()
645 static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) in rtl8188fu_init_aggregation() argument
651 val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); in rtl8188fu_init_aggregation()
654 rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); in rtl8188fu_init_aggregation()
655 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); in rtl8188fu_init_aggregation()
658 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); in rtl8188fu_init_aggregation()
661 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); in rtl8188fu_init_aggregation()
665 rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); in rtl8188fu_init_aggregation()
668 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); in rtl8188fu_init_aggregation()
669 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); in rtl8188fu_init_aggregation()
670 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); in rtl8188fu_init_aggregation()
673 static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) in rtl8188fu_init_statistics() argument
678 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); in rtl8188fu_init_statistics()
679 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); in rtl8188fu_init_statistics()
680 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); in rtl8188fu_init_statistics()
681 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); in rtl8188fu_init_statistics()
684 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_init_statistics()
686 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_init_statistics()
689 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8188fu_init_statistics()
692 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8188fu_init_statistics()
695 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8188fu_init_statistics()
697 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8188fu_init_statistics()
704 static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8188fu_parse_efuse() argument
706 struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; in rtl8188fu_parse_efuse()
712 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8188fu_parse_efuse()
714 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8188fu_parse_efuse()
717 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8188fu_parse_efuse()
721 for (i = 0; i < ARRAY_SIZE(priv->cck_tx_power_index_A); i++) { in rtl8188fu_parse_efuse()
722 if (priv->cck_tx_power_index_A[i] > TX_POWER_INDEX_MAX) in rtl8188fu_parse_efuse()
723 priv->cck_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_CCK; in rtl8188fu_parse_efuse()
726 for (i = 0; i < ARRAY_SIZE(priv->ht40_1s_tx_power_index_A); i++) { in rtl8188fu_parse_efuse()
727 if (priv->ht40_1s_tx_power_index_A[i] > TX_POWER_INDEX_MAX) in rtl8188fu_parse_efuse()
728 priv->ht40_1s_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_HT40; in rtl8188fu_parse_efuse()
731 priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; in rtl8188fu_parse_efuse()
732 priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; in rtl8188fu_parse_efuse()
734 priv->default_crystal_cap = efuse->xtal_k & 0x3f; in rtl8188fu_parse_efuse()
739 static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8188fu_load_firmware() argument
746 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8188fu_load_firmware()
751 static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8188fu_init_phy_bb() argument
757 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8188fu_init_phy_bb()
759 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8188fu_init_phy_bb()
765 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8188fu_init_phy_bb()
769 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); in rtl8188fu_init_phy_bb()
772 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8188fu_init_phy_bb()
774 rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); in rtl8188fu_init_phy_bb()
775 rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); in rtl8188fu_init_phy_bb()
778 static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8188fu_init_phy_rf() argument
782 if (priv->chip_cut == 1) in rtl8188fu_init_phy_rf()
783 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); in rtl8188fu_init_phy_rf()
785 ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); in rtl8188fu_init_phy_rf()
790 void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) in rtl8188f_phy_lc_calibrate() argument
797 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); in rtl8188f_phy_lc_calibrate()
802 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8188f_phy_lc_calibrate()
806 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8188f_phy_lc_calibrate()
810 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8188f_phy_lc_calibrate()
813 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); in rtl8188f_phy_lc_calibrate()
816 if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) in rtl8188f_phy_lc_calibrate()
822 dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); in rtl8188f_phy_lc_calibrate()
824 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); in rtl8188f_phy_lc_calibrate()
828 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); in rtl8188f_phy_lc_calibrate()
830 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); in rtl8188f_phy_lc_calibrate()
833 static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) in rtl8188fu_iqk_path_a() argument
841 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
843 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
848 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_iqk_path_a()
850 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_iqk_path_a()
851 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); in rtl8188fu_iqk_path_a()
852 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8188fu_iqk_path_a()
853 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); in rtl8188fu_iqk_path_a()
856 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); in rtl8188fu_iqk_path_a()
857 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); in rtl8188fu_iqk_path_a()
860 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
863 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
866 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8188fu_iqk_path_a()
867 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8188fu_iqk_path_a()
869 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); in rtl8188fu_iqk_path_a()
870 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); in rtl8188fu_iqk_path_a()
873 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8188fu_iqk_path_a()
876 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8188fu_iqk_path_a()
877 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8188fu_iqk_path_a()
884 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
886 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
888 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); in rtl8188fu_iqk_path_a()
891 *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); in rtl8188fu_iqk_path_a()
894 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8188fu_iqk_path_a()
895 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8188fu_iqk_path_a()
896 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8188fu_iqk_path_a()
906 static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) in rtl8188fu_rx_iqk_path_a() argument
914 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
916 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
921 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_rx_iqk_path_a()
923 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_rx_iqk_path_a()
924 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8188fu_rx_iqk_path_a()
925 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8188fu_rx_iqk_path_a()
926 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); in rtl8188fu_rx_iqk_path_a()
929 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); in rtl8188fu_rx_iqk_path_a()
930 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); in rtl8188fu_rx_iqk_path_a()
935 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
938 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
943 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8188fu_rx_iqk_path_a()
944 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8188fu_rx_iqk_path_a()
947 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); in rtl8188fu_rx_iqk_path_a()
948 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); in rtl8188fu_rx_iqk_path_a()
950 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); in rtl8188fu_rx_iqk_path_a()
951 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); in rtl8188fu_rx_iqk_path_a()
954 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8188fu_rx_iqk_path_a()
957 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8188fu_rx_iqk_path_a()
958 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8188fu_rx_iqk_path_a()
965 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
967 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
969 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); in rtl8188fu_rx_iqk_path_a()
972 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8188fu_rx_iqk_path_a()
973 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8188fu_rx_iqk_path_a()
974 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8188fu_rx_iqk_path_a()
985 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8188fu_rx_iqk_path_a()
990 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
992 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
994 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_rx_iqk_path_a()
996 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_rx_iqk_path_a()
997 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8188fu_rx_iqk_path_a()
998 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8188fu_rx_iqk_path_a()
999 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8188fu_rx_iqk_path_a()
1004 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); in rtl8188fu_rx_iqk_path_a()
1005 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x51000); in rtl8188fu_rx_iqk_path_a()
1010 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
1013 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1018 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8188fu_rx_iqk_path_a()
1021 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); in rtl8188fu_rx_iqk_path_a()
1022 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); in rtl8188fu_rx_iqk_path_a()
1024 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); in rtl8188fu_rx_iqk_path_a()
1025 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); in rtl8188fu_rx_iqk_path_a()
1028 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8188fu_rx_iqk_path_a()
1031 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8188fu_rx_iqk_path_a()
1032 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8188fu_rx_iqk_path_a()
1039 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
1041 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1043 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); in rtl8188fu_rx_iqk_path_a()
1046 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); in rtl8188fu_rx_iqk_path_a()
1049 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8188fu_rx_iqk_path_a()
1050 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8188fu_rx_iqk_path_a()
1061 static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8188fu_phy_iqcalibrate() argument
1064 struct device *dev = &priv->udev->dev; in rtl8188fu_phy_iqcalibrate()
1095 rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1099 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8188fu_phy_iqcalibrate()
1101 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8188fu_phy_iqcalibrate()
1102 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8188fu_phy_iqcalibrate()
1103 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8188fu_phy_iqcalibrate()
1106 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8188fu_phy_iqcalibrate()
1109 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); in rtl8188fu_phy_iqcalibrate()
1110 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); in rtl8188fu_phy_iqcalibrate()
1114 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8188fu_phy_iqcalibrate()
1115 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); in rtl8188fu_phy_iqcalibrate()
1118 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8188fu_phy_iqcalibrate()
1119 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8188fu_phy_iqcalibrate()
1120 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); in rtl8188fu_phy_iqcalibrate()
1123 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); in rtl8188fu_phy_iqcalibrate()
1125 rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); in rtl8188fu_phy_iqcalibrate()
1128 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1131 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1132 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8188fu_phy_iqcalibrate()
1133 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8188fu_phy_iqcalibrate()
1136 path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); in rtl8188fu_phy_iqcalibrate()
1138 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1140 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1142 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1146 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1154 path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); in rtl8188fu_phy_iqcalibrate()
1156 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1160 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1171 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1173 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1178 if (!priv->pi_enabled) { in rtl8188fu_phy_iqcalibrate()
1184 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); in rtl8188fu_phy_iqcalibrate()
1185 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); in rtl8188fu_phy_iqcalibrate()
1189 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8188fu_phy_iqcalibrate()
1193 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8188fu_phy_iqcalibrate()
1196 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8188fu_phy_iqcalibrate()
1197 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8188fu_phy_iqcalibrate()
1200 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); in rtl8188fu_phy_iqcalibrate()
1201 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); in rtl8188fu_phy_iqcalibrate()
1204 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1207 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
1208 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1211 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
1214 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8188fu_phy_iqcalibrate()
1215 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8188fu_phy_iqcalibrate()
1218 static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8188fu_phy_iq_calibrate() argument
1220 struct device *dev = &priv->udev->dev; in rtl8188fu_phy_iq_calibrate()
1231 path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8188fu_phy_iq_calibrate()
1232 path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); in rtl8188fu_phy_iq_calibrate()
1240 rtl8188fu_phy_iqcalibrate(priv, result, i); in rtl8188fu_phy_iq_calibrate()
1243 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); in rtl8188fu_phy_iq_calibrate()
1251 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); in rtl8188fu_phy_iq_calibrate()
1257 simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); in rtl8188fu_phy_iq_calibrate()
1285 priv->rege94 = reg_e94; in rtl8188fu_phy_iq_calibrate()
1287 priv->rege9c = reg_e9c; in rtl8188fu_phy_iq_calibrate()
1291 priv->regeb4 = reg_eb4; in rtl8188fu_phy_iq_calibrate()
1293 priv->regebc = reg_ebc; in rtl8188fu_phy_iq_calibrate()
1303 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8188fu_phy_iq_calibrate()
1304 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8188fu_phy_iq_calibrate()
1308 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8188fu_phy_iq_calibrate()
1311 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8188fu_phy_iq_calibrate()
1312 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8188fu_phy_iq_calibrate()
1314 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); in rtl8188fu_phy_iq_calibrate()
1315 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); in rtl8188fu_phy_iq_calibrate()
1318 static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) in rtl8188f_disabled_to_emu() argument
1323 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8188f_disabled_to_emu()
1325 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8188f_disabled_to_emu()
1328 val8 = rtl8xxxu_read8(priv, 0xc4); in rtl8188f_disabled_to_emu()
1330 rtl8xxxu_write8(priv, 0xc4, val8); in rtl8188f_disabled_to_emu()
1333 static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8188f_emu_to_active() argument
1340 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8188f_emu_to_active()
1342 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8188f_emu_to_active()
1346 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188f_emu_to_active()
1359 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8188f_emu_to_active()
1361 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8188f_emu_to_active()
1364 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8188f_emu_to_active()
1366 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8188f_emu_to_active()
1369 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8188f_emu_to_active()
1371 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8188f_emu_to_active()
1374 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188f_emu_to_active()
1388 val8 = rtl8xxxu_write8(priv, 0x27, 0x35); in rtl8188f_emu_to_active()
1393 static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8188fu_active_to_emu() argument
1400 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); in rtl8188fu_active_to_emu()
1403 val8 = rtl8xxxu_read8(priv, 0x4e); in rtl8188fu_active_to_emu()
1405 rtl8xxxu_write8(priv, 0x4e, val8); in rtl8188fu_active_to_emu()
1408 rtl8xxxu_write8(priv, 0x27, 0x34); in rtl8188fu_active_to_emu()
1411 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8188fu_active_to_emu()
1413 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8188fu_active_to_emu()
1416 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188fu_active_to_emu()
1433 static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) in rtl8188fu_emu_to_disabled() argument
1438 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8188fu_emu_to_disabled()
1441 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8188fu_emu_to_disabled()
1444 val8 = rtl8xxxu_read8(priv, 0xc4); in rtl8188fu_emu_to_disabled()
1446 rtl8xxxu_write8(priv, 0xc4, val8); in rtl8188fu_emu_to_disabled()
1451 static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) in rtl8188fu_active_to_lps() argument
1453 struct device *dev = &priv->udev->dev; in rtl8188fu_active_to_lps()
1460 val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); in rtl8188fu_active_to_lps()
1462 rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); in rtl8188fu_active_to_lps()
1465 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8188fu_active_to_lps()
1474 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8188fu_active_to_lps()
1488 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8188fu_active_to_lps()
1490 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8188fu_active_to_lps()
1495 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8188fu_active_to_lps()
1497 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8188fu_active_to_lps()
1500 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8188fu_active_to_lps()
1503 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8188fu_active_to_lps()
1506 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); in rtl8188fu_active_to_lps()
1508 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); in rtl8188fu_active_to_lps()
1514 static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) in rtl8188fu_power_on() argument
1519 rtl8188f_disabled_to_emu(priv); in rtl8188fu_power_on()
1521 ret = rtl8188f_emu_to_active(priv); in rtl8188fu_power_on()
1525 rtl8xxxu_write8(priv, REG_CR, 0); in rtl8188fu_power_on()
1527 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8188fu_power_on()
1533 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8188fu_power_on()
1539 static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) in rtl8188fu_power_off() argument
1544 rtl8xxxu_flush_fifo(priv); in rtl8188fu_power_off()
1546 val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); in rtl8188fu_power_off()
1548 rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); in rtl8188fu_power_off()
1550 rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); in rtl8188fu_power_off()
1551 rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); in rtl8188fu_power_off()
1554 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8188fu_power_off()
1556 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8188fu_power_off()
1559 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); in rtl8188fu_power_off()
1562 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8188fu_power_off()
1563 rtl8xxxu_firmware_self_reset(priv); in rtl8188fu_power_off()
1565 rtl8188fu_active_to_lps(priv); in rtl8188fu_power_off()
1568 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8188fu_power_off()
1570 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8188fu_power_off()
1573 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8188fu_power_off()
1575 rtl8188fu_active_to_emu(priv); in rtl8188fu_power_off()
1576 rtl8188fu_emu_to_disabled(priv); in rtl8188fu_power_off()
1582 static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) in rtl8188f_enable_rf() argument
1589 rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); in rtl8188f_enable_rf()
1605 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); in rtl8188f_enable_rf()
1608 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); in rtl8188f_enable_rf()
1611 rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); in rtl8188f_enable_rf()
1613 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_enable_rf()
1616 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_enable_rf()
1618 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); in rtl8188f_enable_rf()
1621 static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) in rtl8188f_disable_rf() argument
1625 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_disable_rf()
1627 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_disable_rf()
1630 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); in rtl8188f_disable_rf()
1633 static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) in rtl8188f_usb_quirks() argument
1638 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8188f_usb_quirks()
1640 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8188f_usb_quirks()
1642 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); in rtl8188f_usb_quirks()
1644 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); in rtl8188f_usb_quirks()
1650 void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) in rtl8188f_set_crystal_cap() argument
1652 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; in rtl8188f_set_crystal_cap()
1658 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); in rtl8188f_set_crystal_cap()
1660 dev_dbg(&priv->udev->dev, in rtl8188f_set_crystal_cap()
1671 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); in rtl8188f_set_crystal_cap()
1676 static s8 rtl8188f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) in rtl8188f_cck_rssi() argument