Lines Matching +full:0 +full:x0000fc00
20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
40 #define RF_BASE 0x0004
41 #define RF_SIZE 0x0010
55 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
56 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
57 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
58 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
59 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
60 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
61 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
62 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
63 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
64 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
65 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
66 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
72 #define FIRMWARE_IMAGE_BASE 0x0800
80 #define SHARED_KEY_TABLE_BASE 0x1000
81 #define PAIRWISE_KEY_TABLE_BASE 0x1200
82 #define PAIRWISE_TA_TABLE_BASE 0x1a00
110 #define HW_DEBUG_SETTING_BASE 0x2bf0
115 #define HW_BEACON_BASE0 0x2400
116 #define HW_BEACON_BASE1 0x2500
117 #define HW_BEACON_BASE2 0x2600
118 #define HW_BEACON_BASE3 0x2700
121 ( HW_BEACON_BASE0 + (__index * 0x0100) )
131 #define MAC_CSR0 0x3000
132 #define MAC_CSR0_REVISION FIELD32(0x0000000f)
133 #define MAC_CSR0_CHIPSET FIELD32(0x000ffff0)
137 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
141 #define MAC_CSR1 0x3004
142 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
143 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
144 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
147 * MAC_CSR2: STA MAC register 0.
149 #define MAC_CSR2 0x3008
150 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
151 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
152 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
153 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
163 #define MAC_CSR3 0x300c
164 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
165 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
166 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
169 * MAC_CSR4: BSSID register 0.
171 #define MAC_CSR4 0x3010
172 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
173 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
174 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
175 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
180 * This mask is used to mask off bits 0 and 1 of byte 5 of the
183 * 0: 1-BSSID mode (BSS index = 0)
184 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
186 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
188 #define MAC_CSR5 0x3014
189 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
190 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
191 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
196 #define MAC_CSR6 0x3018
197 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
202 #define MAC_CSR7 0x301c
208 #define MAC_CSR8 0x3020
209 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
210 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
211 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
218 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
220 #define MAC_CSR9 0x3024
221 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
222 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
223 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
224 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
229 #define MAC_CSR10 0x3028
237 #define MAC_CSR11 0x302c
238 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
239 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
240 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
241 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
245 * CURRENT_STATE: 0:sleep, 1:awake.
247 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
249 #define MAC_CSR12 0x3030
250 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
251 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
252 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
253 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
258 * MAC_CSR13_DIRx: GPIO direction: 0 = input; 1 = output
260 #define MAC_CSR13 0x3034
261 #define MAC_CSR13_VAL0 FIELD32(0x00000001)
262 #define MAC_CSR13_VAL1 FIELD32(0x00000002)
263 #define MAC_CSR13_VAL2 FIELD32(0x00000004)
264 #define MAC_CSR13_VAL3 FIELD32(0x00000008)
265 #define MAC_CSR13_VAL4 FIELD32(0x00000010)
266 #define MAC_CSR13_VAL5 FIELD32(0x00000020)
267 #define MAC_CSR13_VAL6 FIELD32(0x00000040)
268 #define MAC_CSR13_VAL7 FIELD32(0x00000080)
269 #define MAC_CSR13_DIR0 FIELD32(0x00000100)
270 #define MAC_CSR13_DIR1 FIELD32(0x00000200)
271 #define MAC_CSR13_DIR2 FIELD32(0x00000400)
272 #define MAC_CSR13_DIR3 FIELD32(0x00000800)
273 #define MAC_CSR13_DIR4 FIELD32(0x00001000)
274 #define MAC_CSR13_DIR5 FIELD32(0x00002000)
275 #define MAC_CSR13_DIR6 FIELD32(0x00004000)
276 #define MAC_CSR13_DIR7 FIELD32(0x00008000)
282 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
283 * SW_LED: s/w LED, 1: ON, 0: OFF.
284 * HW_LED_POLARITY: 0: active low, 1: active high.
286 #define MAC_CSR14 0x3038
287 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
288 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
289 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
290 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
291 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
292 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
297 #define MAC_CSR15 0x303c
319 #define TXRX_CSR0 0x3040
320 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
321 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
322 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
323 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
324 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
325 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
326 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
327 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
328 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
329 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
330 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
331 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
332 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
333 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
338 #define TXRX_CSR1 0x3044
339 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
340 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
341 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
342 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
343 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
344 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
345 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
346 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
351 #define TXRX_CSR2 0x3048
352 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
353 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
354 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
355 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
356 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
357 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
358 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
359 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
364 #define TXRX_CSR3 0x304c
365 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
366 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
367 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
368 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
369 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
370 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
371 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
372 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
376 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
378 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
379 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
381 #define TXRX_CSR4 0x3050
382 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
383 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
384 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
385 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
386 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
387 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
388 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
389 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
390 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
391 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
396 #define TXRX_CSR5 0x3054
401 #define TXRX_CSR6 0x3058
406 #define TXRX_CSR7 0x305c
407 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
408 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
409 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
410 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
415 #define TXRX_CSR8 0x3060
416 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
417 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
418 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
419 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
425 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
428 #define TXRX_CSR9 0x3064
429 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
430 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
431 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
432 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
433 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
434 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
439 #define TXRX_CSR10 0x3068
444 #define TXRX_CSR11 0x306c
449 #define TXRX_CSR12 0x3070
450 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
455 #define TXRX_CSR13 0x3074
456 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
461 #define TXRX_CSR14 0x3078
466 #define TXRX_CSR15 0x307c
476 #define PHY_CSR0 0x3080
477 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
478 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
483 #define PHY_CSR1 0x3084
484 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
489 #define PHY_CSR2 0x3088
495 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
498 #define PHY_CSR3 0x308c
499 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
500 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
501 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
502 #define PHY_CSR3_BUSY FIELD32(0x00010000)
508 * IF_SELECT: 1: select IF to program, 0: select RF to program.
512 #define PHY_CSR4 0x3090
513 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
514 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
515 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
516 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
517 #define PHY_CSR4_BUSY FIELD32(0x80000000)
522 #define PHY_CSR5 0x3094
523 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
528 #define PHY_CSR6 0x3098
529 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
534 #define PHY_CSR7 0x309c
543 #define SEC_CSR0 0x30a0
544 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
545 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
546 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
547 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
548 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
549 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
550 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
551 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
552 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
553 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
554 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
555 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
556 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
557 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
558 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
559 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
564 #define SEC_CSR1 0x30a4
565 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
566 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
567 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
568 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
569 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
570 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
571 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
572 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
576 * SEC_CSR2: pairwise key table valid bitmap 0.
579 #define SEC_CSR2 0x30a8
580 #define SEC_CSR3 0x30ac
585 #define SEC_CSR4 0x30b0
586 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
587 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
588 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
589 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
594 #define SEC_CSR5 0x30b4
595 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
596 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
597 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
598 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
599 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
600 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
601 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
602 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
611 #define STA_CSR0 0x30c0
612 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
613 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
618 #define STA_CSR1 0x30c4
619 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
620 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
625 #define STA_CSR2 0x30c8
626 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
627 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
632 #define STA_CSR3 0x30cc
633 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
638 #define STA_CSR4 0x30d0
639 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
640 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
645 #define STA_CSR5 0x30d4
646 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
647 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
656 #define QOS_CSR1 0x30e4
657 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
658 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
663 #define QOS_CSR2 0x30e8
667 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
670 #define QOS_CSR3 0x30ec
671 #define QOS_CSR4 0x30f0
676 #define QOS_CSR5 0x30f4
689 #define AIFSN_CSR 0x0400
690 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
691 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
692 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
693 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
702 #define CWMIN_CSR 0x0404
703 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
704 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
705 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
706 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
715 #define CWMAX_CSR 0x0408
716 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
717 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
718 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
719 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
726 #define AC_TXOP_CSR0 0x040c
727 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
728 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
735 #define AC_TXOP_CSR1 0x0410
736 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
737 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
747 #define BBP_R2_BG_MODE FIELD8(0x20)
752 #define BBP_R3_SMART_MODE FIELD8(0x01)
756 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
761 * 0x1: Software controlled antenna switching (fixed or SW diversity)
762 * 0x2: Hardware diversity.
764 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
765 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
770 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
779 #define RF3_TXPOWER FIELD32(0x00003e00)
784 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
794 #define EEPROM_MAC_ADDR_0 0x0002
795 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
796 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
797 #define EEPROM_MAC_ADDR1 0x0003
798 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
799 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
800 #define EEPROM_MAC_ADDR_2 0x0004
801 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
802 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
807 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
808 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
809 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
814 #define EEPROM_ANTENNA 0x0010
815 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
816 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
817 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
818 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
819 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
820 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
821 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
827 #define EEPROM_NIC 0x0011
828 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
835 #define EEPROM_GEOGRAPHY 0x0012
836 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
837 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
842 #define EEPROM_BBP_START 0x0013
844 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
845 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
850 #define EEPROM_TXPOWER_G_START 0x0023
852 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
853 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
858 #define EEPROM_FREQ 0x002f
859 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
860 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
861 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
875 #define EEPROM_LED 0x0030
876 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
877 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
878 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
879 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
880 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
881 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
882 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
883 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
884 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
889 #define EEPROM_TXPOWER_A_START 0x0031
891 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
892 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
897 #define EEPROM_RSSI_OFFSET_BG 0x004d
898 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
899 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
904 #define EEPROM_RSSI_OFFSET_A 0x004e
905 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
906 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
925 * Key index (0~31) to the pairwise KEY table.
926 * 0~3 to shared KEY table 0 (BSS0).
932 #define TXD_W0_BURST FIELD32(0x00000001)
933 #define TXD_W0_VALID FIELD32(0x00000002)
934 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
935 #define TXD_W0_ACK FIELD32(0x00000008)
936 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
937 #define TXD_W0_OFDM FIELD32(0x00000020)
938 #define TXD_W0_IFS FIELD32(0x00000040)
939 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
940 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
941 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
942 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
943 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
944 #define TXD_W0_BURST2 FIELD32(0x10000000)
945 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
953 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
954 #define TXD_W1_AIFSN FIELD32(0x000000f0)
955 #define TXD_W1_CWMIN FIELD32(0x00000f00)
956 #define TXD_W1_CWMAX FIELD32(0x0000f000)
957 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
958 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
959 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
964 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
965 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
966 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
967 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
972 #define TXD_W3_IV FIELD32(0xffffffff)
977 #define TXD_W4_EIV FIELD32(0xffffffff)
986 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
987 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
988 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
989 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1000 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1001 #define RXD_W0_DROP FIELD32(0x00000002)
1002 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1003 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1004 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1005 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1006 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1007 #define RXD_W0_OFDM FIELD32(0x00000080)
1008 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1009 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1010 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1011 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1018 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1019 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1020 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1021 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1027 #define RXD_W2_IV FIELD32(0xffffffff)
1033 #define RXD_W3_EIV FIELD32(0xffffffff)
1040 #define RXD_W4_ICV FIELD32(0xffffffff)
1052 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1058 #define MIN_TXPOWER 0